path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.102954                       # Number of seconds simulated
sim_ticks                                1102954033500                       # Number of ticks simulated
final_tick                               1102954033500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  66183                       # Simulator instruction rate (inst/s)
host_op_rate                                    85190                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1185337549                       # Simulator tick rate (ticks/s)
host_mem_usage                                 402972                       # Number of bytes of host memory used
host_seconds                                   930.50                       # Real time elapsed on the host
sim_insts                                    61582952                       # Number of instructions simulated
sim_ops                                      79269552                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           410112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4380532                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           404608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5226032                       # Number of bytes read from this memory
system.physmem.bytes_read::total             59181988                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       410112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       404608                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          814720                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4260416                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7287760                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6094848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           11                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6408                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68518                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6322                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             81683                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6257809                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66569                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823405                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        44207449                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           174                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              371831                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3971636                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           928                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              366840                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4738214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53657710                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         371831                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         366840                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             738671                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3862732                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              15413                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2729347                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6607492                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3862732                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       44207449                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          638                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             371831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3987049                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          928                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             366840                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7467561                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               60265202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6257809                       # Total number of read requests seen
system.physmem.writeReqs                       823405                       # Total number of write requests seen
system.physmem.cpureqs                         242034                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    400499776                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52697920                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               59181988                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7287760                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       69                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              12609                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                391396                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                391210                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                390867                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                391605                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                391533                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                390879                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                390924                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                391633                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                391393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                390703                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               390862                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               391239                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               391232                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               390529                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               390469                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               391266                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 51407                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 51229                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 51010                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51679                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51546                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50964                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50973                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51667                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 52037                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51352                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51503                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51884                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51844                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51249                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51170                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51891                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32620                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1102952897500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                     105                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6094848                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  162856                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 756836                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  66569                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    493795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    430407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    391611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1441549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1086056                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1098465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1064627                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     26919                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     24797                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     44432                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    63777                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    44227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    12032                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    11790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    15214                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     7879                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      148                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3064                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32659                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32633                       # What write queue length does an incoming req see
system.physmem.totQLat                   199184958750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              239005190000                       # Sum of mem lat for all requests
system.physmem.totBusLat                  31288700000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8531531250                       # Total cycles spent in bank access
system.physmem.avgQLat                       31830.17                       # Average queueing delay per request
system.physmem.avgBankLat                     1363.36                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  38193.53                       # Average memory access latency
system.physmem.avgRdBW                         363.12                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          47.78                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  53.66                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.61                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.21                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.22                       # Average read queue length over time
system.physmem.avgWrQLen                        10.07                       # Average write queue length over time
system.physmem.readRowHits                    6213915                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    799980                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.16                       # Row buffer hit rate for writes
system.physmem.avgGap                       155757.60                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         72561                       # number of replacements
system.l2c.tagsinuse                     53740.730134                       # Cycle average of tags in use
system.l2c.total_refs                         1839807                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        137757                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.355452                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        39373.368087                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       3.826392                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.258184                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4017.777159                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2831.337785                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       9.908379                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3708.426786                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          3795.827361                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.600790                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000058                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000004                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.061306                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.043203                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000151                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.056586                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.057920                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.820018                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        21639                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4056                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             386080                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166672                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30823                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4930                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             589304                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198131                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1401635                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          581048                       # number of Writeback hits
system.l2c.Writeback_hits::total               581048                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1122                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             742                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1864                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           191                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           146                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               337                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48001                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58894                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106895                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         21639                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4056                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              386080                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214673                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30823                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4930                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              589304                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              257025                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1508530                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        21639                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4056                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             386080                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214673                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30823                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4930                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             589304                       # number of overall hits
system.l2c.overall_hits::cpu1.data             257025                       # number of overall hits
system.l2c.overall_hits::total                1508530                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           11                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6288                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6413                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6286                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6293                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25310                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5149                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3783                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8932                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          648                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          416                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1064                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63471                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76594                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140065                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           11                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6288                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69884                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6286                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             82887                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165375                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           11                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6288                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69884                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           16                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6286                       # number of overall misses
system.l2c.overall_misses::cpu1.data            82887                       # number of overall misses
system.l2c.overall_misses::total               165375                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       728500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       187000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    351113000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    364719994                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1085000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    375250500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    394358500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1487442494                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8752489                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     11759000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     20511489                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       635500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2909999                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3545499                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3160530987                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4109769495                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7270300482                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       728500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       187000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    351113000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3525250981                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1085000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    375250500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4504127995                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8757742976                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       728500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       187000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    351113000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3525250981                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1085000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    375250500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4504127995                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8757742976                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        21650                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4059                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         392368                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         173085                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30839                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         4930                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         595590                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204424                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1426945                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       581048                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           581048                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6271                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4525                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10796                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          839                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          562                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1401                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111472                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135488                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246960                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        21650                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4059                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          392368                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284557                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30839                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         4930                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          595590                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          339912                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1673905                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        21650                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4059                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         392368                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284557                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30839                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         4930                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         595590                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         339912                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1673905                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000508                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000739                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016026                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.037051                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000519                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010554                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030784                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017737                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.821081                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836022                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.827343                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.772348                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.740214                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.759458                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.569390                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.565319                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567157                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000508                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000739                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016026                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.245589                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000519                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010554                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.243848                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098796                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000508                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000739                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016026                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.245589                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000519                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010554                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.243848                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098796                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62333.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55838.581425                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56871.977857                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 67812.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59696.229717                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 62666.216431                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 58768.964599                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1699.842494                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3108.379593                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2296.404948                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   980.709877                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6995.189904                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3332.235902                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49794.882498                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53656.546139                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 51906.618227                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55838.581425                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50444.321747                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 67812.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 59696.229717                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54340.584108                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52956.873627                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55838.581425                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50444.321747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 67812.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 59696.229717                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54340.584108                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52956.873627                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66569                       # number of writebacks
system.l2c.writebacks::total                    66569                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                74                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           11                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6283                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6375                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           16                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6279                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6269                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25236                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5149                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3783                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8932                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          648                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          416                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1064                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63471                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76594                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140065                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           11                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6283                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69846                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6279                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        82863                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165301                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           11                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6283                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69846                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           16                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6279                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        82863                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165301                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       149502                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    272716100                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    283395281                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       885015                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    296731552                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    314362700                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1168831411                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51783496                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     38465204                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     90248700                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      6527625                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4177911                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10705536                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2373885027                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3151647666                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5525532693                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       149502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    272716100                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2657280308                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       885015                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    296731552                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3466010366                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6694364104                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       591261                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       149502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    272716100                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2657280308                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       885015                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    296731552                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3466010366                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6694364104                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5286835                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12406629546                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      1838032                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667146747                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167080901160                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1050375737                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  25934678687                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  26985054424                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5286835                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13457005283                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      1838032                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180601825434                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 194065955584                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000508                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000739                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016013                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036832                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000519                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010542                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030667                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017685                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.821081                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.836022                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.827343                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.772348                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.740214                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.759458                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569390                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.565319                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567157                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000508                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000739                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016013                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.245455                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000519                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010542                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.243778                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098752                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000508                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000739                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016013                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.245455                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000519                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010542                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.243778                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098752                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        49834                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43405.395512                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44454.161725                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47257.772257                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50145.589408                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 46316.033088                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.000583                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10167.910124                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10103.974474                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.495370                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.055288                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10061.593985                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37401.096989                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41147.448442                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 39449.774697                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        49834                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43405.395512                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38044.845918                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47257.772257                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41828.202768                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40498.025444                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        53751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        49834                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43405.395512                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38044.845918                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47257.772257                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41828.202768                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40498.025444                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                5994746                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4572445                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           294986                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3765254                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2911375                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.322141                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 671631                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28577                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8900432                       # DTB read hits
system.cpu0.dtb.read_misses                     28720                       # DTB read misses
system.cpu0.dtb.write_hits                    5136537                       # DTB write hits
system.cpu0.dtb.write_misses                     5640                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1815                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1027                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   311                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8929152                       # DTB read accesses
system.cpu0.dtb.write_accesses                5142177                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14036969                       # DTB hits
system.cpu0.dtb.misses                          34360                       # DTB misses
system.cpu0.dtb.accesses                     14071329                       # DTB accesses
system.cpu0.itb.inst_hits                     4213831                       # ITB inst hits
system.cpu0.itb.inst_misses                      5055                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1341                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1480                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4218886                       # ITB inst accesses
system.cpu0.itb.hits                          4213831                       # DTB hits
system.cpu0.itb.misses                           5055                       # DTB misses
system.cpu0.itb.accesses                      4218886                       # DTB accesses
system.cpu0.numCycles                        67827180                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11769589                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      31997398                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    5994746                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3583006                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7510057                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1450935                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     59891                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              19410639                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4833                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        47194                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1299057                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          233                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4212263                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               157193                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2052                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41143300                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.004817                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.385260                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                33640645     81.76%     81.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  563027      1.37%     83.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  816788      1.99%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  677485      1.65%     86.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  772099      1.88%     88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  558236      1.36%     90.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  667723      1.62%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  351865      0.86%     92.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3095432      7.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41143300                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.088383                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.471749                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12271204                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20567331                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6814121                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               512354                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                978290                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              934838                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64553                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              39983053                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               212073                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                978290                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12839379                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5742381                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      12712172                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6708467                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2162611                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38883586                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1814                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                436137                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1233923                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents              17                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39230664                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175613245                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       175579140                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34105                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30916187                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8314476                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            411042                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        370243                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5355635                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7643947                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5684540                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1124242                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1215247                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36809311                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             895353                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37222613                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            81088                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6285112                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13160919                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256794                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41143300                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.904707                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.513127                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           26016757     63.23%     63.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5731331     13.93%     77.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3155319      7.67%     84.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2471251      6.01%     90.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2103314      5.11%     95.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             932641      2.27%     98.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             493188      1.20%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             184690      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              54809      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41143300                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  26572      2.49%      2.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   453      0.04%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                841830     78.79%     81.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               199561     18.68%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52149      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22321556     59.97%     60.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46948      0.13%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  9      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              6      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           700      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9357811     25.14%     85.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5443427     14.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37222613                       # Type of FU issued
system.cpu0.iq.rate                          0.548786                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1068416                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028703                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         116763775                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         43997708                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34321266                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8390                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4632                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3861                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38234480                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4400                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          306660                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1372064                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2343                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13106                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       537968                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2192754                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5299                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                978290                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4120588                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                98455                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37822346                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            84553                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7643947                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5684540                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571228                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39920                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 2911                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13106                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        150072                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       117309                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              267381                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             36846322                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9215739                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           376291                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       117682                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14611771                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4852307                       # Number of branches executed
system.cpu0.iew.exec_stores                   5396032                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.543238                       # Inst execution rate
system.cpu0.iew.wb_sent                      36653422                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34325127                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18280728                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35164479                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.506067                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.519863                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6092264                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         638559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           231469                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40165010                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.778528                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.739872                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28490647     70.93%     70.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5723698     14.25%     85.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1913208      4.76%     89.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       977623      2.43%     92.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       784001      1.95%     94.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       521196      1.30%     95.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       385694      0.96%     96.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       221095      0.55%     97.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1147848      2.86%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40165010                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23670535                       # Number of instructions committed
system.cpu0.commit.committedOps              31269580                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11418455                       # Number of memory references committed
system.cpu0.commit.loads                      6271883                       # Number of loads committed
system.cpu0.commit.membars                     229601                       # Number of memory barriers committed
system.cpu0.commit.branches                   4243632                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27627385                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489162                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1147848                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    75528065                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75703855                       # The number of ROB writes
system.cpu0.timesIdled                         360661                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26683880                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2138039181                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23589793                       # Number of Instructions Simulated
system.cpu0.committedOps                     31188838                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23589793                       # Number of Instructions Simulated
system.cpu0.cpi                              2.875277                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.875277                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.347793                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.347793                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               171736211                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34071636                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3249                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     898                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               12999243                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                450984                       # number of misc regfile writes
system.cpu0.icache.replacements                392403                       # number of replacements
system.cpu0.icache.tagsinuse               511.011252                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3789022                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                392915                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.643363                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6567370000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.011252                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.998069                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.998069                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3789022                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3789022                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3789022                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3789022                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3789022                       # number of overall hits
system.cpu0.icache.overall_hits::total        3789022                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       423106                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       423106                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       423106                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        423106                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       423106                       # number of overall misses
system.cpu0.icache.overall_misses::total       423106                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5802286496                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5802286496                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5802286496                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5802286496                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5802286496                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5802286496                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4212128                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4212128                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4212128                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4212128                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4212128                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4212128                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100449                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100449                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100449                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100449                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100449                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100449                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13713.552859                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13713.552859                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13713.552859                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13713.552859                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13713.552859                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4195                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              183                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.923497                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30174                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30174                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30174                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30174                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30174                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30174                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       392932                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       392932                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       392932                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       392932                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       392932                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       392932                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4748967496                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4748967496                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4748967496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4748967496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4748967496                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4748967496                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7889500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7889500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7889500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7889500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093286                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093286                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093286                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093286                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093286                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093286                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12085.977971                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12085.977971                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12085.977971                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12085.977971                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12085.977971                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12085.977971                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                275974                       # number of replacements
system.cpu0.dcache.tagsinuse               462.017037                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9251393                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                276486                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.460620                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43505000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   462.017037                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.902377                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.902377                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5774321                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5774321                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3157289                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3157289                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139126                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139126                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137035                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137035                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8931610                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8931610                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8931610                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8931610                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392659                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392659                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1582356                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1582356                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8783                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8783                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7478                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7478                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1975015                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1975015                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1975015                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1975015                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5465751000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5465751000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  60871178363                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  60871178363                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     88481000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     88481000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     46675000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     46675000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  66336929363                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  66336929363                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  66336929363                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  66336929363                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6166980                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6166980                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4739645                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4739645                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       147909                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       147909                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144513                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144513                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10906625                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10906625                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10906625                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10906625                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063671                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.063671                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333855                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.333855                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059381                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059381                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051746                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051746                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.181084                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.181084                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.181084                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.181084                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13919.841389                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13919.841389                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.700067                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38468.700067                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10074.120460                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10074.120460                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6241.642150                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6241.642150                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33588.063566                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33588.063566                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33588.063566                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33588.063566                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         8548                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         2163                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              649                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             77                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.171032                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    28.090909                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256417                       # number of writebacks
system.cpu0.dcache.writebacks::total           256417                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203981                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       203981                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1452148                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1452148                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          473                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          473                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1656129                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1656129                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1656129                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1656129                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188678                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188678                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130208                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130208                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8310                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8310                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7477                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7477                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       318886                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       318886                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       318886                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       318886                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2371660000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2371660000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4050141991                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4050141991                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     66675500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     66675500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31721000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31721000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6421801991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6421801991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6421801991                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6421801991                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13513534500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13513534500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1180320378                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1180320378                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14693854878                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14693854878                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030595                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030595                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027472                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027472                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056183                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056183                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051739                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051739                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029238                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029238                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029238                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029238                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8023.525872                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8023.525872                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4242.476929                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4242.476929                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9076266                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7463483                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           407973                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             6084116                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5247879                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            86.255407                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 773475                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             42302                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42903620                       # DTB read hits
system.cpu1.dtb.read_misses                     37068                       # DTB read misses
system.cpu1.dtb.write_hits                    6823215                       # DTB write hits
system.cpu1.dtb.write_misses                    10679                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2009                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2777                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   305                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      663                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42940688                       # DTB read accesses
system.cpu1.dtb.write_accesses                6833894                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49726835                       # DTB hits
system.cpu1.dtb.misses                          47747                       # DTB misses
system.cpu1.dtb.accesses                     49774582                       # DTB accesses
system.cpu1.itb.inst_hits                     8394995                       # ITB inst hits
system.cpu1.itb.inst_misses                      5378                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1532                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1500                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8400373                       # ITB inst accesses
system.cpu1.itb.hits                          8394995                       # DTB hits
system.cpu1.itb.misses                           5378                       # DTB misses
system.cpu1.itb.accesses                      8400373                       # DTB accesses
system.cpu1.numCycles                       408777731                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19817241                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      66077936                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9076266                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6021354                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14149044                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3958978                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     63415                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              75978247                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                4643                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42826                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1407438                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          103                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8393192                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               739597                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2716                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         114161892                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.700766                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.044841                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               100020305     87.61%     87.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  795953      0.70%     88.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  939001      0.82%     89.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1889167      1.65%     90.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1518004      1.33%     92.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  578108      0.51%     92.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2132011      1.87%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  410005      0.36%     94.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5879338      5.15%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           114161892                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022203                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.161648                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                21336269                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             76905312                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12792890                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               524784                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2602637                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1103950                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                97871                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              75228090                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               324995                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2602637                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22719770                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31941572                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      40729697                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11839035                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4329181                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              69767929                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                18791                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                669754                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3086107                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             334                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           73761871                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            321211401                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       321151882                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            59519                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49052831                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                24709040                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            445091                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        388163                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7873081                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            13208830                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8144792                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1029727                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1553546                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  63522315                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1158429                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 89134167                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            94409                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       16267434                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     45777798                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        277724                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    114161892                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.780770                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.519105                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           83758719     73.37%     73.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8417078      7.37%     80.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4293584      3.76%     84.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3776789      3.31%     87.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10574202      9.26%     97.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1966117      1.72%     98.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1029866      0.90%     99.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             271331      0.24%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              74206      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      114161892                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  32060      0.41%      0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   998      0.01%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7549280     95.84%     96.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               294896      3.74%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           313932      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37620086     42.21%     42.56% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59138      0.07%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 13      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1510      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.63% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43968936     49.33%     91.96% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7170532      8.04%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              89134167                       # Type of FU issued
system.cpu1.iq.rate                          0.218050                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7877234                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088375                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         300434418                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         80956642                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     53641825                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15018                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8136                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6869                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96689561                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7908                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          342287                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3455090                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3893                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17135                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1305851                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31905929                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       888458                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2602637                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               24185109                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               359685                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           64785366                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           111899                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             13208830                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8144792                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            869085                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 64974                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3561                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17135                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        202123                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       154728                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              356851                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             86703480                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43273897                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2430687                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104622                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50383100                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 6997981                       # Number of branches executed
system.cpu1.iew.exec_stores                   7109203                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.212104                       # Inst execution rate
system.cpu1.iew.wb_sent                      85724428                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     53648694                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 29926721                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 53389506                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131242                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.560536                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       16147511                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         880705                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           311675                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    111559255                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.431612                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.399673                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     94810700     84.99%     84.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8240774      7.39%     92.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2114811      1.90%     94.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1254575      1.12%     95.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1245157      1.12%     96.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       568382      0.51%     97.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       999815      0.90%     97.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       505524      0.45%     98.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1819517      1.63%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    111559255                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38062798                       # Number of instructions committed
system.cpu1.commit.committedOps              48150353                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16592681                       # Number of memory references committed
system.cpu1.commit.loads                      9753740                       # Number of loads committed
system.cpu1.commit.membars                     190132                       # Number of memory barriers committed
system.cpu1.commit.branches                   5967363                       # Number of branches committed
system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42685619                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              534609                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1819517                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   172993511                       # The number of ROB reads
system.cpu1.rob.rob_writes                  131291211                       # The number of ROB writes
system.cpu1.timesIdled                        1408204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      294615839                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1796493799                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   37993159                       # Number of Instructions Simulated
system.cpu1.committedOps                     48080714                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             37993159                       # Number of Instructions Simulated
system.cpu1.cpi                             10.759246                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.759246                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092943                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092943                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               387964882                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56217113                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4997                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2346                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               18468785                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                405479                       # number of misc regfile writes
system.cpu1.icache.replacements                595625                       # number of replacements
system.cpu1.icache.tagsinuse               480.695488                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7752260                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                596137                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 13.004158                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74233129000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   480.695488                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.938858                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.938858                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      7752260                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7752260                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7752260                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7752260                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7752260                       # number of overall hits
system.cpu1.icache.overall_hits::total        7752260                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       640881                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       640881                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       640881                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        640881                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       640881                       # number of overall misses
system.cpu1.icache.overall_misses::total       640881                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8621805995                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8621805995                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8621805995                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8621805995                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8621805995                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8621805995                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      8393141                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8393141                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      8393141                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8393141                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      8393141                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8393141                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.076358                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.076358                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.076358                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.076358                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.076358                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.076358                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.052899                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.052899                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.052899                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13453.052899                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.052899                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13453.052899                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         2044                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              172                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.883721                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        44715                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        44715                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        44715                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        44715                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        44715                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        44715                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       596166                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       596166                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       596166                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       596166                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       596166                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       596166                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7061200496                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7061200496                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7061200496                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7061200496                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7061200496                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7061200496                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2836500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2836500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2836500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      2836500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071030                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071030                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071030                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.071030                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071030                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.071030                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.352908                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.352908                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.352908                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.352908                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.352908                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.352908                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                360596                       # number of replacements
system.cpu1.dcache.tagsinuse               474.658932                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                12676805                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                360947                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 35.120960                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           70362477000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   474.658932                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.927068                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.927068                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8309067                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8309067                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4139347                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4139347                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        97521                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        97521                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        94873                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        94873                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12448414                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12448414                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12448414                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12448414                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       400056                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       400056                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1556122                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1556122                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13956                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13956                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10608                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10608                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1956178                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1956178                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1956178                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1956178                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6114203000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6114203000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  61457337496                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  61457337496                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    130378000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    130378000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     53868000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     53868000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  67571540496                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  67571540496                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  67571540496                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  67571540496                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8709123                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8709123                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5695469                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5695469                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       111477                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       111477                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105481                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       105481                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14404592                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14404592                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14404592                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14404592                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045935                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045935                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.273221                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.273221                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125192                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125192                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100568                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100568                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135802                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135802                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135802                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135802                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15283.367829                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15283.367829                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39493.906966                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39493.906966                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9342.075093                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9342.075093                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5078.054299                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5078.054299                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34542.633899                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 34542.633899                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34542.633899                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 34542.633899                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        26379                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        12882                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3330                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            156                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.921622                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    82.576923                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       324632                       # number of writebacks
system.cpu1.dcache.writebacks::total           324632                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171788                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       171788                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1394549                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1394549                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1443                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1443                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1566337                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1566337                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1566337                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1566337                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       228268                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       228268                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161573                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161573                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12513                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12513                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10605                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10605                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       389841                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       389841                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       389841                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       389841                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2854852000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2854852000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5117226213                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5117226213                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89555500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89555500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32658000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32658000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7972078213                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7972078213                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7972078213                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7972078213                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989815500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  35679552148                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  35679552148                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204669367648                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204669367648                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026210                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026210                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028369                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028369                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112247                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112247                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100539                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100539                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027064                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027064                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027064                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027064                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7156.996723                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7156.996723                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3079.490806                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3079.490806                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 540125454155                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   41707                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   48865                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------