path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.104766                       # Number of seconds simulated
sim_ticks                                1104765949000                       # Number of ticks simulated
final_tick                               1104765949000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  62642                       # Simulator instruction rate (inst/s)
host_op_rate                                    80640                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1123477436                       # Simulator tick rate (ticks/s)
host_mem_usage                                 430892                       # Number of bytes of host memory used
host_seconds                                   983.35                       # Real time elapsed on the host
sim_insts                                    61598253                       # Number of instructions simulated
sim_ops                                      79296895                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           408192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4366132                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           406848                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5251248                       # Number of bytes read from this memory
system.physmem.bytes_read::total             59192932                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       408192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       406848                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          815040                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4268480                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7295824                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6094848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6378                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68293                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6357                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82077                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6257980                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66695                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823531                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        44134945                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           174                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              369483                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3952088                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           637                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              368266                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4753267                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53579613                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         369483                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         368266                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             737749                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3863696                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              15388                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2724870                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6603954                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3863696                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       44134945                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          753                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             369483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3967476                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             368266                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7478138                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               60183567                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6257980                       # Number of read requests accepted
system.physmem.writeReqs                       823531                       # Number of write requests accepted
system.physmem.readBursts                     6257980                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     823531                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                398200448                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2310272                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7402624                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  59192932                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7295824                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    36098                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  707850                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12605                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              391110                       # Per bank write bursts
system.physmem.perBankRdBursts::1              390863                       # Per bank write bursts
system.physmem.perBankRdBursts::2              386866                       # Per bank write bursts
system.physmem.perBankRdBursts::3              386878                       # Per bank write bursts
system.physmem.perBankRdBursts::4              391778                       # Per bank write bursts
system.physmem.perBankRdBursts::5              391417                       # Per bank write bursts
system.physmem.perBankRdBursts::6              386925                       # Per bank write bursts
system.physmem.perBankRdBursts::7              386783                       # Per bank write bursts
system.physmem.perBankRdBursts::8              391442                       # Per bank write bursts
system.physmem.perBankRdBursts::9              391216                       # Per bank write bursts
system.physmem.perBankRdBursts::10             386574                       # Per bank write bursts
system.physmem.perBankRdBursts::11             385570                       # Per bank write bursts
system.physmem.perBankRdBursts::12             390981                       # Per bank write bursts
system.physmem.perBankRdBursts::13             390596                       # Per bank write bursts
system.physmem.perBankRdBursts::14             386700                       # Per bank write bursts
system.physmem.perBankRdBursts::15             386183                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7188                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7193                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7297                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7231                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7835                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7450                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7370                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7176                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7508                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7517                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6849                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6596                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7160                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6824                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7287                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7185                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1104764856500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     105                       # Read request sizes (log2)
system.physmem.readPktSize::3                 6094848                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  163027                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66695                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    548369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    494073                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    445478                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1468713                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1058783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1047686                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1043195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     25365                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     25416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      9815                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     9549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     9391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     9130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     8948                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     8825                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     8725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5769                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        71125                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean     5702.673097                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     368.783347                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   12967.835637                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          25909     36.43%     36.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14850     20.88%     57.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         3162      4.45%     61.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2234      3.14%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1545      2.17%     67.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1302      1.83%     68.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          996      1.40%     70.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519         1191      1.67%     71.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          629      0.88%     72.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          663      0.93%     73.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          567      0.80%     74.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          536      0.75%     75.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          288      0.40%     75.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          263      0.37%     76.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          175      0.25%     76.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          373      0.52%     76.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          125      0.18%     77.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          132      0.19%     77.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223           91      0.13%     77.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          197      0.28%     77.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351           57      0.08%     77.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415          541      0.76%     78.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479           41      0.06%     78.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          225      0.32%     78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           27      0.04%     78.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671          110      0.15%     79.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           22      0.03%     79.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799          111      0.16%     79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           16      0.02%     79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           61      0.09%     79.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           13      0.02%     79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          267      0.38%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119           16      0.02%     79.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           40      0.06%     79.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           17      0.02%     79.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311           50      0.07%     79.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375           11      0.02%     79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           22      0.03%     79.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503            7      0.01%     79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567           43      0.06%     80.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631            4      0.01%     80.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           15      0.02%     80.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759            8      0.01%     80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823           32      0.04%     80.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887            7      0.01%     80.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           30      0.04%     80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015            5      0.01%     80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          157      0.22%     80.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143            6      0.01%     80.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           17      0.02%     80.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            2      0.00%     80.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335           36      0.05%     80.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399            9      0.01%     80.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           17      0.02%     80.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527            7      0.01%     80.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591           88      0.12%     80.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655            7      0.01%     80.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           27      0.04%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783            8      0.01%     80.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847           39      0.05%     80.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911            6      0.01%     80.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           18      0.03%     80.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039            4      0.01%     80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          181      0.25%     81.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            9      0.01%     81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           12      0.02%     81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295           12      0.02%     81.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359          102      0.14%     81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423           17      0.02%     81.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           25      0.04%     81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551            7      0.01%     81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615           11      0.02%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679            5      0.01%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743            3      0.00%     81.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807           10      0.01%     81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871           19      0.03%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            2      0.00%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999            6      0.01%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063            5      0.01%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          161      0.23%     81.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            6      0.01%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           13      0.02%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            9      0.01%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383           14      0.02%     81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447            3      0.00%     81.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511           16      0.02%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575            3      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639           18      0.03%     81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            5      0.01%     81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767            8      0.01%     81.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            5      0.01%     81.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895          150      0.21%     81.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            2      0.00%     81.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023           12      0.02%     82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087           13      0.02%     82.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151           95      0.13%     82.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            7      0.01%     82.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279            6      0.01%     82.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407           23      0.03%     82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471            4      0.01%     82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535           11      0.02%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            3      0.00%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663          112      0.16%     82.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727            9      0.01%     82.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791           20      0.03%     82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855            8      0.01%     82.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           28      0.04%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983            5      0.01%     82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047            4      0.01%     82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111            2      0.00%     82.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175           94      0.13%     82.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303            6      0.01%     82.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367           10      0.01%     82.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431           92      0.13%     82.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495            3      0.00%     82.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559           10      0.01%     82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            3      0.00%     82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687           20      0.03%     82.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7751            2      0.00%     82.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815            2      0.00%     82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7879            4      0.01%     82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           30      0.04%     82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007            6      0.01%     82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071            8      0.01%     82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8135            1      0.00%     82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          249      0.35%     83.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8327            1      0.00%     83.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           31      0.04%     83.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8647            1      0.00%     83.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711           16      0.02%     83.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8839            3      0.00%     83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8903            1      0.00%     83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967           75      0.11%     83.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095            1      0.00%     83.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223           93      0.13%     83.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9415            1      0.00%     83.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           20      0.03%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9607            1      0.00%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735          102      0.14%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9863            1      0.00%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927            1      0.00%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991           14      0.02%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119            3      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247           94      0.13%     83.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10375            1      0.00%     83.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503           94      0.13%     84.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759           15      0.02%     84.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10816-10823            1      0.00%     84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10887            1      0.00%     84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015            6      0.01%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11079            2      0.00%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143            1      0.00%     84.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          147      0.21%     84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11335            3      0.00%     84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527           15      0.02%     84.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591            1      0.00%     84.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783            1      0.00%     84.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11847            1      0.00%     84.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911            1      0.00%     84.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039           79      0.11%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12103            1      0.00%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12231            1      0.00%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          162      0.23%     84.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423            1      0.00%     84.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551           20      0.03%     84.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679            1      0.00%     84.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12743            1      0.00%     84.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807           68      0.10%     84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12871            1      0.00%     84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12935            1      0.00%     84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063           20      0.03%     84.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191            1      0.00%     84.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          148      0.21%     85.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13447            1      0.00%     85.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13511            1      0.00%     85.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575           19      0.03%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13703            1      0.00%     85.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831           18      0.03%     85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087           11      0.02%     85.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          228      0.32%     85.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599           27      0.04%     85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           14      0.02%     85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14919            1      0.00%     85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14983            1      0.00%     85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           73      0.10%     85.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15175            2      0.00%     85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          145      0.20%     85.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           10      0.01%     85.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15687            1      0.00%     85.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15751            1      0.00%     85.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879           20      0.03%     85.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16071            1      0.00%     85.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135           17      0.02%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263            1      0.00%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16327            1      0.00%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          273      0.38%     86.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16455            1      0.00%     86.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519            1      0.00%     86.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647           20      0.03%     86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16711            1      0.00%     86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903           21      0.03%     86.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           13      0.02%     86.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287            1      0.00%     86.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17351            1      0.00%     86.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          156      0.22%     86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479            2      0.00%     86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17543            1      0.00%     86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           80      0.11%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799            1      0.00%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17863            1      0.00%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           14      0.02%     86.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183           31      0.04%     86.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247            2      0.00%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311            1      0.00%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18375            1      0.00%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          219      0.31%     87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503            1      0.00%     87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695            6      0.01%     87.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18752-18759            1      0.00%     87.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951           15      0.02%     87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19008-19015            1      0.00%     87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079            4      0.01%     87.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207           13      0.02%     87.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19264-19271            1      0.00%     87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          140      0.20%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19584-19591            1      0.00%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19648-19655            1      0.00%     87.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719           17      0.02%     87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19840-19847            2      0.00%     87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975           68      0.10%     87.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20032-20039            1      0.00%     87.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20096-20103            1      0.00%     87.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231           17      0.02%     87.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359            2      0.00%     87.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423            1      0.00%     87.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          157      0.22%     87.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743           82      0.12%     87.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999            4      0.01%     87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255           14      0.02%     87.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383            2      0.00%     87.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447            2      0.00%     87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          145      0.20%     88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21632-21639            1      0.00%     88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21696-21703            1      0.00%     88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767            4      0.01%     88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21824-21831            1      0.00%     88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21895            1      0.00%     88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023           14      0.02%     88.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151            2      0.00%     88.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279           92      0.13%     88.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407            1      0.00%     88.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22464-22471            2      0.00%     88.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535           85      0.12%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791           14      0.02%     88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22848-22855            1      0.00%     88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047          102      0.14%     88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23104-23111            2      0.00%     88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23232-23239            1      0.00%     88.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           21      0.03%     88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23488-23495            1      0.00%     88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559           91      0.13%     88.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23616-23623            1      0.00%     88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23744-23751            4      0.01%     88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815           75      0.11%     88.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23872-23879            2      0.00%     88.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24000-24007            1      0.00%     88.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071           21      0.03%     88.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           31      0.04%     88.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455            1      0.00%     88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24512-24519            1      0.00%     88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          139      0.20%     89.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24704-24711            1      0.00%     89.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24775            1      0.00%     89.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839           29      0.04%     89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24896-24903            2      0.00%     89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095           18      0.03%     89.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25280-25287            1      0.00%     89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351           77      0.11%     89.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479            2      0.00%     89.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607           90      0.13%     89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           19      0.03%     89.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119          104      0.15%     89.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375           14      0.02%     89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503            1      0.00%     89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631           87      0.12%     89.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823            2      0.00%     89.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887           94      0.13%     89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143           12      0.02%     89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27200-27207            1      0.00%     89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27264-27271            2      0.00%     89.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27328-27335            1      0.00%     89.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399            5      0.01%     89.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            1      0.00%     89.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591            1      0.00%     89.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          143      0.20%     90.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27776-27783            1      0.00%     90.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911           16      0.02%     90.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27968-27975            2      0.00%     90.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167            5      0.01%     90.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28224-28231            2      0.00%     90.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423           82      0.12%     90.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28480-28487            1      0.00%     90.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551            1      0.00%     90.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          157      0.22%     90.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28743            2      0.00%     90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807            1      0.00%     90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28864-28871            1      0.00%     90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935           22      0.03%     90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127            2      0.00%     90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191           67      0.09%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29376-29383            1      0.00%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447           16      0.02%     90.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511            1      0.00%     90.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            3      0.00%     90.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          139      0.20%     90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831            3      0.00%     90.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959           13      0.02%     90.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30016-30023            1      0.00%     90.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30080-30087            2      0.00%     90.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215           17      0.02%     90.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279            4      0.01%     90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471           11      0.02%     90.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30528-30535            2      0.00%     90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            1      0.00%     90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30656-30663            1      0.00%     90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          213      0.30%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855            2      0.00%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30912-30919            2      0.00%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983           26      0.04%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31047            1      0.00%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31168-31175            1      0.00%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           17      0.02%     91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367            1      0.00%     91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           70      0.10%     91.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623            1      0.00%     91.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          147      0.21%     91.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31808-31815            1      0.00%     91.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31872-31879            1      0.00%     91.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           14      0.02%     91.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32064-32071            1      0.00%     91.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135            1      0.00%     91.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263           20      0.03%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32320-32327            1      0.00%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391            2      0.00%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32448-32455            1      0.00%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519           14      0.02%     91.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647            1      0.00%     91.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32704-32711            1      0.00%     91.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          271      0.38%     91.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031           14      0.02%     91.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287           20      0.03%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415            1      0.00%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           20      0.03%     92.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33607            1      0.00%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            4      0.01%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33735            1      0.00%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          153      0.22%     92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33856-33863            1      0.00%     92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           71      0.10%     92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34119            1      0.00%     92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34176-34183            1      0.00%     92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           15      0.02%     92.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34368-34375            1      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439            2      0.00%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567           26      0.04%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34624-34631            2      0.00%     92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          211      0.30%     92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079            7      0.01%     92.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335           15      0.02%     92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463            1      0.00%     92.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591           13      0.02%     92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          136      0.19%     92.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36032-36039            1      0.00%     92.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103           19      0.03%     93.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36288-36295            1      0.00%     93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359           67      0.09%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36487            1      0.00%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615           18      0.03%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36736-36743            1      0.00%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          155      0.22%     93.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127           79      0.11%     93.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319            1      0.00%     93.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383            3      0.00%     93.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37440-37447            1      0.00%     93.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37568-37575            1      0.00%     93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639           12      0.02%     93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37696-37703            1      0.00%     93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          140      0.20%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38016-38023            1      0.00%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151            3      0.00%     93.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407           13      0.02%     93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535            1      0.00%     93.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663           93      0.13%     93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919           85      0.12%     93.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175           15      0.02%     93.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39360-39367            2      0.00%     93.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431          104      0.15%     94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39623            1      0.00%     94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           19      0.03%     94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943           90      0.13%     94.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199           75      0.11%     94.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455           16      0.02%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583            2      0.00%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           30      0.04%     94.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40832-40839            1      0.00%     94.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          138      0.19%     94.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223           29      0.04%     94.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41280-41287            1      0.00%     94.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479           18      0.03%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41536-41543            1      0.00%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607            1      0.00%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41664-41671            1      0.00%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735           74      0.10%     94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41792-41799            2      0.00%     94.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41920-41927            2      0.00%     94.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991           90      0.13%     94.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42176-42183            1      0.00%     94.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           19      0.03%     94.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503           98      0.14%     95.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42695            1      0.00%     95.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759           15      0.02%     95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42816-42823            1      0.00%     95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42880-42887            2      0.00%     95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015           82      0.12%     95.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43200-43207            1      0.00%     95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271           90      0.13%     95.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43392-43399            1      0.00%     95.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527           12      0.02%     95.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43712-43719            1      0.00%     95.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783            4      0.01%     95.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          144      0.20%     95.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103            2      0.00%     95.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295           12      0.02%     95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423            2      0.00%     95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44480-44487            1      0.00%     95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551            5      0.01%     95.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807           85      0.12%     95.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          155      0.22%     95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45120-45127            1      0.00%     95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191            1      0.00%     95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319           16      0.02%     96.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45440-45447            1      0.00%     96.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45504-45511            2      0.00%     96.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575           71      0.10%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45639            2      0.00%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45760-45767            1      0.00%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831           19      0.03%     96.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45888-45895            1      0.00%     96.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          138      0.19%     96.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46144-46151            1      0.00%     96.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343           14      0.02%     96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46528-46535            1      0.00%     96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599           15      0.02%     96.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855           10      0.01%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47040-47047            1      0.00%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          214      0.30%     96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367           31      0.04%     96.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47424-47431            1      0.00%     96.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495            1      0.00%     96.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           15      0.02%     96.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47680-47687            1      0.00%     96.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           70      0.10%     96.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007            1      0.00%     96.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          146      0.21%     97.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391           10      0.01%     97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647           20      0.03%     97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775           13      0.02%     97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48832-48839            2      0.00%     97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903           13      0.02%     97.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            5      0.01%     97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            2      0.00%     97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         1979      2.78%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49216-49223            1      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49728-49735            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49792-49799            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50183            2      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50368-50375            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50432-50439            2      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50695            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50752-50759            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50880-50887            4      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50944-50951            3      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51008-51015            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51207            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51264-51271            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51328-51335            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51648-51655            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51712-51719            3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52160-52167            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52352-52359            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52672-52679            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          71125                       # Bytes accessed per row activation
system.physmem.totQLat                   151840872500                       # Total ticks spent queuing
system.physmem.totMemAccLat              191562815000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  31109410000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  8612532500                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24404.33                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1384.23                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30788.56                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         360.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.70                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       53.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.60                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.06                       # Average write queue length when enqueuing
system.physmem.readRowHits                    6168484                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97939                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.14                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.66                       # Row buffer hit rate for writes
system.physmem.avgGap                       156006.94                       # Average gap between requests
system.physmem.pageHitRate                      98.88                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               3.92                       # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     62369736                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7306752                       # Transaction distribution
system.membus.trans_dist::ReadResp            7306752                       # Transaction distribution
system.membus.trans_dist::WriteReq             767894                       # Transaction distribution
system.membus.trans_dist::WriteResp            767894                       # Transaction distribution
system.membus.trans_dist::Writeback             66695                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            33888                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          17695                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12605                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138070                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137680                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382518                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          842                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971209                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4366229                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12189696                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12189696                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               16555925                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389781                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        23284                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1684                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17729972                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20145177                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            68903961                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               68903961                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487006499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             9880000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy              749500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy          8612723499                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4837509170                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        13760375954                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
system.l2c.tags.replacements                    72740                       # number of replacements
system.l2c.tags.tagsinuse                53853.567584                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1839137                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   137924                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.334423                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   39512.680536                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.162068                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.257969                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4009.847433                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2829.767621                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.955070                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3709.355619                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3778.541270                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.602916                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000079                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.061185                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043179                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000121                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.056600                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.057656                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.821740                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        22065                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             386342                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166614                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30647                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5089                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             590258                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198399                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1403772                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          581386                       # number of Writeback hits
system.l2c.Writeback_hits::total               581386                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1334                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             750                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2084                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           191                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           137                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               328                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48317                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58643                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106960                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         22065                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              386342                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214931                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30647                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5089                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              590258                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              257042                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1510732                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        22065                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4358                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             386342                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214931                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30647                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5089                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             590258                       # number of overall hits
system.l2c.overall_hits::cpu1.data             257042                       # number of overall hits
system.l2c.overall_hits::total                1510732                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           13                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6260                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6384                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           11                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6325                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6267                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25263                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5164                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3801                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8965                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          637                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          413                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1050                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63263                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          77007                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140270                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6260                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69647                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           11                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6325                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83274                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165533                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6260                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69647                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           11                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6325                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83274                       # number of overall misses
system.l2c.overall_misses::total               165533                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1016250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       477500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    449841750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    482248247                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       862750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    476239250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    488675250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1899360997                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8963096                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12325976                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21289072                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       488979                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2955872                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3444851                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4446470608                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   6273738055                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10720208663                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1016250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       477500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    449841750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4928718855                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       862750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    476239250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6762413305                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12619569660                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1016250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       477500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    449841750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4928718855                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       862750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    476239250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6762413305                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12619569660                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        22078                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4361                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         392602                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         172998                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30658                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5089                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         596583                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204666                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1429035                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       581386                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           581386                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6498                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4551                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           11049                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          828                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          550                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1378                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111580                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       135650                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247230                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        22078                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4361                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          392602                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          284578                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30658                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5089                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          596583                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          340316                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1676265                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        22078                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4361                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         392602                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         284578                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30658                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5089                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         596583                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         340316                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1676265                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000589                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000688                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015945                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036902                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000359                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010602                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030621                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017678                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.794706                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.835201                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.811386                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.769324                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.750909                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.761974                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.566974                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.567689                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.567366                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000589                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000688                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015945                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244738                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000359                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010602                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.244696                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098751                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000589                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000688                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015945                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244738                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000359                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010602                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.244696                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098751                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78173.076923                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 159166.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71859.704473                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 75540.138941                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78431.818182                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75294.743083                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77975.945428                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 75183.509362                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1735.688613                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3242.824520                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2374.687340                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   767.627943                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7157.075061                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3280.810476                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70285.484533                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81469.711260                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76425.526934                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78173.076923                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 159166.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 71859.704473                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70767.137924                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78431.818182                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75294.743083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81206.778887                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 76235.975062                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78173.076923                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 159166.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 71859.704473                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70767.137924                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78431.818182                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75294.743083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81206.778887                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 76235.975062                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66695                       # number of writebacks
system.l2c.writebacks::total                    66695                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            27                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                77                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             27                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 77                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            27                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                77                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6257                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6345                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           11                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6317                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6240                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25186                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5164                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3801                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8965                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          637                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          413                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1050                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63263                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        77007                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140270                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6257                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69608                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           11                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6317                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83247                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165456                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6257                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69608                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           11                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6317                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83247                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165456                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       853750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       440500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    370880500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    400730997                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       728750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    396408250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    408765250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1578807997                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     51771606                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     38348722                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     90120328                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      6378635                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4156405                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10535040                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3652529888                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5315357439                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8967887327                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       853750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       440500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    370880500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4053260885                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       728750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    396408250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5724122689                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10546695324                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       853750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       440500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    370880500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4053260885                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       728750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    396408250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5724122689                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10546695324                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6382249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12399939239                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2397749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603749244                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167012468481                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1006407999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16511968075                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17518376074                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6382249                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13406347238                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2397749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171115717319                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184530844555                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000589                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000688                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015937                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036677                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000359                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010589                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030489                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017624                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.794706                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.835201                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.811386                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.769324                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.750909                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.761974                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.566974                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.567689                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.567366                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000589                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000688                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015937                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244601                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000359                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010589                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.244617                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.098705                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000589                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000688                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015937                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244601                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000359                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010589                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.244617                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.098705                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        66250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        66250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 63743.202567                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        66250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 63743.202567                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   136691596                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2708551                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2708550                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767894                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767894                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           581386                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           33382                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         18023                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          51405                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           258959                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          258959                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       785985                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073715                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        13547                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        55934                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1193885                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4802054                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        14684                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        71694                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8011498                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25134272                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34847315                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        17444                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        88312                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     38184256                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     47797126                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        20356                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       122632                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          146211713                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             146211713                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4800508                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4894625900                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1771371395                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1514575770                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9208452                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          34011429                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy        2689519761                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy        3237226447                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           9617950                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy          41300207                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      46298101                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7278157                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7278157                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7950                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7950                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30460                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8022                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          724                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          494                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382518                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12189696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12189696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                14572214                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40178                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16044                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1448                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          271                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2389781                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     48758784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             51148565                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                51148565                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21360000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4017000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               368000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               297000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6094848000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374568000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         16664438046                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6002691                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4577903                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           294712                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3771820                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2913648                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.247801                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 672509                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28479                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8905508                       # DTB read hits
system.cpu0.dtb.read_misses                     28991                       # DTB read misses
system.cpu0.dtb.write_hits                    5140500                       # DTB write hits
system.cpu0.dtb.write_misses                     5723                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1824                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      969                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   309                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      556                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8934499                       # DTB read accesses
system.cpu0.dtb.write_accesses                5146223                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14046008                       # DTB hits
system.cpu0.dtb.misses                          34714                       # DTB misses
system.cpu0.dtb.accesses                     14080722                       # DTB accesses
system.cpu0.itb.inst_hits                     4219281                       # ITB inst hits
system.cpu0.itb.inst_misses                      5089                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1343                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1465                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4224370                       # ITB inst accesses
system.cpu0.itb.hits                          4219281                       # DTB hits
system.cpu0.itb.misses                           5089                       # DTB misses
system.cpu0.itb.accesses                      4224370                       # DTB accesses
system.cpu0.numCycles                        69432037                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11713503                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32019404                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6002691                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3586157                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7516730                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1449804                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     61386                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              19631994                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                4874                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        46872                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1335943                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          243                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4217707                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               157539                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2075                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41351812                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.000563                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.381156                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                33842541     81.84%     81.84% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  565579      1.37%     83.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  816874      1.98%     85.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  676358      1.64%     86.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  772843      1.87%     88.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  558608      1.35%     90.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  669211      1.62%     91.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  351371      0.85%     92.51% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3098427      7.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41351812                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.086454                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.461162                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12216999                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20826551                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6820783                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               510850                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                976629                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              935170                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64759                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40012064                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213022                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                976629                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12786291                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5985032                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      12800887                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6711570                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2091403                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              38907337                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1875                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                435425                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1163203                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             107                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           39252215                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            175728295                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       161804372                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             3955                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30935092                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8317122                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            411284                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        370379                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5367119                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7645996                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5688511                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1121166                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1220161                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  36823164                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             895382                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37236653                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            80347                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6279547                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13158300                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256522                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41351812                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.900484                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.514831                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           26282952     63.56%     63.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5688374     13.76%     77.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3116432      7.54%     84.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2466494      5.96%     90.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2112034      5.11%     95.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             939185      2.27%     98.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             506930      1.23%     99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             184996      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              54415      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41351812                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  27736      2.59%      2.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   453      0.04%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                842113     78.49%     81.12% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               202594     18.88%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52214      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22326150     59.96%     60.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46947      0.13%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  7      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 1      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              4      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           700      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9362954     25.14%     85.37% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5447671     14.63%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37236653                       # Type of FU issued
system.cpu0.iq.rate                          0.536304                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1072896                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028813                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         117004426                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         44005967                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34332716                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8422                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4624                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3857                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38252914                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4421                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          307648                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1368398                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2491                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13086                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       537466                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2192854                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5939                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                976629                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4337522                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               100010                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           37836354                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            83498                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7645996                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5688511                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571219                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39755                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 6621                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13086                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        149491                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       117486                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              266977                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             36859042                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9220953                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           377611                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       117808                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14621413                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4853789                       # Number of branches executed
system.cpu0.iew.exec_stores                   5400460                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.530865                       # Inst execution rate
system.cpu0.iew.wb_sent                      36664720                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34336573                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18306413                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35193198                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.494535                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.520169                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6085996                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         638860                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           231074                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40375183                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.775004                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.739173                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28737053     71.18%     71.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5697190     14.11%     85.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1882101      4.66%     89.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       980199      2.43%     92.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       786708      1.95%     94.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       526531      1.30%     95.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       398386      0.99%     96.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       216969      0.54%     97.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1150046      2.85%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40375183                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            23683551                       # Number of instructions committed
system.cpu0.commit.committedOps              31290943                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11428643                       # Number of memory references committed
system.cpu0.commit.loads                      6277598                       # Number of loads committed
system.cpu0.commit.membars                     229694                       # Number of memory barriers committed
system.cpu0.commit.branches                   4245889                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 27646853                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              489416                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1150046                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    75750709                       # The number of ROB reads
system.cpu0.rob.rob_writes                   75732466                       # The number of ROB writes
system.cpu0.timesIdled                         364061                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       28080225                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2140058132                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23602809                       # Number of Instructions Simulated
system.cpu0.committedOps                     31210201                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             23602809                       # Number of Instructions Simulated
system.cpu0.cpi                              2.941685                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.941685                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.339941                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.339941                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               171807193                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34081987                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3237                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     886                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               13003191                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                451099                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           392605                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.965142                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            3793600                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           393117                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.650053                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7051834000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.965142                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997979                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3793600                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3793600                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3793600                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3793600                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3793600                       # number of overall hits
system.cpu0.icache.overall_hits::total        3793600                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       423979                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       423979                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       423979                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        423979                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       423979                       # number of overall misses
system.cpu0.icache.overall_misses::total       423979                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5892352014                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5892352014                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5892352014                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5892352014                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5892352014                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5892352014                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4217579                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4217579                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4217579                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4217579                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4217579                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4217579                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100527                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100527                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100527                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100527                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100527                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100527                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13897.744969                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13897.744969                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3802                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              164                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.182927                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30839                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30839                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30839                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30839                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30839                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30839                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       393140                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       393140                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       393140                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       393140                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       393140                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       393140                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4794002596                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4794002596                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4794002596                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4794002596                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4794002596                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4794002596                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8923000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8923000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8923000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      8923000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093215                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093215                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093215                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093215                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093215                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093215                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           276287                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          459.684046                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9258198                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           276799                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            33.447368                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         43491250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   459.684046                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.897820                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.897820                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5778274                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5778274                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3158747                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3158747                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139141                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139141                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137092                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137092                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8937021                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8937021                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8937021                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8937021                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       392090                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       392090                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1584925                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1584925                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8730                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8730                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7451                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7451                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1977015                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1977015                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1977015                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1977015                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5539255201                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5539255201                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  79907349135                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  79907349135                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     90050735                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     90050735                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45818635                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     45818635                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  85446604336                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  85446604336                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  85446604336                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  85446604336                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6170364                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6170364                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4743672                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4743672                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       147871                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       147871                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144543                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144543                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10914036                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     10914036                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10914036                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     10914036                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063544                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.063544                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.334114                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.334114                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059038                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059038                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051549                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051549                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.181144                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.181144                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.181144                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.181144                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6149.326936                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6149.326936                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9481                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        10276                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              609                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            131                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.568144                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    78.442748                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       256484                       # number of writebacks
system.cpu0.dcache.writebacks::total           256484                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203289                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       203289                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1454440                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1454440                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          445                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          445                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1657729                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1657729                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1657729                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1657729                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188801                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188801                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130485                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130485                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7449                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7449                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       319286                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       319286                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       319286                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       319286                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2419086873                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2419086873                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5310990170                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5310990170                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     68672765                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     68672765                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     30919365                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     30919365                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7730077043                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7730077043                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7730077043                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7730077043                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13504888791                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13504888791                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1131913883                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1131913883                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14636802674                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14636802674                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030598                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030598                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027507                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027507                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056029                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056029                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051535                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051535                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029255                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029255                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029255                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029255                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8288.806880                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8288.806880                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4150.807491                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4150.807491                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                8781819                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7169373                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           406881                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             5765537                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                4953289                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            85.912015                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 772113                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             42948                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42694682                       # DTB read hits
system.cpu1.dtb.read_misses                     36199                       # DTB read misses
system.cpu1.dtb.write_hits                    6825983                       # DTB write hits
system.cpu1.dtb.write_misses                    10603                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2017                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2691                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   287                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      664                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42730881                       # DTB read accesses
system.cpu1.dtb.write_accesses                6836586                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49520665                       # DTB hits
system.cpu1.dtb.misses                          46802                       # DTB misses
system.cpu1.dtb.accesses                     49567467                       # DTB accesses
system.cpu1.itb.inst_hits                     7578103                       # ITB inst hits
system.cpu1.itb.inst_misses                      5415                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1532                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1496                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7583518                       # ITB inst accesses
system.cpu1.itb.hits                          7578103                       # DTB hits
system.cpu1.itb.misses                           5415                       # DTB misses
system.cpu1.itb.accesses                      7583518                       # DTB accesses
system.cpu1.numCycles                       409882606                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          18878139                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      60299044                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    8781819                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           5725402                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13123323                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3309042                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     63154                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              78443797                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5020                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42366                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1440662                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7576329                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               547353                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2737                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         114261108                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.645293                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.969526                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               101145087     88.52%     88.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  796077      0.70%     89.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  936773      0.82%     90.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1687391      1.48%     91.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1395150      1.22%     92.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  571856      0.50%     93.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1930284      1.69%     94.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  409373      0.36%     95.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5389117      4.72%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           114261108                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.021425                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.147113                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                20196476                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             79405562                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 11967958                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               523276                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2167836                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1103528                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                98181                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              69822224                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               326370                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2167836                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                21386304                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               34427825                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      40782107                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11206546                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4290490                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              65904089                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                18821                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                671145                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3046869                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             355                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           69217965                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            302501585                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       280690851                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6493                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             49057579                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                20160386                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            444741                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        387793                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7877859                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            12590402                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            7938263                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1041211                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1447247                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  60694774                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1157845                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 87723814                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            94478                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       13427979                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     35976172                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        277080                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    114261108                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.767749                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.513486                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           84436887     73.90%     73.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8271726      7.24%     81.14% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4125209      3.61%     84.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3692140      3.23%     87.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10373138      9.08%     97.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1967895      1.72%     98.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1041724      0.91%     99.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             276233      0.24%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              76156      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      114261108                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  32226      0.41%      0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   994      0.01%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7551636     95.89%     96.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               290793      3.69%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           314062      0.36%      0.36% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             36606472     41.73%     42.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59249      0.07%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1508      0.00%     42.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     42.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.16% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43568189     49.67%     91.82% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7174305      8.18%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              87723814                       # Type of FU issued
system.cpu1.iq.rate                          0.214022                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7875649                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.089778                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         297709996                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         75289267                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     53144243                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15477                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8000                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6803                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              95277128                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   8273                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          341654                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2834942                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3919                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17226                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1098203                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31919752                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       674526                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2167836                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               26657812                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               361941                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           61957280                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           112544                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             12590402                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             7938263                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            869014                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 64925                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 4205                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17226                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        200285                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       154811                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              355096                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             85998990                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43064757                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1724824                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104661                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50176981                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 6911907                       # Number of branches executed
system.cpu1.iew.exec_stores                   7112224                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.209814                       # Inst execution rate
system.cpu1.iew.wb_sent                      85240093                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     53151046                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 29713379                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 52980753                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.129674                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.560833                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       13311701                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         880765                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           310263                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    112093272                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.429609                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.397405                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     95372912     85.08%     85.08% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8221460      7.33%     92.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2092695      1.87%     94.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1254196      1.12%     95.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1248841      1.11%     96.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       572620      0.51%     97.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       992421      0.89%     97.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       531111      0.47%     98.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1807016      1.61%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    112093272                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38065083                       # Number of instructions committed
system.cpu1.commit.committedOps              48156333                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16595520                       # Number of memory references committed
system.cpu1.commit.loads                      9755460                       # Number of loads committed
system.cpu1.commit.membars                     190120                       # Number of memory barriers committed
system.cpu1.commit.branches                   5967695                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 42691207                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              534629                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1807016                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   170710273                       # The number of ROB reads
system.cpu1.rob.rob_writes                  125186848                       # The number of ROB writes
system.cpu1.timesIdled                        1415125                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      295621498                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  1799013115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   37995444                       # Number of Instructions Simulated
system.cpu1.committedOps                     48086694                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             37995444                       # Number of Instructions Simulated
system.cpu1.cpi                             10.787678                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.787678                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.092698                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.092698                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               384930549                       # number of integer regfile reads
system.cpu1.int_regfile_writes               55277579                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5074                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2336                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               18448778                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                405411                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           596659                       # number of replacements
system.cpu1.icache.tags.tagsinuse          480.521199                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6934084                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           597171                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            11.611555                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      74930526000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.521199                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938518                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.938518                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      6934084                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6934084                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6934084                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6934084                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6934084                       # number of overall hits
system.cpu1.icache.overall_hits::total        6934084                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       642197                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       642197                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       642197                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        642197                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       642197                       # number of overall misses
system.cpu1.icache.overall_misses::total       642197                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8716898620                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8716898620                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8716898620                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8716898620                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8716898620                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8716898620                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7576281                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7576281                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7576281                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7576281                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7576281                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7576281                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.084764                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.084764                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.084764                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.084764                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.084764                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.084764                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13573.558612                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13573.558612                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3156                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              190                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    16.610526                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        44987                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        44987                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        44987                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        44987                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        44987                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        44987                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       597210                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       597210                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       597210                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       597210                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       597210                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       597210                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7115046481                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7115046481                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7115046481                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7115046481                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7115046481                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7115046481                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3356250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3356250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3356250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      3356250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.078826                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.078826                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.078826                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.078826                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.078826                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.078826                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           360813                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          473.792536                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           12672687                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           361164                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            35.088456                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      70971728000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.792536                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.925376                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.925376                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8306232                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8306232                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4138701                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4138701                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        97355                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        97355                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        94895                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        94895                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12444933                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12444933                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12444933                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12444933                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       398716                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       398716                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1557859                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1557859                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13937                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13937                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10575                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10575                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1956575                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1956575                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1956575                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1956575                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6078170016                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6078170016                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  80199088679                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  80199088679                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    128606244                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    128606244                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52837907                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     52837907                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  86277258695                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  86277258695                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  86277258695                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  86277258695                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8704948                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8704948                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5696560                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5696560                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       111292                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       111292                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       105470                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       105470                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14401508                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14401508                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14401508                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14401508                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045803                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045803                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.273474                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.273474                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125229                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125229                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100265                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100265                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135859                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135859                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135859                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135859                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9227.684868                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9227.684868                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  4996.492388                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  4996.492388                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        31164                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        18449                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3306                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            166                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.426497                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   111.138554                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       324902                       # number of writebacks
system.cpu1.dcache.writebacks::total           324902                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       170345                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       170345                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1396167                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1396167                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1435                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1435                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1566512                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1566512                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1566512                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1566512                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       228371                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       228371                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       161692                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       161692                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12502                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12502                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10574                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10574                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       390063                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       390063                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       390063                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       390063                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2847018297                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2847018297                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   7247965426                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   7247965426                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87929505                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87929505                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31688093                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31688093                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  10094983723                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  10094983723                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  10094983723                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  10094983723                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25838951416                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25838951416                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026235                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026235                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028384                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028384                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112335                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112335                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100256                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100256                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027085                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027085                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027085                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027085                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7033.235082                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7033.235082                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  2996.793361                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  2996.793361                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 612781961046                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   41730                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   48851                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------