path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.605246                       # Number of seconds simulated
sim_ticks                                2605245500000                       # Number of ticks simulated
final_tick                               2605245500000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  66179                       # Simulator instruction rate (inst/s)
host_op_rate                                    85203                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2745863070                       # Simulator tick rate (ticks/s)
host_mem_usage                                 426204                       # Number of bytes of host memory used
host_seconds                                   948.79                       # Real time elapsed on the host
sim_insts                                    62790043                       # Number of instructions simulated
sim_ops                                      80839298                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           393536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4351548                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           427968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5241528                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131526900                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       393536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       427968                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          821504                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4250944                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7280080                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6149                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68067                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6687                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             81927                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15301674                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66421                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823705                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46487184                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              151055                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1670302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           319                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              164272                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2011913                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50485415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         151055                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         164272                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315327                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1631687                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6525                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1156181                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2794393                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1631687                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46487184                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             151055                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1676828                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             164272                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3168095                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53279808                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15301674                       # Number of read requests accepted
system.physmem.writeReqs                       823705                       # Number of write requests accepted
system.physmem.readBursts                    15301674                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     823705                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                974584832                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   4722304                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7299840                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131526900                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7280080                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    73786                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709619                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14174                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              956301                       # Per bank write bursts
system.physmem.perBankRdBursts::1              950868                       # Per bank write bursts
system.physmem.perBankRdBursts::2              950386                       # Per bank write bursts
system.physmem.perBankRdBursts::3              950557                       # Per bank write bursts
system.physmem.perBankRdBursts::4              956616                       # Per bank write bursts
system.physmem.perBankRdBursts::5              950990                       # Per bank write bursts
system.physmem.perBankRdBursts::6              949776                       # Per bank write bursts
system.physmem.perBankRdBursts::7              949548                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956645                       # Per bank write bursts
system.physmem.perBankRdBursts::9              951285                       # Per bank write bursts
system.physmem.perBankRdBursts::10             949982                       # Per bank write bursts
system.physmem.perBankRdBursts::11             948991                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956228                       # Per bank write bursts
system.physmem.perBankRdBursts::13             950424                       # Per bank write bursts
system.physmem.perBankRdBursts::14             949846                       # Per bank write bursts
system.physmem.perBankRdBursts::15             949445                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7049                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6917                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7321                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7203                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7749                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7008                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6995                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7363                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7456                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6910                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6580                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7092                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7012                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7131                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6974                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2605244301000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  162749                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66421                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1076672                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1007796                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    966781                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1073648                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    970528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1031139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2669789                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2577083                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3357471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    128637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   110466                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   102015                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    98116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    19856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    18946                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18627                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      197                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6859                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1012037                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      970.206299                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     901.657757                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     207.022901                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24841      2.45%      2.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        20798      2.06%      4.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8822      0.87%      5.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2548      0.25%      5.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2540      0.25%      5.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1879      0.19%      6.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8798      0.87%      6.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1115      0.11%      7.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       940696     92.95%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1012037                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6684                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2278.257181                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    111148.889106                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287         6680     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6684                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6684                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.064632                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.010880                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.396865                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3849     57.59%     57.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 42      0.63%     58.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1749     26.17%     84.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                863     12.91%     97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 73      1.09%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 28      0.42%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 31      0.46%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 31      0.46%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 14      0.21%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6684                       # Writes before turning the bus around for reads
system.physmem.totQLat                   394529621500                       # Total ticks spent queuing
system.physmem.totMemAccLat              680052521500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76139440000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25908.36                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44658.36                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         374.09                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.94                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.92                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14233868                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96043                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  84.18                       # Row buffer hit rate for writes
system.physmem.avgGap                       161561.74                       # Average gap between requests
system.physmem.pageHitRate                      93.40                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2261037204000                       # Time in different power states
system.physmem.memoryStateTime::REF       86994700000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      257208674750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          147                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              172                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          147                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          172                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54210578                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16352619                       # Transaction distribution
system.membus.trans_dist::ReadResp           16352619                       # Transaction distribution
system.membus.trans_dist::WriteReq             769183                       # Transaction distribution
system.membus.trans_dist::WriteResp            769183                       # Transaction distribution
system.membus.trans_dist::Writeback             66421                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35773                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          18321                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14174                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137666                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137285                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384364                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13834                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1975354                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4375612                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34653244                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27668                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17696452                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20121337                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141231865                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141231865                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487709500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11701000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy             1799000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17608394498                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4825319244                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37398632151                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    72458                       # number of replacements
system.l2c.tags.tagsinuse                53011.924457                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1875821                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   137631                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.629349                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37713.505334                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.216539                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000245                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4181.052971                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2965.825646                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.076579                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4028.442908                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4106.804235                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.575462                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000080                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063798                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.045255                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000169                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.061469                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.062665                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.808898                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3104                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8671                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53043                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18870937                       # Number of tag accesses
system.l2c.tags.data_accesses                18870937                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        23602                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4624                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             393472                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166101                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        33133                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5623                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             609766                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             201485                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1437806                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          583097                       # number of Writeback hits
system.l2c.Writeback_hits::total               583097                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1009                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             849                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1858                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           210                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           170                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               380                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48094                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            59208                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107302                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         23602                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4624                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              393472                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              214195                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         33133                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5623                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              609766                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              260693                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1545108                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        23602                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4624                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             393472                       # number of overall hits
system.l2c.overall_hits::cpu0.data             214195                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        33133                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5623                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             609766                       # number of overall hits
system.l2c.overall_hits::cpu1.data             260693                       # number of overall hits
system.l2c.overall_hits::total                1545108                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6027                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6315                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           13                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6652                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6349                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25371                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5736                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4455                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             10191                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          772                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          591                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1363                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63106                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76799                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139905                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6027                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69421                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6652                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83148                       # number of demand (read+write) misses
system.l2c.demand_misses::total                165276                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6027                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69421                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6652                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83148                       # number of overall misses
system.l2c.overall_misses::total               165276                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1286000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       293000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    437446500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    469525749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1020750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    484881000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    483780000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1878232999                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9370079                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12322478                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21692557                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       533977                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3118865                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3652842                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4338208852                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5958244026                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10296452878                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1286000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       293000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    437446500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4807734601                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1020750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    484881000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6442024026                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12174685877                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1286000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       293000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    437446500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4807734601                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1020750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    484881000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6442024026                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12174685877                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        23616                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4625                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         399499                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         172416                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        33146                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5623                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         616418                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         207834                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1463177                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       583097                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           583097                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6745                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5304                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           12049                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          982                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          761                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1743                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111200                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       136007                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247207                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        23616                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4625                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          399499                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          283616                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        33146                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5623                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          616418                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          343841                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1710384                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        23616                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4625                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         399499                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         283616                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        33146                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5623                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         616418                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         343841                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1710384                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000593                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000216                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015086                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036627                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000392                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010791                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030548                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017340                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.850408                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.839932                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.845796                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.786151                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.776610                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.781985                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.567500                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.564669                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.565943                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000593                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000216                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015086                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244771                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000392                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010791                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.241821                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.096631                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000593                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000216                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015086                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244771                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000392                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010791                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.241821                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.096631                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91857.142857                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       293000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.134893                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74350.870784                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72892.513530                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76197.826429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74030.704308                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1633.556311                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2765.988328                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2128.599450                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   691.680052                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5277.267343                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2680.001467                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68744.792128                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77582.312608                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73596.032150                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91857.142857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       293000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72581.134893                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69254.758661                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72892.513530                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77476.596262                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 73662.757309                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91857.142857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       293000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72581.134893                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69254.758661                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72892.513530                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77476.596262                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 73662.757309                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66421                       # number of writebacks
system.l2c.writebacks::total                    66421                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            26                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                77                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 77                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            26                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                77                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6022                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6277                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6644                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6323                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25294                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5736                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4455                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        10191                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          772                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          591                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1363                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63106                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76799                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139905                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6022                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69383                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6644                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83122                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165199                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6022                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69383                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6644                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83122                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165199                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1113000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       281000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    361272500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    388267999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    400921250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    403426250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1556142749                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57546650                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44906373                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    102453023                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7730770                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5917089                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     13647859                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3559268136                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5010952970                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8570221106                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1113000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       281000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    361272500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   3947536135                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    400921250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5414379220                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10126363855                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1113000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       281000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    361272500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   3947536135                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    400921250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5414379220                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10126363855                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      7054750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12335372985                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3127500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881187230                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167226742465                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1073385998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16534155943                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17607541941                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      7054750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13408758983                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3127500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171415343173                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184834284406                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000593                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000216                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015074                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036406                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000392                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010778                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030423                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017287                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.850408                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.839932                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.845796                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.786151                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.776610                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.781985                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.567500                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564669                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.565943                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000593                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000216                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015074                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244637                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000392                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010778                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.241745                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.096586                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000593                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000216                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015074                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244637                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000392                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010778                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.241745                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.096586                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        79500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       281000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59992.112255                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61855.663374                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60343.354907                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63802.981180                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61522.208785                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10032.540098                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.993939                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10053.284565                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.950777                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.994924                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.102715                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56401.421988                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65247.633042                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61257.432586                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        79500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       281000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59992.112255                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56894.860917                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60343.354907                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65137.739949                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61297.973081                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        79500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       281000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60343.354907                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61297.973081                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58770672                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2743232                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2743231                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            769183                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           769183                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           583097                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           35011                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         18701                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          53712                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           259154                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          259154                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       799809                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1073837                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        14034                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        57985                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1233533                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820063                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15283                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        75701                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8090245                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25576064                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34728353                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18500                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        94464                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39453888                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48201112                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        22492                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132584                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148227457                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148227457                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4884572                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4922251450                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1802620121                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1515652575                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9436941                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          34537141                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        2778792830                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        3257203486                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           9681453                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy          42845398                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      47405592                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322915                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322915                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8836                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          736                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2384364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32661996                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17672                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2392677                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123503205                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123503205                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4424000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               440000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2376281000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         38152801849                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6193187                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          4738042                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           296192                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             3876930                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                2986045                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.020864                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 687525                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28310                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8977307                       # DTB read hits
system.cpu0.dtb.read_misses                     29619                       # DTB read misses
system.cpu0.dtb.write_hits                    5215302                       # DTB write hits
system.cpu0.dtb.write_misses                     5680                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1732                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      993                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   285                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      620                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 9006926                       # DTB read accesses
system.cpu0.dtb.write_accesses                5220982                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14192609                       # DTB hits
system.cpu0.dtb.misses                          35299                       # DTB misses
system.cpu0.dtb.accesses                     14227908                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     4299863                       # ITB inst hits
system.cpu0.itb.inst_misses                      5195                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1219                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1331                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4305058                       # ITB inst accesses
system.cpu0.itb.hits                          4299863                       # DTB hits
system.cpu0.itb.misses                           5195                       # DTB misses
system.cpu0.itb.accesses                      4305058                       # DTB accesses
system.cpu0.numCycles                        69478980                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          11944453                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32774113                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6193187                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3673570                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7678957                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1502530                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     63317                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              19508655                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                6049                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        47760                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1413705                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          248                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4298413                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               159366                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2185                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          41753011                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.013655                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.394447                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                34081524     81.63%     81.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  576095      1.38%     83.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  828597      1.98%     84.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  688423      1.65%     86.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  783359      1.88%     88.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  570610      1.37%     89.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  698382      1.67%     91.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  360373      0.86%     92.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3165648      7.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            41753011                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.089138                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.471713                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12274082                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             20961054                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  7066192                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               425731                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1025952                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              955706                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                65065                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40945366                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213036                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1025952                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12760478                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                3004976                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      13648632                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  7041602                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4271371                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              39802599                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1199                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1526731                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1438820                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               1837389                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents             522                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           40279465                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            182145305                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       165318292                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             4116                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31479900                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8799564                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            460456                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        417031                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  4293085                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7837564                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5796369                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1159621                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1213862                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  37649045                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             906994                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37770468                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            93887                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6620221                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     14342287                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        258409                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     41753011                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.904617                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.539726                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           26686839     63.92%     63.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            5690671     13.63%     77.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3035101      7.27%     84.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2408430      5.77%     90.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2094356      5.02%     95.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             953036      2.28%     97.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             611124      1.46%     99.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             212675      0.51%     99.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              60779      0.15%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       41753011                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  29050      2.58%      2.58% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   460      0.04%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                862862     76.64%     79.26% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               233562     20.74%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            14549      0.04%      0.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22728130     60.17%     60.21% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48220      0.13%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9442602     25.00%     85.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5536256     14.66%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37770468                       # Type of FU issued
system.cpu0.iq.rate                          0.543624                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1125934                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.029810                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         118540397                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         45184408                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     34905571                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8382                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4748                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3872                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38877516                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4337                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          330330                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1458060                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2363                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13414                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       565962                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2141820                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5981                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1025952                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                2385802                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               275075                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           38676599                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            76106                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7837564                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5796369                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            579111                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 58653                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               199282                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13414                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        149919                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       118426                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              268345                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             37387044                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9294285                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           383424                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       120560                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14782259                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4971290                       # Number of branches executed
system.cpu0.iew.exec_stores                   5487974                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.538106                       # Inst execution rate
system.cpu0.iew.wb_sent                      37190474                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     34909443                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18996365                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 36943291                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.502446                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.514203                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6443412                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         648585                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           232277                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     40727059                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.780301                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.748318                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     28935599     71.05%     71.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5796697     14.23%     85.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1842943      4.53%     89.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1067095      2.62%     92.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       737891      1.81%     94.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       511993      1.26%     95.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       448684      1.10%     96.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       197374      0.48%     97.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1188783      2.92%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     40727059                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            24067678                       # Number of instructions committed
system.cpu0.commit.committedOps              31779383                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11609911                       # Number of memory references committed
system.cpu0.commit.loads                      6379504                       # Number of loads committed
system.cpu0.commit.membars                     231786                       # Number of memory barriers committed
system.cpu0.commit.branches                   4350837                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 28125415                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              498912                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        20129006     63.34%     63.34% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          39786      0.13%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc          680      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.47% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        6379504     20.07%     83.54% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5230407     16.46%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         31779383                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1188783                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    76892389                       # The number of ROB reads
system.cpu0.rob.rob_writes                   77473478                       # The number of ROB writes
system.cpu0.timesIdled                         368167                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27725969                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5140969387                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   23986936                       # Number of Instructions Simulated
system.cpu0.committedOps                     31698641                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.896534                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.896534                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.345240                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.345240                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               174527841                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34672219                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3319                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     920                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               78617689                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                500675                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           399525                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.581560                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            3866760                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           400037                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.666006                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6951542250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.581560                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999183                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999183                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          4698333                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         4698333                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      3866760                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3866760                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3866760                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3866760                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3866760                       # number of overall hits
system.cpu0.icache.overall_hits::total        3866760                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       431519                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       431519                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       431519                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        431519                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       431519                       # number of overall misses
system.cpu0.icache.overall_misses::total       431519                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5963742706                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5963742706                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5963742706                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5963742706                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5963742706                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5963742706                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4298279                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4298279                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4298279                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4298279                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4298279                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4298279                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100393                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100393                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100393                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100393                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100393                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100393                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13820.347901                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13820.347901                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4778                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.493827                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31464                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        31464                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        31464                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        31464                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        31464                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        31464                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       400055                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       400055                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       400055                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       400055                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       400055                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       400055                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4860147872                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4860147872                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4860147872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4860147872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4860147872                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4860147872                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9713500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9713500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9713500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      9713500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093073                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093073                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093073                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093073                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12148.699234                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           275167                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.361699                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9408418                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           275679                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            34.128164                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         42907250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.361699                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938206                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.938206                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         45804428                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        45804428                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5867272                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5867272                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3220606                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3220606                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139465                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       139465                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137168                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       137168                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9087878                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9087878                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9087878                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9087878                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       403110                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       403110                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1588797                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1588797                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8920                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8920                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7758                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7758                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1991907                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1991907                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1991907                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1991907                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5653636758                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5653636758                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74855868606                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  74855868606                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91362982                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     91362982                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50049767                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     50049767                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  80509505364                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  80509505364                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  80509505364                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  80509505364                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6270382                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6270382                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4809403                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4809403                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148385                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       148385                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144926                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       144926                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11079785                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11079785                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11079785                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11079785                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.064288                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.064288                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330352                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.330352                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060114                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060114                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053531                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053531                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.179778                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.179778                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.179778                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.179778                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6451.374968                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6451.374968                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         9294                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         6492                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              635                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            113                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.636220                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    57.451327                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       255545                       # number of writebacks
system.cpu0.dcache.writebacks::total           255545                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       213826                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       213826                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1457949                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1457949                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          469                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          469                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1671775                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1671775                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1671775                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1671775                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189284                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       189284                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       130848                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       130848                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8451                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8451                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7758                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7758                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       320132                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       320132                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       320132                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       320132                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2416725188                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2416725188                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5154000431                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5154000431                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69605516                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69605516                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34529233                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34529233                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7570725619                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7570725619                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7570725619                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7570725619                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13434660545                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13434660545                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1206058380                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1206058380                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14640718925                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14640718925                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030187                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030187                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027207                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027207                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056953                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056953                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053531                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053531                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028893                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028893                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028893                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028893                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8236.364454                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8236.364454                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4450.790539                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4450.790539                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                9402679                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          7728805                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           418099                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             6037829                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                5108046                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            84.600707                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 802186                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             44176                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    42878527                       # DTB read hits
system.cpu1.dtb.read_misses                     38253                       # DTB read misses
system.cpu1.dtb.write_hits                    6985734                       # DTB write hits
system.cpu1.dtb.write_misses                    10793                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1922                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2963                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   279                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      687                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                42916780                       # DTB read accesses
system.cpu1.dtb.write_accesses                6996527                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         49864261                       # DTB hits
system.cpu1.dtb.misses                          49046                       # DTB misses
system.cpu1.dtb.accesses                     49913307                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7755980                       # ITB inst hits
system.cpu1.itb.inst_misses                      5491                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1362                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1507                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7761471                       # ITB inst accesses
system.cpu1.itb.hits                          7755980                       # DTB hits
system.cpu1.itb.misses                           5491                       # DTB misses
system.cpu1.itb.accesses                      7761471                       # DTB accesses
system.cpu1.numCycles                       413132210                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          19420388                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      61788688                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9402679                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           5910232                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13466568                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3411318                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     67616                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              77041165                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5941                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        42813                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1523639                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          257                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7754163                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               555305                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2851                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         113918823                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.663934                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.994464                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               100459727     88.19%     88.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  820479      0.72%     88.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  969052      0.85%     89.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1718827      1.51%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1427854      1.25%     92.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  590556      0.52%     93.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1988498      1.75%     94.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  426289      0.37%     95.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5517541      4.84%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           113918823                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022759                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.149562                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                20573629                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             78271180                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12141436                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               681674                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2250904                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1146333                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               101070                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              71648546                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               337709                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2250904                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                21753755                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               11785871                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      44839476                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11758144                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             21530673                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              67615561                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  613                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents              15671923                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents              18336953                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1545811                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            1295                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           71310682                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            315205355                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       288681323                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6622                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             50413608                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                20897074                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            766814                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        706637                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  7207016                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            12951593                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8155935                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1106689                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1533453                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  62295252                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1184366                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 88905891                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           106644                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       13983630                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     37714490                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        285025                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    113918823                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.780432                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.530885                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           83813472     73.57%     73.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8528665      7.49%     81.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3988574      3.50%     84.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3433815      3.01%     87.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10704573      9.40%     96.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1891022      1.66%     98.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1169449      1.03%     99.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             305487      0.27%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              83766      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      113918823                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  34951      0.44%      0.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   989      0.01%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7593663     95.44%     95.90% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               326577      4.10%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            14267      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37698483     42.40%     42.42% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               61348      0.07%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1706      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.49% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43772925     49.24%     91.72% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7357130      8.28%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              88905891                       # Type of FU issued
system.cpu1.iq.rate                          0.215200                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7956180                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.089490                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         299826864                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         77472999                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     54370047                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              15424                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8128                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6867                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96839621                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   8183                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          371805                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2971595                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3826                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        18443                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1153168                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31846626                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       675699                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2250904                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                9489416                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1235015                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           63585663                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           104803                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             12951593                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8155935                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            886916                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                232294                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               885959                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         18443                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        206591                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       158855                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              365446                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             87166570                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43262018                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1739321                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       106045                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50553896                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7398817                       # Number of branches executed
system.cpu1.iew.exec_stores                   7291878                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.210990                       # Inst execution rate
system.cpu1.iew.wb_sent                      86399299                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     54376914                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30829889                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 55266228                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.131621                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.557843                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       13879712                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         899341                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           318567                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    111667919                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.440684                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.404622                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     93786179     83.99%     83.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      9487781      8.50%     92.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2098555      1.88%     94.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1338170      1.20%     95.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       960614      0.86%     96.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       571645      0.51%     96.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1030883      0.92%     97.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       527820      0.47%     98.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1866272      1.67%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    111667919                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38872746                       # Number of instructions committed
system.cpu1.commit.committedOps              49210296                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16982765                       # Number of memory references committed
system.cpu1.commit.loads                      9979998                       # Number of loads committed
system.cpu1.commit.membars                     195533                       # Number of memory barriers committed
system.cpu1.commit.branches                   6424967                       # Number of branches committed
system.cpu1.commit.fp_insts                      6822                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 43922606                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              553368                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        32167564     65.37%     65.37% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          58261      0.12%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         1706      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        9979998     20.28%     85.77% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       7002767     14.23%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         49210296                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1866272                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   171825162                       # The number of ROB reads
system.cpu1.rob.rob_writes                  128514038                       # The number of ROB writes
system.cpu1.timesIdled                        1427088                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      299213387                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4796716848                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38803107                       # Number of Instructions Simulated
system.cpu1.committedOps                     49140657                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                             10.646885                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.646885                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.093924                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.093924                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               391718305                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56505033                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     5108                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2336                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              199117817                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                722972                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           616464                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.721065                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            7090163                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           616976                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            11.491797                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      74744507500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.721065                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974065                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974065                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          8371129                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         8371129                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      7090163                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7090163                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7090163                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7090163                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7090163                       # number of overall hits
system.cpu1.icache.overall_hits::total        7090163                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       663949                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       663949                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       663949                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        663949                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       663949                       # number of overall misses
system.cpu1.icache.overall_misses::total       663949                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9003300184                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9003300184                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9003300184                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9003300184                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9003300184                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9003300184                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7754112                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7754112                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7754112                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7754112                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7754112                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7754112                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085625                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.085625                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085625                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.085625                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085625                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.085625                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13560.228548                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13560.228548                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3101                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          648                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.290323                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          648                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46932                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        46932                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        46932                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        46932                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        46932                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        46932                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       617017                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       617017                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       617017                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       617017                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       617017                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       617017                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7343865656                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7343865656                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7343865656                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7343865656                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7343865656                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7343865656                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      4135000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      4135000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      4135000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      4135000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079573                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.079573                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079573                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.079573                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           363234                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          485.053035                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           13011922                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           363603                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            35.786069                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      70837218250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.053035                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.947369                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.947369                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          369                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          369                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.720703                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         60324528                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        60324528                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      8516413                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8516413                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4259216                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4259216                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99616                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        99616                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97058                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        97058                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12775629                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12775629                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12775629                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12775629                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       409488                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       409488                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1576995                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1576995                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14210                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14210                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10944                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10944                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1986483                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1986483                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1986483                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1986483                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6227092173                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6227092173                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  74233295889                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  74233295889                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131030244                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    131030244                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58441088                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     58441088                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  80460388062                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  80460388062                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  80460388062                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  80460388062                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8925901                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8925901                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5836211                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5836211                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       113826                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       113826                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       108002                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       108002                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14762112                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14762112                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14762112                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14762112                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045876                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045876                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.270209                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.270209                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124840                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124840                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101331                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101331                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134566                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.134566                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134566                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.134566                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9220.988318                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9220.988318                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5340.011696                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5340.011696                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        30714                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        17665                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3287                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            190                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.344083                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    92.973684                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       327552                       # number of writebacks
system.cpu1.dcache.writebacks::total           327552                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       178171                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       178171                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1413840                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1413840                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1455                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1455                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1592011                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1592011                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1592011                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1592011                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231317                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       231317                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163155                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       163155                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12755                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12755                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10944                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10944                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       394472                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       394472                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       394472                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       394472                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2894401946                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2894401946                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6921941032                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6921941032                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89586755                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89586755                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36550912                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36550912                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9816342978                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   9816342978                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9816342978                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   9816342978                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25874415734                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25874415734                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025915                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025915                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027956                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027956                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.112057                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.112057                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101331                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101331                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026722                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026722                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026722                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026722                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7023.657781                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7023.657781                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3339.812865                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3339.812865                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1734300149849                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   42635                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   50404                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------