path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.537930                       # Number of seconds simulated
sim_ticks                                2537929870500                       # Number of ticks simulated
final_tick                               2537929870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  62423                       # Simulator instruction rate (inst/s)
host_op_rate                                    80294                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2613828720                       # Simulator tick rate (ticks/s)
host_mem_usage                                 387060                       # Number of bytes of host memory used
host_seconds                                   970.96                       # Real time elapsed on the host
sim_insts                                    60609996                       # Number of instructions simulated
sim_ops                                      77962726                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         4160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            798976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9090320                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131004112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       798976                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          798976                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3779648                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6795720                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           65                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12484                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142070                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293437                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59057                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813075                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47720203                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1639                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               314814                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3581785                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51618492                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          314814                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314814                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1489264                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1188398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2677663                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1489264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47720203                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1639                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              314814                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4770184                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54296154                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements                         64349                       # number of replacements
system.cpu.l2cache.tagsinuse                     51364.190937                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                         1931844                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                        129748                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                         14.889201                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                  2501176617000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks        36900.070707                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker       52.346118                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker        0.000306                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst           8179.867206                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data           6231.906599                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks           0.563050                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker       0.000799                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst             0.124815                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data             0.095091                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total                0.783755                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         84751                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         12176                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst              977692                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data              389039                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total                1463658                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks          609524                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total               609524                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data               48                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total                  48                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data             10                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            113135                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total               113135                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker          84751                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker          12176                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst               977692                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data               502174                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total                 1576793                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         84751                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         12176                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst              977692                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data              502174                       # number of overall hits
system.cpu.l2cache.overall_hits::total                1576793                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           65                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst             12366                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data             10706                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total                23139                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           2920                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total              2920                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          133143                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total             133143                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           65                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst              12366                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data             143849                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total                156282                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           65                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst             12366                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data            143849                       # number of overall misses
system.cpu.l2cache.overall_misses::total               156282                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3412000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       112500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    658599996                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    563085498                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     1225209994                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1357500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1357500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        52000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        52000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7070470996                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7070470996                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3412000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       112500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    658599996                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7633556494                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total      8295680990                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3412000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       112500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    658599996                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7633556494                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     8295680990                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        84816                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12178                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst          990058                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          399745                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total            1486797                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       609524                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           609524                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2968                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            2968                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           13                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            13                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        246278                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           246278                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        84816                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12178                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst           990058                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data           646023                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total             1733075                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        84816                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12178                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          990058                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          646023                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total            1733075                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000766                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000164                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst       0.012490                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data       0.026782                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total          0.015563                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.983827                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total       0.983827                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.230769                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.230769                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.540621                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total        0.540621                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000766                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000164                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst        0.012490                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data        0.222669                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total           0.090176                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000766                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000164                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst       0.012490                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data       0.222669                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total          0.090176                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        56250                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   464.897260                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   464.897260                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        56250                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        56250                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets                      0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                              0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                             0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks               59057                       # number of writebacks
system.cpu.l2cache.writebacks::total                    59057                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total                70                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total                 70                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total                70                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           65                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12358                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10644                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total           23069                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133143                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        133143                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           65                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         12358                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        143787                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total           156212                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           65                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12358                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143787                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          156212                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2621000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        88000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    507385499                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    430816500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    940910999                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    117082500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    117082500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5437705996                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5437705996                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2621000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        88000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    507385499                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5868522496                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6378616995                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2621000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        88000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    507385499                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5868522496                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6378616995                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      5274000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  32089389588                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  32089389588                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      5274000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000766                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000164                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012482                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026627                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015516                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.983827                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.983827                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.230769                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.230769                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.540621                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.540621                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000766                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000164                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012482                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.222573                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total      0.090136                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000766                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000164                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012482                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.222573                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.090136                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        44000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        44000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        44000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51757171                       # DTB read hits
system.cpu.dtb.read_misses                      78755                       # DTB read misses
system.cpu.dtb.write_hits                    11824944                       # DTB write hits
system.cpu.dtb.write_misses                     17612                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4306                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      3128                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    514                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1187                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51835926                       # DTB read accesses
system.cpu.dtb.write_accesses                11842556                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63582115                       # DTB hits
system.cpu.dtb.misses                           96367                       # DTB misses
system.cpu.dtb.accesses                      63678482                       # DTB accesses
system.cpu.itb.inst_hits                     13115769                       # ITB inst hits
system.cpu.itb.inst_misses                      12252                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2604                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      3277                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 13128021                       # ITB inst accesses
system.cpu.itb.hits                          13115769                       # DTB hits
system.cpu.itb.misses                           12252                       # DTB misses
system.cpu.itb.accesses                      13128021                       # DTB accesses
system.cpu.numCycles                        487049956                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 15265836                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           12253522                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             790029                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10231069                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  8383104                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1454061                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               83540                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           33339940                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      101517104                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    15265836                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9837165                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      22278409                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6025504                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     157129                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles              102031349                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2877                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        112878                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       209522                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          412                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13111736                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1022555                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6694                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          162271988                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.770946                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.133351                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                140010343     86.28%     86.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1387058      0.85%     87.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1759256      1.08%     88.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2673832      1.65%     89.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2324399      1.43%     91.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1142133      0.70%     92.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2914571      1.80%     93.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   802946      0.49%     94.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9257450      5.70%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            162271988                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.031343                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.208433                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35519413                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             101672639                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  20003488                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1109197                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3967251                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2027366                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                175080                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              118004769                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                577706                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3967251                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37625250                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                40424922                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       54666118                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18858904                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6729543                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              110552041                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 22802                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1145502                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4490712                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            31851                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115544038                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             506134218                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        506042308                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             91910                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78748778                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 36795259                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             893517                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         798182                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13541663                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21062832                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13840935                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1956455                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2555240                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  101213239                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2059558                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 126297159                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            200424                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        24661368                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     65776088                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         514288                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     162271988                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.778305                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.488656                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           116217920     71.62%     71.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14878353      9.17%     80.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7338383      4.52%     85.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6288492      3.88%     89.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12644772      7.79%     96.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2813043      1.73%     98.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1525517      0.94%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              444905      0.27%     99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              120603      0.07%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       162271988                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   53198      0.60%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      4      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8363826     94.73%     95.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                412000      4.67%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              59965938     47.48%     47.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                95633      0.08%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  2      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2112      0.00%     47.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.85% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53400637     42.28%     90.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12469145      9.87%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              126297159                       # Type of FU issued
system.cpu.iq.rate                           0.259310                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8829028                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.069907                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          423968404                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         127951101                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87290001                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23313                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12742                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10305                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              134750106                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12415                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           633498                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5342526                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         8187                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30812                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2040125                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107208                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1052465                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3967251                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                30033054                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                539777                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           103499292                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            223830                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21062832                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13840935                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1467584                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 130279                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 41269                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30812                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         412836                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       293063                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               705899                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             123087993                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52445768                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3209166                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        226495                       # number of nop insts executed
system.cpu.iew.exec_refs                     64783153                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11753944                       # Number of branches executed
system.cpu.iew.exec_stores                   12337385                       # Number of stores executed
system.cpu.iew.exec_rate                     0.252721                       # Inst execution rate
system.cpu.iew.wb_sent                      121723565                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87300306                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47490892                       # num instructions producing a value
system.cpu.iew.wb_consumers                  86410198                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.179243                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.549598                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        24569978                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1545270                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            617808                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    158387180                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.493178                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.461668                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    130224510     82.22%     82.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13962931      8.82%     91.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3932666      2.48%     93.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2224869      1.40%     94.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2020992      1.28%     96.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1058227      0.67%     96.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1402359      0.89%     97.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       664028      0.42%     98.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2896598      1.83%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    158387180                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60760377                       # Number of instructions committed
system.cpu.commit.committedOps               78113107                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27521116                       # Number of memory references committed
system.cpu.commit.loads                      15720306                       # Number of loads committed
system.cpu.commit.membars                      413361                       # Number of memory barriers committed
system.cpu.commit.branches                   10025135                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  69149691                       # Number of committed integer instructions.
system.cpu.commit.function_calls               996276                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2896598                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    256258159                       # The number of ROB reads
system.cpu.rob.rob_writes                   209428063                       # The number of ROB writes
system.cpu.timesIdled                         1906854                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       324777968                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4588721746                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60609996                       # Number of Instructions Simulated
system.cpu.committedOps                      77962726                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60609996                       # Number of Instructions Simulated
system.cpu.cpi                               8.035802                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         8.035802                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.124443                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.124443                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                557221649                       # number of integer regfile reads
system.cpu.int_regfile_writes                90065135                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8220                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2852                       # number of floating regfile writes
system.cpu.misc_regfile_reads               133714329                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 913466                       # number of misc regfile writes
system.cpu.icache.replacements                 990831                       # number of replacements
system.cpu.icache.tagsinuse                511.552497                       # Cycle average of tags in use
system.cpu.icache.total_refs                 12036161                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 991343                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  12.141268                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             7225774000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.552497                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999126                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999126                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     12036161                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12036161                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12036161                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12036161                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12036161                       # number of overall hits
system.cpu.icache.overall_hits::total        12036161                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1075440                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1075440                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1075440                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1075440                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1075440                       # number of overall misses
system.cpu.icache.overall_misses::total       1075440                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16637783989                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16637783989                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16637783989                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16637783989                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16637783989                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16637783989                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13111601                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13111601                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13111601                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13111601                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13111601                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13111601                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082022                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.082022                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.082022                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.082022                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.082022                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.082022                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15470.676178                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15470.676178                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2693492                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               350                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  7695.691429                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84051                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        84051                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        84051                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        84051                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        84051                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        84051                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991389                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       991389                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       991389                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       991389                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       991389                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       991389                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12620585492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12620585492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12620585492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12620585492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12620585492                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12620585492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075612                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075612                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075612                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.075612                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075612                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.075612                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 645511                       # number of replacements
system.cpu.dcache.tagsinuse                511.991460                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21729121                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 646023                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.635213                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               50910000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.991460                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13899785                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13899785                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7254429                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7254429                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       285860                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       285860                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       285827                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285827                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21154214                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21154214                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21154214                       # number of overall hits
system.cpu.dcache.overall_hits::total        21154214                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       767038                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        767038                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2998364                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2998364                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13689                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13689                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           13                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3765402                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3765402                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3765402                       # number of overall misses
system.cpu.dcache.overall_misses::total       3765402                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14912254500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14912254500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 129601345080                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    222071000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    222071000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       314500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       314500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 144513599580                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 144513599580                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 144513599580                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 144513599580                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14666823                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14666823                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10252793                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10252793                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299549                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       299549                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       285840                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285840                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24919616                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24919616                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24919616                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24919616                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052297                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.052297                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292444                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.292444                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045699                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045699                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000045                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.151102                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.151102                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.151102                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.151102                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38379.328311                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38379.328311                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     34382405                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7145000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              7505                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             285                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  4581.266489                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       609524                       # number of writebacks
system.cpu.dcache.writebacks::total            609524                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379381                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       379381                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2749244                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2749244                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1475                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1475                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3128625                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3128625                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3128625                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3128625                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387657                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       387657                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249120                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249120                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12214                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12214                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       636777                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       636777                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       636777                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       636777                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6303506404                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6303506404                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9254265450                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9254265450                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    162323500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    162323500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15557771854                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15557771854                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15557771854                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15557771854                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41932970674                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41932970674                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026431                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026431                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024298                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024298                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.040775                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.040775                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025553                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025553                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025553                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025553                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1323990187654                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    88040                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------