path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.534332                       # Number of seconds simulated
sim_ticks                                2534332336000                       # Number of ticks simulated
final_tick                               2534332336000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  60160                       # Simulator instruction rate (inst/s)
host_op_rate                                    77409                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2528112838                       # Simulator tick rate (ticks/s)
host_mem_usage                                 401532                       # Number of bytes of host memory used
host_seconds                                  1002.46                       # Real time elapsed on the host
sim_insts                                    60307773                       # Number of instructions simulated
sim_ops                                      77599321                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    119572608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            798144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9095056                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129468752                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       798144                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          798144                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3785216                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6801288                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14946576                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           44                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12471                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142144                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15101237                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59144                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813162                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47181108                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               314933                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3588738                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51085941                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          314933                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314933                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1493575                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1190085                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2683661                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1493575                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47181108                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              314933                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4778824                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53769602                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15101237                       # Total number of read requests seen
system.physmem.writeReqs                       813162                       # Total number of write requests seen
system.physmem.cpureqs                         218445                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    966479168                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52042368                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              129468752                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6801288                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      279                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4676                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                944611                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                944270                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                944423                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                944612                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                943754                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                943694                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                943515                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                943302                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                944002                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                943653                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               943221                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               942812                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               943924                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               943688                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               943784                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               943693                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 49130                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 48913                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50969                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51083                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51011                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51261                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51258                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51200                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51354                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51098                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50757                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                50407                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51356                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50977                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51264                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51124                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32457                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2534332242000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      36                       # Categorize read packet sizes
system.physmem.readPktSize::3                14946576                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154625                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  59144                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1052232                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    984006                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    974713                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3682136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2757823                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2756219                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2725955                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     17025                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15237                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     28723                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    42159                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    28643                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     9083                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     9038                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    12526                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     5326                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32470                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        42332                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    24053.235566                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1833.734815                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   32311.504914                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95           8211     19.40%     19.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159         3440      8.13%     27.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223         2237      5.28%     32.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287         1775      4.19%     37.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351         1231      2.91%     39.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415         1031      2.44%     42.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479          888      2.10%     44.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543          774      1.83%     46.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607          547      1.29%     47.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671          559      1.32%     48.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735          426      1.01%     49.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799          432      1.02%     50.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863          287      0.68%     51.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927          279      0.66%     52.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991          159      0.38%     52.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055          249      0.59%     53.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119          131      0.31%     53.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183          141      0.33%     53.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247          101      0.24%     54.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311          136      0.32%     54.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375           82      0.19%     54.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439          379      0.90%     55.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503         1813      4.28%     59.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567          447      1.06%     60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631           86      0.20%     61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695          158      0.37%     61.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759           41      0.10%     61.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823          104      0.25%     61.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887           37      0.09%     61.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951           64      0.15%     62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015           25      0.06%     62.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079           71      0.17%     62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143           17      0.04%     62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207           45      0.11%     62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271           11      0.03%     62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335           40      0.09%     62.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399           10      0.02%     62.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463           26      0.06%     62.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527           12      0.03%     62.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591           19      0.04%     62.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655            3      0.01%     62.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719           16      0.04%     62.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783            8      0.02%     62.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847           18      0.04%     62.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911           12      0.03%     62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975           13      0.03%     62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039            6      0.01%     62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103           25      0.06%     62.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167            6      0.01%     62.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231            6      0.01%     62.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295            9      0.02%     62.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359           13      0.03%     62.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423            6      0.01%     62.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487            6      0.01%     63.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551            2      0.00%     63.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615            9      0.02%     63.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679            6      0.01%     63.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743            8      0.02%     63.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807            5      0.01%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871            1      0.00%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935            4      0.01%     63.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999            6      0.01%     63.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063            4      0.01%     63.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127           43      0.10%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191            2      0.00%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255            3      0.01%     63.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319            7      0.02%     63.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383            8      0.02%     63.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447            8      0.02%     63.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511            6      0.01%     63.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575            4      0.01%     63.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4639            7      0.02%     63.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767            4      0.01%     63.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895            2      0.00%     63.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959            3      0.01%     63.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023            2      0.00%     63.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151           10      0.02%     63.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215            3      0.01%     63.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279            2      0.00%     63.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343            1      0.00%     63.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407            2      0.00%     63.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471            1      0.00%     63.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5663            1      0.00%     63.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5727            1      0.00%     63.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5791            1      0.00%     63.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5855            3      0.01%     63.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919            5      0.01%     63.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5983            1      0.00%     63.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047            1      0.00%     63.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111            1      0.00%     63.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175            7      0.02%     63.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6239            1      0.00%     63.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303            1      0.00%     63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495            2      0.00%     63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559            4      0.01%     63.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6623            3      0.01%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6687            2      0.00%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751            1      0.00%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815           20      0.05%     63.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879            3      0.01%     63.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943            3      0.01%     63.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7007            1      0.00%     63.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071            4      0.01%     63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7135            1      0.00%     63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199            4      0.01%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7327            1      0.00%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391            1      0.00%     63.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455            4      0.01%     63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7519            1      0.00%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583            3      0.01%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7647            1      0.00%     63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711            7      0.02%     63.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7775            1      0.00%     63.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839            3      0.01%     63.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903            2      0.00%     63.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967            3      0.01%     63.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031            3      0.01%     63.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095           11      0.03%     63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159            4      0.01%     63.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223          322      0.76%     64.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8479            1      0.00%     64.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8735            1      0.00%     64.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8991            1      0.00%     64.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9247            1      0.00%     64.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271           18      0.04%     64.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10527            2      0.00%     64.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11039            1      0.00%     64.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11295            2      0.00%     64.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11551            1      0.00%     64.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11807            1      0.00%     64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319            3      0.01%     64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12511            1      0.00%     64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12575            1      0.00%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12831            1      0.00%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13087            1      0.00%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343            2      0.00%     64.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14367            5      0.01%     64.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14495            1      0.00%     64.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14623            1      0.00%     64.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15391            3      0.01%     64.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15839            1      0.00%     64.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16415            2      0.00%     64.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16991            1      0.00%     64.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17247            4      0.01%     64.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17439            5      0.01%     64.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17951            2      0.00%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18399            1      0.00%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463            1      0.00%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18719            1      0.00%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18816-18847            1      0.00%     64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18975            1      0.00%     64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19136-19167            1      0.00%     64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19487            3      0.01%     64.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19584-19615            1      0.00%     64.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20511            2      0.00%     64.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-21023            1      0.00%     64.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21279            2      0.00%     64.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21343            1      0.00%     64.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21535            1      0.00%     64.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21919            1      0.00%     64.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22336-22367            1      0.00%     64.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22559            2      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23071            1      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23583            1      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24000-24031            1      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24095            1      0.00%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24351            2      0.00%     64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24607            4      0.01%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24640-24671            1      0.00%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24799            1      0.00%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24863            1      0.00%     64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25280-25311            1      0.00%     64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25631            2      0.00%     64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25887            2      0.00%     64.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26271            1      0.00%     64.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26655            3      0.01%     64.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26911            1      0.00%     64.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27679            3      0.01%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27712-27743            1      0.00%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27935            1      0.00%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28191            1      0.00%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28447            1      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28639            1      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28703            2      0.00%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28767            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28959            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29215            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29471            1      0.00%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29599            1      0.00%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29727            3      0.01%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29983            1      0.00%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30303            1      0.00%     64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30495            1      0.00%     64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30751            3      0.01%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31007            2      0.00%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31135            1      0.00%     64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31263            1      0.00%     64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31775            2      0.00%     64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31936-31967            1      0.00%     64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32031            1      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32159            1      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32543            2      0.00%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33055            2      0.00%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33311            1      0.00%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33567            6      0.01%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33631            2      0.00%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33695            1      0.00%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823           44      0.10%     64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34591            2      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35200-35231            1      0.00%     64.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35871            2      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37535            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37919            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37983            1      0.00%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38943            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40256-40287            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40735            1      0.00%     64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40991            3      0.01%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42015            1      0.00%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44575            1      0.00%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46111            1      0.00%     64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47647            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50207            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51231            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52255            1      0.00%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52992-53023            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53056-53087            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53279            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53760-53791            1      0.00%     64.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54528-54559            2      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57344-57375            1      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57856-57887            1      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58399            2      0.00%     64.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62464-62495            1      0.00%     64.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62528-62559            1      0.00%     64.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65088-65119            8      0.02%     64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65216-65247           18      0.04%     65.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65311           18      0.04%     65.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65344-65375           12      0.03%     65.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65503           12      0.03%     65.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567        14415     34.05%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130816-130847            1      0.00%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103          330      0.78%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127            3      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::159168-159199            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::160704-160735            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::160768-160799            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192512-192543            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196416-196447            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196639            8      0.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          42332                       # Bytes accessed per row activation
system.physmem.totQLat                   352162436750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              443380465500                       # Sum of mem lat for all requests
system.physmem.totBusLat                  75504790000                       # Total cycles spent in databus access
system.physmem.totBankLat                 15713238750                       # Total cycles spent in bank access
system.physmem.avgQLat                       23320.54                       # Average queueing delay per request
system.physmem.avgBankLat                     1040.55                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  29361.08                       # Average memory access latency
system.physmem.avgRdBW                         381.35                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.53                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.09                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.14                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                        10.77                       # Average write queue length over time
system.physmem.readRowHits                   15074158                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    797610                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  98.09                       # Row buffer hit rate for writes
system.physmem.avgGap                       159247.75                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54715776                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16153842                       # Transaction distribution
system.membus.trans_dist::ReadResp           16153842                       # Transaction distribution
system.membus.trans_dist::WriteReq             763336                       # Transaction distribution
system.membus.trans_dist::WriteResp            763336                       # Transaction distribution
system.membus.trans_dist::Writeback             59144                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4673                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4676                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131438                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131438                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382948                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885854                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29893152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     29893152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave      2382948                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port     31779006                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio         3770                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34165728                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390313                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7540                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095353                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119572608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    119572608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave      2390313                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port    136270040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio         7540                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           138667961                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              138667961                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1475262000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy         17374745000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.7                       # Layer utilization (%)
system.membus.reqLayer3.occupancy             3634500                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4718589198                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33742309741                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      48124265                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16129900                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16129887                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8158                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8158                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7938                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          518                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29893155                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     29893155                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio         7938                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio          518                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio         1026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side     29893155                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32276103                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1036                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2052                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390313                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119572568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119572568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio        15876                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio         1036                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio         2052                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side    119572568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            121962881                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               121962881                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3974000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               518000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               519000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         14946584000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374790000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         40962341509                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu.branchPred.lookups                14663186                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11751443                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            703165                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9748962                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7940354                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.448199                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1396465                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72132                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51389107                       # DTB read hits
system.cpu.dtb.read_misses                      64168                       # DTB read misses
system.cpu.dtb.write_hits                    11699261                       # DTB write hits
system.cpu.dtb.write_misses                     15977                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3558                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2439                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    422                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1367                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51453275                       # DTB read accesses
system.cpu.dtb.write_accesses                11715238                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63088368                       # DTB hits
system.cpu.dtb.misses                           80145                       # DTB misses
system.cpu.dtb.accesses                      63168513                       # DTB accesses
system.cpu.itb.inst_hits                     12244686                       # ITB inst hits
system.cpu.itb.inst_misses                      11272                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2481                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2937                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 12255958                       # ITB inst accesses
system.cpu.itb.hits                          12244686                       # DTB hits
system.cpu.itb.misses                           11272                       # DTB misses
system.cpu.itb.accesses                      12255958                       # DTB accesses
system.cpu.numCycles                        475312551                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30486466                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       96013812                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14663186                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9336819                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21137847                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5287329                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     121734                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               94652697                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 3821                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         86418                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      2672948                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          439                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  12241258                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                862361                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5349                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          152790281                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.777398                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.141854                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131667661     86.18%     86.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1302340      0.85%     87.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1711403      1.12%     88.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2491779      1.63%     89.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2204039      1.44%     91.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1109873      0.73%     91.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2734812      1.79%     93.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   742969      0.49%     94.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8825405      5.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            152790281                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.030850                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.202001                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32434469                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              96765795                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19163623                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                968040                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3458354                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1955309                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                172027                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              112442167                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                568180                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3458354                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 34339332                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38106819                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       52671042                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18167139                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6047595                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              106212332                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20597                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1004586                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4065982                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              631                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           110697957                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             485950395                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        485859311                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             91084                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78390094                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32307862                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             830633                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         736877                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12210661                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             20268413                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13492534                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1964739                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2435625                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97824738                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1983401                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 124295624                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            165509                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21636439                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     56320984                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         501000                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     152790281                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.813505                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.528895                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           108515921     71.02%     71.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13589329      8.89%     79.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7066338      4.62%     84.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5978859      3.91%     88.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12565558      8.22%     96.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2772936      1.81%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1725765      1.13%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              449060      0.29%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              126515      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       152790281                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   62738      0.71%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      4      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8365929     94.58%     95.29% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                416628      4.71%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58652585     47.19%     47.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93247      0.08%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  21      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  2      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              14      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2114      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           14      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.56% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52864927     42.53%     90.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12319034      9.91%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              124295624                       # Type of FU issued
system.cpu.iq.rate                           0.261503                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8845299                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071163                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          410448757                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         121460975                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86059539                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23386                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12542                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10302                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              132764827                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12430                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           625909                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4613851                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6375                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30092                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1760453                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107892                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        916935                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3458354                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                29328857                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                436741                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100030676                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            203650                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              20268413                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13492534                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1410837                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 115234                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3326                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30092                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         349264                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       268145                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               617409                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121630045                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52076046                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2665579                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        222537                       # number of nop insts executed
system.cpu.iew.exec_refs                     64287237                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11556571                       # Number of branches executed
system.cpu.iew.exec_stores                   12211191                       # Number of stores executed
system.cpu.iew.exec_rate                     0.255895                       # Inst execution rate
system.cpu.iew.wb_sent                      120479293                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      86069841                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47268516                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88195904                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.181081                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535949                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        21374007                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482401                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            533608                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    149331927                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.520650                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.508241                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    121887208     81.62%     81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13290460      8.90%     90.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3923979      2.63%     93.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2130804      1.43%     94.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1950357      1.31%     95.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       968781      0.65%     96.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1543061      1.03%     97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       783043      0.52%     98.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2854234      1.91%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    149331927                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60458154                       # Number of instructions committed
system.cpu.commit.committedOps               77749702                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27386643                       # Number of memory references committed
system.cpu.commit.loads                      15654562                       # Number of loads committed
system.cpu.commit.membars                      403601                       # Number of memory barriers committed
system.cpu.commit.branches                    9961356                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68854920                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991265                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2854234                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    243752783                       # The number of ROB reads
system.cpu.rob.rob_writes                   201807644                       # The number of ROB writes
system.cpu.timesIdled                         1781061                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       322522270                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4593269077                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60307773                       # Number of Instructions Simulated
system.cpu.committedOps                      77599321                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60307773                       # Number of Instructions Simulated
system.cpu.cpi                               7.881448                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.881448                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.126880                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.126880                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                550637144                       # number of integer regfile reads
system.cpu.int_regfile_writes                88566595                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8370                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2906                       # number of floating regfile writes
system.cpu.misc_regfile_reads                30124157                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 831896                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                58663468                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2657447                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2657446                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763336                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       607541                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2966                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2983                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       245999                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       245999                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side      1961368                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      5795761                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma        30461                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma       126683                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count                  7914273                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side     62726656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     85494329                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma        41328                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma       209684                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size             148471997                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148471997                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       200728                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3128200875                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1474731013                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2562590429                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      20135737                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      74394752                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements                 980590                       # number of replacements
system.cpu.icache.tags.tagsinuse                511.580932                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                 11180201                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs                 981102                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs                  11.395554                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle             6861342250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst     511.580932                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst      0.999182                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total         0.999182                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11180201                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11180201                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11180201                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11180201                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11180201                       # number of overall hits
system.cpu.icache.overall_hits::total        11180201                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1060929                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1060929                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1060929                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1060929                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1060929                       # number of overall misses
system.cpu.icache.overall_misses::total       1060929                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14286603183                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14286603183                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14286603183                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14286603183                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14286603183                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14286603183                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12241130                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12241130                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12241130                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12241130                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12241130                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12241130                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.086669                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.086669                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.086669                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.086669                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.086669                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.086669                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13466.125615                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13466.125615                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         8464                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               385                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    21.984416                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79785                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79785                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79785                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79785                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79785                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79785                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981144                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       981144                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       981144                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       981144                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       981144                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       981144                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11597968227                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11597968227                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11597968227                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11597968227                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11597968227                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11597968227                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9563750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9563750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9563750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      9563750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.080151                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.080151                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.080151                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.080151                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.080151                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.080151                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                 64396                       # number of replacements
system.cpu.l2cache.tags.tagsinuse             51354.796312                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 1885755                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs                129794                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs                 14.528830                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle          2499257274500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36876.248148                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.469348                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000368                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   8188.920307                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   6258.158141                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.562687                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000480                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124953                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.095492                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total        0.783612                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52377                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10330                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       967621                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       386975                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1417303                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607541                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607541                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           44                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           44                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           14                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           14                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112810                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112810                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52377                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10330                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       967621                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       499785                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1530113                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52377                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10330                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       967621                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       499785                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1530113                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           44                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12364                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10739                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23149                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2922                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2922                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133189                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133189                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           44                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12364                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143928                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156338                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           44                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12364                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143928                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156338                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4379500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       130250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    918927250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    809103750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1732540750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       487979                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       487979                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9125635499                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9125635499                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4379500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       130250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    918927250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9934739249                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10858176249                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4379500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       130250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    918927250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9934739249                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10858176249                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52421                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10332                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       979985                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397714                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1440452                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607541                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607541                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2966                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2966                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           17                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           17                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       245999                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       245999                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52421                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10332                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       979985                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643713                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1686451                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52421                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10332                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       979985                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643713                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1686451                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000194                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012617                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027002                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016071                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.985165                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.985165                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.176471                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.176471                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000194                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012617                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223590                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092702                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000194                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012617                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223590                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092702                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 99534.090909                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        65125                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74322.812197                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75342.559829                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74843.006177                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   167.001711                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   167.001711                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68516.435284                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68516.435284                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 99534.090909                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        65125                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74322.812197                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69025.757664                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69453.211945                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 99534.090909                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        65125                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74322.812197                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69025.757664                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69453.211945                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59144                       # number of writebacks
system.cpu.l2cache.writebacks::total            59144                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           69                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           69                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           69                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           81                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           44                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12352                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10670                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23068                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2922                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2922                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133189                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133189                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           44                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12352                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143859                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156257                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           44                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12352                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143859                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156257                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3822500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       105750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    761684000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    670036500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1435648750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29223421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29223421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7438270001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7438270001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3822500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       105750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    761684000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8108306501                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8873918751                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3822500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       105750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    761684000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8108306501                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8873918751                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      7076250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166924302000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166931378250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  26354291876                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  26354291876                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      7076250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000194                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012604                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026828                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016014                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.985165                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.985165                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.176471                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.176471                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000194                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012604                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223483                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092654                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000194                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012604                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223483                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092654                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        86875                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61664.831606                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62796.298032                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62235.510231                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.170773                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.170773                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55847.479904                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55847.479904                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        86875                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61664.831606                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56362.872681                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56790.535790                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        86875                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        52875                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61664.831606                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 643201                       # number of replacements
system.cpu.dcache.tags.tagsinuse                511.992056                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                 21499493                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs                 643713                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs                  33.399190                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle               48741250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data     511.992056                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total         0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13746666                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13746666                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7259188                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7259188                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242891                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242891                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247601                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247601                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21005854                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21005854                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21005854                       # number of overall hits
system.cpu.dcache.overall_hits::total        21005854                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       736262                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        736262                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2963161                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2963161                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13548                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13548                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           17                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           17                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3699423                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3699423                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3699423                       # number of overall misses
system.cpu.dcache.overall_misses::total       3699423                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  10077942358                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  10077942358                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 134690017209                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 134690017209                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184520250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    184520250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       258503                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       258503                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 144767959567                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 144767959567                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 144767959567                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 144767959567                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14482928                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14482928                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222349                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222349                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256439                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256439                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247618                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247618                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24705277                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24705277                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24705277                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24705277                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050837                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050837                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289871                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289871                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052831                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052831                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000069                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000069                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149742                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149742                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149742                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149742                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39132.578126                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39132.578126                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        32140                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        25391                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2640                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             284                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.174242                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    89.404930                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607541                       # number of writebacks
system.cpu.dcache.writebacks::total            607541                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350669                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       350669                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2714279                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2714279                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1344                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1344                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3064948                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3064948                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3064948                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3064948                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385593                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385593                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248882                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       248882                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12204                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12204                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           17                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           17                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634475                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634475                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634475                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634475                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967192840                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967192840                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10605079278                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10605079278                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    144959500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    144959500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       224497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       224497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15572272118                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15572272118                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15572272118                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15572272118                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  35728890492                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  35728890492                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026624                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026624                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024347                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024347                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047590                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047590                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000069                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000069                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025682                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025682                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                         0                       # number of replacements
system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1486035968259                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83045                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------