path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.503581                       # Number of seconds simulated
sim_ticks                                2503580880500                       # Number of ticks simulated
final_tick                               2503580880500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  56444                       # Simulator instruction rate (inst/s)
host_tick_rate                             1840259079                       # Simulator tick rate (ticks/s)
host_mem_usage                                 413160                       # Number of bytes of host memory used
host_seconds                                  1360.45                       # Real time elapsed on the host
sim_insts                                    76789886                       # Number of instructions simulated
system.nvmem.bytes_read                            64                       # Number of bytes read from this memory
system.nvmem.bytes_inst_read                       64                       # Number of instructions bytes read from this memory
system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
system.nvmem.num_reads                              1                       # Number of read requests responded to by this memory
system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
system.nvmem.bw_read                               26                       # Total read bandwidth from this memory (bytes/s)
system.nvmem.bw_inst_read                          26                       # Instruction read bandwidth from this memory (bytes/s)
system.nvmem.bw_total                              26                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read                   130729872                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1100224                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                  9585224                       # Number of bytes written to this memory
system.physmem.num_reads                     15117120                       # Number of read requests responded to by this memory
system.physmem.num_writes                      856661                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       52217155                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    439460                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       3828606                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      56045761                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        119505                       # number of replacements
system.l2c.tagsinuse                     25834.929390                       # Cycle average of tags in use
system.l2c.total_refs                         1795685                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        150314                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         11.946226                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 11478.014025                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 14356.915365                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.175141                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.219069                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1349535                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     153277                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1502812                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   630148                       # number of Writeback hits
system.l2c.Writeback_hits::total               630148                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                      47                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  47                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                    17                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                17                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                   105970                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105970                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1455505                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      153277                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1608782                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1455505                       # number of overall hits
system.l2c.overall_hits::1                     153277                       # number of overall hits
system.l2c.overall_hits::total                1608782                       # number of overall hits
system.l2c.ReadReq_misses::0                    36088                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                      150                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36238                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  3252                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3252                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                   4                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                 140397                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140397                       # number of ReadExReq misses
system.l2c.demand_misses::0                    176485                       # number of demand (read+write) misses
system.l2c.demand_misses::1                       150                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176635                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   176485                       # number of overall misses
system.l2c.overall_misses::1                      150                       # number of overall misses
system.l2c.overall_misses::total               176635                       # number of overall misses
system.l2c.ReadReq_miss_latency            1895542500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency            1059500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7383005500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             9278548000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            9278548000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                1385623                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 153427                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1539050                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               630148                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           630148                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                3299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0                21                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            21                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               246367                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246367                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 1631990                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  153427                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1785417                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                1631990                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 153427                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1785417                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.026045                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.000978                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.027022                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.985753                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.190476                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.569869                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.108141                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.000978                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.109119                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.108141                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.000978                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.109119                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52525.562514                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1       12636950                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 12689475.562514                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0   325.799508                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52586.632905                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    52574.145111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    61856986.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 61909560.811778                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   52574.145111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   61856986.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 61909560.811778                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          102643                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       94                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        94                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       94                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  36144                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3252                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses                 4                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               140397                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  176541                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 176541                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       1450468000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     131324500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency       160000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5639183500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        7089651500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       7089651500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 131770082500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency  32364127897                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 164134210397                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.026085                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.235578                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.261663                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      0.985753                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     0.190476                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.569869                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.108175                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.150651                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.258827                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.108175                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.150651                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.258827                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40158.668525                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40158.668525                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     52219999                       # DTB read hits
system.cpu.dtb.read_misses                      90279                       # DTB read misses
system.cpu.dtb.write_hits                    11976179                       # DTB write hits
system.cpu.dtb.write_misses                     25577                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4346                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      6089                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    654                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      2193                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 52310278                       # DTB read accesses
system.cpu.dtb.write_accesses                12001756                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          64196178                       # DTB hits
system.cpu.dtb.misses                          115856                       # DTB misses
system.cpu.dtb.accesses                      64312034                       # DTB accesses
system.cpu.itb.inst_hits                     14123674                       # ITB inst hits
system.cpu.itb.inst_misses                       9885                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2599                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      7902                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 14133559                       # ITB inst accesses
system.cpu.itb.hits                          14123674                       # DTB hits
system.cpu.itb.misses                            9885                       # DTB misses
system.cpu.itb.accesses                      14133559                       # DTB accesses
system.cpu.numCycles                        415943429                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 16201364                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           12549421                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1109380                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              13917593                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 10243002                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1423675                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              227604                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           32912368                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      104836271                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16201364                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11666677                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      24487466                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 7079059                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     131458                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               92859775                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2945                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        145565                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       217503                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  14115008                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1041610                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4861                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          155569254                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.838536                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.184070                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131107551     84.28%     84.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1739904      1.12%     85.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2616632      1.68%     87.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  3657999      2.35%     89.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2164577      1.39%     90.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1434404      0.92%     91.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2630326      1.69%     93.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   851935      0.55%     93.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9365926      6.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            155569254                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.038951                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.252045                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35134284                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              92713878                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  21991115                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1092987                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4636990                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2313958                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                177730                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              122065816                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                573184                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4636990                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37283411                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                36813700                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       49928995                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  20929371                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5976787                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              113968448                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  4165                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 915244                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3983499                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            42655                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           118524115                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             524000264                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        523903687                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             96577                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              77492548                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 41031566                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1204512                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1098851                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12310506                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21988549                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14164932                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1902928                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2266136                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  102902284                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1875395                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 126904684                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            253228                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        27017748                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     72978464                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         375688                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     155569254                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.815744                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.505343                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           108923700     70.02%     70.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15131938      9.73%     79.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7543329      4.85%     84.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6524442      4.19%     88.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12759852      8.20%     96.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2730334      1.76%     98.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1400610      0.90%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              422368      0.27%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              132681      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       155569254                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   45526      0.51%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      7      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8417505     94.61%     95.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                433723      4.88%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              60099266     47.36%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                96421      0.08%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   5      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               4      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2248      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53941927     42.51%     90.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12658279      9.97%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              126904684                       # Type of FU issued
system.cpu.iq.rate                           0.305101                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8896761                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.070106                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          418619840                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         131813494                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87332577                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23940                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13540                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10418                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              135682181                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12734                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           614286                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6307786                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11074                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        32675                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2385852                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34061916                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1151020                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4636990                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                28345844                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                418518                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           104992332                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            473238                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21988549                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14164932                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1227782                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  84296                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  7341                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          32675                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         852505                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       256815                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1109320                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             123469909                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52917262                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3434775                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        214653                       # number of nop insts executed
system.cpu.iew.exec_refs                     65406640                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11708135                       # Number of branches executed
system.cpu.iew.exec_stores                   12489378                       # Number of stores executed
system.cpu.iew.exec_rate                     0.296843                       # Inst execution rate
system.cpu.iew.wb_sent                      121811310                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87342995                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47060292                       # num instructions producing a value
system.cpu.iew.wb_consumers                  86666260                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.209988                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.543006                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       76940267                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        27835988                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1499707                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            978113                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    151014616                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.509489                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.459114                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    122165210     80.90%     80.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14833013      9.82%     90.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4110348      2.72%     93.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2186082      1.45%     94.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1788351      1.18%     96.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1361296      0.90%     96.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1264343      0.84%     97.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       665414      0.44%     98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2640559      1.75%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    151014616                       # Number of insts commited each cycle
system.cpu.commit.count                      76940267                       # Number of instructions committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27459843                       # Number of memory references committed
system.cpu.commit.loads                      15680763                       # Number of loads committed
system.cpu.commit.membars                      413065                       # Number of memory barriers committed
system.cpu.commit.branches                    9891047                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68493330                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995601                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2640559                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    251393815                       # The number of ROB reads
system.cpu.rob.rob_writes                   214319630                       # The number of ROB writes
system.cpu.timesIdled                         1877181                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       260374175                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4591130340                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    76789886                       # Number of Instructions Simulated
system.cpu.committedInsts_total              76789886                       # Number of Instructions Simulated
system.cpu.cpi                               5.416643                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         5.416643                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.184616                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.184616                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                559798057                       # number of integer regfile reads
system.cpu.int_regfile_writes                89741069                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8257                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2814                       # number of floating regfile writes
system.cpu.misc_regfile_reads               137366935                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912292                       # number of misc regfile writes
system.cpu.icache.replacements                 991177                       # number of replacements
system.cpu.icache.tagsinuse                511.615293                       # Cycle average of tags in use
system.cpu.icache.total_refs                 13035657                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 991689                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  13.144904                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6445921000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            511.615293                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.999249                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0            13035657                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13035657                       # number of ReadReq hits
system.cpu.icache.demand_hits::0             13035657                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13035657                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::0            13035657                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total        13035657                       # number of overall hits
system.cpu.icache.ReadReq_misses::0           1079227                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1079227                       # number of ReadReq misses
system.cpu.icache.demand_misses::0            1079227                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1079227                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::0           1079227                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total       1079227                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency    15906225491                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency     15906225491                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency    15906225491                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0        14114884                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     14114884                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0         14114884                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     14114884                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0        14114884                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     14114884                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0       0.076460                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0        0.076460                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0       0.076460                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::0 14738.535536                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14738.535536                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2390996                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               341                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  7011.718475                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                    57255                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits             87505                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits              87505                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits             87505                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses          991722                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses           991722                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses          991722                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency  11850340996                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency  11850340996                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency  11850340996                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency      6359500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency      6359500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0     0.070261                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0     0.070261                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0     0.070261                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643728                       # number of replacements
system.cpu.dcache.tagsinuse                511.991681                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 22270301                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 644240                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  34.568330                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               48663000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0            511.991681                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0            14416609                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        14416609                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0            7264899                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7264899                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0        299899                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       299899                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0         285488                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285488                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0             21681508                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21681508                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0            21681508                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        21681508                       # number of overall hits
system.cpu.dcache.ReadReq_misses::0            722544                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        722544                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0          2966373                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2966373                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0        13502                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13502                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::0           21                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::0            3688917                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3688917                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0           3688917                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total       3688917                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency    10864923000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency  110367485740                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency    219139000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency       467500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency    121232408740                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency   121232408740                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0        15139153                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     15139153                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0       10231272                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10231272                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0       313401                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       313401                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0       285509                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285509                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0         25370425                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     25370425                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0        25370425                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     25370425                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0       0.047727                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0      0.289932                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.043082                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::0     0.000074                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::0        0.145402                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0       0.145402                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 32863.956749                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 32863.956749                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     16658435                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7526500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2975                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             277                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5599.473950                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                   572893                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits            336628                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits          2716799                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits         1453                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits            3053427                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits           3053427                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses          385916                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses         249574                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses        12049                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses           21                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses           635490                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses          635490                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency   5245615500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency   8926036935                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency    161663500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency       398500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency  14171652435                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency  14171652435                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency  42287348315                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025491                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.024393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.038446                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000074                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0     0.025048                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0     0.025048                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency 1307927966543                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    87993                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------