path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.501676                       # Number of seconds simulated
sim_ticks                                2501676293500                       # Number of ticks simulated
final_tick                               2501676293500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  32202                       # Simulator instruction rate (inst/s)
host_op_rate                                    41595                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1355039119                       # Simulator tick rate (ticks/s)
host_mem_usage                                 388344                       # Number of bytes of host memory used
host_seconds                                  1846.20                       # Real time elapsed on the host
sim_insts                                    59451291                       # Number of instructions simulated
sim_ops                                      76792341                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                   129652968                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1121024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                  9585096                       # Number of bytes written to this memory
system.physmem.num_reads                     14979455                       # Number of read requests responded to by this memory
system.physmem.num_writes                      856659                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       51826437                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    448109                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       3831469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      55657906                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read                   64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read              64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
system.realview.nvmem.num_reads                     1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
system.realview.nvmem.bw_read                      26                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read                 26                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total                     26                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        119784                       # number of replacements
system.l2c.tagsinuse                     25999.615357                       # Cycle average of tags in use
system.l2c.total_refs                         1826145                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        150763                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         12.112687                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        14272.421964                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       65.344146                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.932012                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           6169.201034                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           5491.716201                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.217780                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000997                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.094135                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.083797                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.396723                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        141919                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker         12116                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst              995766                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              377927                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1527728                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          634955                       # number of Writeback hits
system.l2c.Writeback_hits::total               634955                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               46                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  46                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data              7                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            105770                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105770                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         141919                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker          12116                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst               995766                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               483697                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1633498                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        141919                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker         12116                       # number of overall hits
system.l2c.overall_hits::cpu.inst              995766                       # number of overall hits
system.l2c.overall_hits::cpu.data              483697                       # number of overall hits
system.l2c.overall_hits::total                1633498                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker          157                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker           13                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             17392                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             19166                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36728                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           3302                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3302                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          140335                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140335                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker          157                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              17392                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             159501                       # number of demand (read+write) misses
system.l2c.demand_misses::total                177063                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker          157                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu.inst             17392                       # number of overall misses
system.l2c.overall_misses::cpu.data            159501                       # number of overall misses
system.l2c.overall_misses::total               177063                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      8196500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       677000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    910933000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data   1001503500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1921310000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data      1203000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1203000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu.data        52000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        52000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   7367598500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7367598500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      8196500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       677000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    910933000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   8369102000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      9288908500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      8196500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       677000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    910933000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   8369102000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     9288908500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       142076                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker        12129                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst         1013158                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          397093                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1564456                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       634955                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           634955                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         3348                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3348                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data           10                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        246105                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246105                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       142076                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker        12129                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst          1013158                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           643198                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1810561                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       142076                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker        12129                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1013158                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          643198                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1810561                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001105                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001072                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.017166                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.048266                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.986260                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.300000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.570224                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.001105                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.001072                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.017166                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.247981                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.001105                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.001072                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.017166                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.247981                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data   364.324652                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52470.529965                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52470.529965                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102641                       # number of writebacks
system.l2c.writebacks::total                   102641                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst             10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data             81                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                91                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst              10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data              81                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 91                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst             10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data             81                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                91                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          157                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        17382                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        19085                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           36637                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         3302                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3302                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       140335                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140335                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker          157                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         17382                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        159420                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176972                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker          157                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        17382                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       159420                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176972                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      6288500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       521000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    698170500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data    765243500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1470223500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    132738500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    132738500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5623589000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5623589000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      6288500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker       521000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    698170500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   6388832500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   7093812500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      6288500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker       521000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    698170500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   6388832500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   7093812500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5427000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32346079731                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  32346079731                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5427000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 164116828231                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001105                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001072                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017156                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.048062                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986260                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.300000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.570224                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001105                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001072                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.017156                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.247855                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001105                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001072                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.017156                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.247855                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     52069399                       # DTB read hits
system.cpu.dtb.read_misses                      92258                       # DTB read misses
system.cpu.dtb.write_hits                    11926847                       # DTB write hits
system.cpu.dtb.write_misses                     25023                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4540                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      5662                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    693                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      2731                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 52161657                       # DTB read accesses
system.cpu.dtb.write_accesses                11951870                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63996246                       # DTB hits
system.cpu.dtb.misses                          117281                       # DTB misses
system.cpu.dtb.accesses                      64113527                       # DTB accesses
system.cpu.itb.inst_hits                     13699541                       # ITB inst hits
system.cpu.itb.inst_misses                      12131                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2626                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      6936                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 13711672                       # ITB inst accesses
system.cpu.itb.hits                          13699541                       # DTB hits
system.cpu.itb.misses                           12131                       # DTB misses
system.cpu.itb.accesses                      13711672                       # DTB accesses
system.cpu.numCycles                        411150559                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 15631672                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           12342234                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             929456                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10552810                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  8288947                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1323523                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              194787                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           32982972                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      102837345                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    15631672                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9612470                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      22590084                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6692504                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     158663                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               89850563                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2746                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        143204                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       218934                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          483                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13691858                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                996334                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6838                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          150553763                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.848436                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.233477                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                127980574     85.01%     85.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1480097      0.98%     85.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1855620      1.23%     87.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2694532      1.79%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1893570      1.26%     90.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1188011      0.79%     91.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2948135      1.96%     93.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   848652      0.56%     93.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9664572      6.42%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            150553763                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.038019                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.250121                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35091688                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              89690975                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  20321625                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1025705                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4423770                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2273029                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                186320                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              119828190                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                605140                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4423770                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37165531                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37166387                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       46484492                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19226681                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6086902                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              112339029                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  3754                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1012932                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4107831                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            44905                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           116884712                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             516607430                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        516512877                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             94553                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              77495227                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 39389484                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             939636                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         835400                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12435347                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21635443                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14050113                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1939177                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2494760                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  102209700                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1618930                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 126189021                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            231742                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26205661                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     71388624                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         331981                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     150553763                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.838166                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.542583                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           105343416     69.97%     69.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14065037      9.34%     79.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7354541      4.88%     84.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5909522      3.93%     88.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12758140      8.47%     96.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2807768      1.86%     98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1730475      1.15%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              446826      0.30%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              138038      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       150553763                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   60599      0.68%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      2      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8416262     94.64%     95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                416317      4.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              59665616     47.28%     47.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                95635      0.08%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  36      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                 48      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               9      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2270      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53732100     42.58%     90.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12586768      9.97%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              126189021                       # Type of FU issued
system.cpu.iq.rate                           0.306917                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8893180                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.070475                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          412149363                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         130053896                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     86886822                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               24048                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13080                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10409                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              134962848                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12823                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           636825                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5953964                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11249                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        33793                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2270680                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34115287                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1151875                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4423770                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                28606306                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                435959                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           104089793                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            334839                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21635443                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14050113                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             991881                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  95881                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11592                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          33793                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         550966                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       345374                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               896340                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             122956903                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52760819                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3232118                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        261163                       # number of nop insts executed
system.cpu.iew.exec_refs                     65197273                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11589071                       # Number of branches executed
system.cpu.iew.exec_stores                   12436454                       # Number of stores executed
system.cpu.iew.exec_rate                     0.299056                       # Inst execution rate
system.cpu.iew.wb_sent                      121403477                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      86897231                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47438485                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88321921                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.211351                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.537109                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       59601672                       # The number of committed instructions
system.cpu.commit.commitCommittedOps         76942722                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        26965943                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1286949                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            790517                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    146212348                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.526240                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.505087                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    118498573     81.05%     81.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13699176      9.37%     90.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3966547      2.71%     93.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2244227      1.53%     94.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1750329      1.20%     95.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1033206      0.71%     96.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1542131      1.05%     97.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       667633      0.46%     98.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2810526      1.92%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    146212348                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             59601672                       # Number of instructions committed
system.cpu.commit.committedOps               76942722                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27460912                       # Number of memory references committed
system.cpu.commit.loads                      15681479                       # Number of loads committed
system.cpu.commit.membars                      413077                       # Number of memory barriers committed
system.cpu.commit.branches                    9891359                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68495555                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995632                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2810526                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    245553933                       # The number of ROB reads
system.cpu.rob.rob_writes                   212368242                       # The number of ROB writes
system.cpu.timesIdled                         1894262                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       260596796                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4592114044                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    59451291                       # Number of Instructions Simulated
system.cpu.committedOps                      76792341                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              59451291                       # Number of Instructions Simulated
system.cpu.cpi                               6.915755                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         6.915755                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.144597                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.144597                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                557431988                       # number of integer regfile reads
system.cpu.int_regfile_writes                89182974                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8912                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2994                       # number of floating regfile writes
system.cpu.misc_regfile_reads               135303561                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912352                       # number of misc regfile writes
system.cpu.icache.replacements                1013837                       # number of replacements
system.cpu.icache.tagsinuse                511.616166                       # Cycle average of tags in use
system.cpu.icache.total_refs                 12585526                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1014349                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  12.407491                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6289783000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.616166                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999250                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999250                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     12585526                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12585526                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12585526                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12585526                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12585526                       # number of overall hits
system.cpu.icache.overall_hits::total        12585526                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1106194                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1106194                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1106194                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1106194                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1106194                       # number of overall misses
system.cpu.icache.overall_misses::total       1106194                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16291440480                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16291440480                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16291440480                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16291440480                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16291440480                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16291440480                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13691720                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13691720                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13691720                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13691720                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13691720                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13691720                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.080793                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.080793                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.080793                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      3199983                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               416                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  7692.266827                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        59844                       # number of writebacks
system.cpu.icache.writebacks::total             59844                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91810                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        91810                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        91810                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        91810                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        91810                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        91810                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1014384                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1014384                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1014384                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1014384                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1014384                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1014384                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12127535483                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12127535483                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12127535483                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12127535483                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12127535483                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12127535483                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7292000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7292000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7292000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7292000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.074087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.074087                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.074087                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 645435                       # number of replacements
system.cpu.dcache.tagsinuse                511.991565                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 22022963                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 645947                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  34.094071                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               49188000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.991565                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     14182326                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        14182326                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7265741                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7265741                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       285851                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       285851                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       285519                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285519                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21448067                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21448067                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21448067                       # number of overall hits
system.cpu.dcache.overall_hits::total        21448067                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       745935                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        745935                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2965804                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2965804                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13758                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13758                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           10                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3711739                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3711739                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3711739                       # number of overall misses
system.cpu.dcache.overall_misses::total       3711739                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  11230893500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  11230893500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110142219264                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    224423500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    224423500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       267500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       267500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 121373112764                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 121373112764                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 121373112764                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 121373112764                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14928261                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14928261                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10231545                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10231545                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       299609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       285529                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285529                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     25159806                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     25159806                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     25159806                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     25159806                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049968                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289869                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045920                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000035                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.147527                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.147527                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        26750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     16852944                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7563500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2993                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             267                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5630.786502                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       575111                       # number of writebacks
system.cpu.dcache.writebacks::total            575111                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       358347                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       358347                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2716460                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2716460                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1395                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1395                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3074807                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3074807                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3074807                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3074807                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387588                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       387588                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249344                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249344                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12363                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12363                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           10                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       636932                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       636932                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       636932                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       636932                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5281773000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5281773000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8909514444                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8909514444                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    166180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    166180500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       235000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       235000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14191287444                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  14191287444                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14191287444                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  14191287444                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42252638495                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42252638495                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025963                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024370                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041264                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025315                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025315                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        23500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1296055922339                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    87985                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------