path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.829112                       # Number of seconds simulated
sim_ticks                                2829111899000                       # Number of ticks simulated
final_tick                               2829111899000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 175088                       # Simulator instruction rate (inst/s)
host_op_rate                                   212371                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4377954653                       # Simulator tick rate (ticks/s)
host_mem_usage                                 587752                       # Number of bytes of host memory used
host_seconds                                   646.22                       # Real time elapsed on the host
sim_insts                                   113144906                       # Number of instructions simulated
sim_ops                                     137237936                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1316192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9473064                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10791560                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1316192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1316192                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8091072                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8108596                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              22817                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             148537                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                171390                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126423                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               130804                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            339                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               465232                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3348423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3814469                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          465232                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             465232                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2859934                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6194                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2866128                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2859934                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           339                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              465232                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3354617                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6680597                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        171391                       # Number of read requests accepted
system.physmem.writeReqs                       130804                       # Number of write requests accepted
system.physmem.readBursts                      171391                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     130804                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10959616                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8121152                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10791624                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8108596                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10684                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10046                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10837                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10895                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13724                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10674                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11441                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11403                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10108                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10400                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10362                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9483                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10233                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11051                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10017                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9886                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8065                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7694                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8363                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8151                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8125                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8034                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8547                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8477                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7686                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7978                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7776                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7088                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7779                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8428                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7464                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7238                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          67                       # Number of times write queue was full causing retry
system.physmem.totGap                    2829111664000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3002                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  167833                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 126423                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    150076                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     14975                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5318                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       858                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5955                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      180                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61280                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      311.370235                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.627944                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.836836                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22555     36.81%     36.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14711     24.01%     60.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6399     10.44%     71.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3617      5.90%     77.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2643      4.31%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1730      2.82%     84.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1046      1.71%     86.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1020      1.66%     87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7559     12.34%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61280                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6329                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.046295                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      535.582122                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6327     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6329                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6329                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.049455                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.259917                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.703816                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5592     88.36%     88.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              89      1.41%     89.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              39      0.62%     90.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              43      0.68%     91.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             270      4.27%     95.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              18      0.28%     95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              20      0.32%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              12      0.19%     96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.17%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.09%     96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.03%     96.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.09%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             144      2.28%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.11%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.02%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.06%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             8      0.13%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             4      0.06%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.02%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.24%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.06%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             5      0.08%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6329                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4759784250                       # Total ticks spent queuing
system.physmem.totMemAccLat                7970609250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    856220000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27795.17                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46545.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.87                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.87                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     141725                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95132                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.76                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.96                       # Row buffer hit rate for writes
system.physmem.avgGap                      9361874.50                       # Average gap between requests
system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  229315380                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  121884015                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 640486560                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                341680320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           5265620880.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4324767840                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              323323200                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       10830363660                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        7337789280                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       667252731645                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             696670151130                       # Total energy per rank (pJ)
system.physmem_0.averagePower              246.250476                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2818571248250                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      597049500                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2238844000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2775921295250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  19108902750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      7495096250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  23750711250                       # Time in different power states
system.physmem_1.actEnergy                  208223820                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  110673585                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 582195600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                320701140                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           5120565840.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4126082940                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              330709920                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       10081531860                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        7328179680                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       667772142345                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             695983009200                       # Total energy per rank (pJ)
system.physmem_1.averagePower              246.007593                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2819198005500                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      626918750                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2177664000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2778005345250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  19083791250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      7109310750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  22108869000                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                46861889                       # Number of BP lookups
system.cpu.branchPred.condPredicted          23994211                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1178677                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             29377087                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13527695                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             46.048456                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                11745847                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              34771                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         7932573                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            7787517                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           145056                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        60304                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                     70988                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                70988                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        28945                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23300                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore        18743                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples        52245                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean   398.564456                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev  2327.323415                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095        50380     96.43%     96.43% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191          694      1.33%     97.76% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287          600      1.15%     98.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383          333      0.64%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-20479           70      0.13%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575          116      0.22%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-28671           29      0.06%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767            3      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::45056-49151            9      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        52245                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples        16835                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean  9419.156519                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  7648.743457                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  6474.178852                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-8191         8274     49.15%     49.15% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::8192-16383         6961     41.35%     90.50% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-24575         1349      8.01%     98.51% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::24576-32767          164      0.97%     99.48% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-40959           19      0.11%     99.60% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::40960-49151           59      0.35%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::90112-98303            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-106495            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::114688-122879            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total        16835                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 118986443724                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.628139                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.489522                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1  118939907724     99.96%     99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3      32370000      0.03%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5       6888500      0.01%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7       4293000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9        974500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11       505000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13      1161500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15       334500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17         9000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 118986443724                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6321     82.34%     82.34% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1356     17.66%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7677                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        70988                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        70988                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7677                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7677                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        78665                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     25415823                       # DTB read hits
system.cpu.dtb.read_misses                      61333                       # DTB read misses
system.cpu.dtb.write_hits                    19865547                       # DTB write hits
system.cpu.dtb.write_misses                      9655                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4258                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       385                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   2212                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1098                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 25477156                       # DTB read accesses
system.cpu.dtb.write_accesses                19875202                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          45281370                       # DTB hits
system.cpu.dtb.misses                           70988                       # DTB misses
system.cpu.dtb.accesses                      45352358                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                     12746                       # Table walker walks requested
system.cpu.itb.walker.walksShort                12746                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1         3372                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         7811                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore         1563                       # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples        11183                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean   675.266029                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev  2802.587445                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095        10603     94.81%     94.81% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191          140      1.25%     96.07% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287          267      2.39%     98.45% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383          112      1.00%     99.45% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479           22      0.20%     99.65% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575           26      0.23%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671            5      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767            4      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total        11183                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         4880                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean  9080.327869                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  7055.685836                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 11146.166993                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535         4878     99.96%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         4880                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples  24496220212                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean     0.683787                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev     0.465095                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      7747033500     31.63%     31.63% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1     16748218212     68.37%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2          952500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3            3000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4            3500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::5            3000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::6            6500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total  24496220212                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2980     89.84%     89.84% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           337     10.16%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3317                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12746                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total        12746                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3317                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3317                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total        16063                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     66035618                       # ITB inst hits
system.cpu.itb.inst_misses                      12746                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     3018                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2274                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 66048364                       # ITB inst accesses
system.cpu.itb.hits                          66035618                       # DTB hits
system.cpu.itb.misses                           12746                       # DTB misses
system.cpu.itb.accesses                      66048364                       # DTB accesses
system.cpu.numPwrStateTransitions                6078                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3039                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     886809089.600197                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17417893131.253975                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2967     97.63%     97.63% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           66      2.17%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499972215488                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3039                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    134099075705                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012823295                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        268198207                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          105002772                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      184114970                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    46861889                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           33061059                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     151938402                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6072000                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     175966                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 7979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        334285                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       875612                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          143                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  66034467                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               1042471                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6106                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          261371159                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.859042                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.228291                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                162416335     62.14%     62.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 29147387     11.15%     73.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 14040939      5.37%     78.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 55766498     21.34%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            261371159                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.174729                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.686488                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 78127678                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             112458141                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  64373777                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3837716                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                2573847                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             10211840                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                470330                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              157024104                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3522922                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                2573847                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 83881832                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                11236308                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       76411931                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  62459889                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              24807352                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              146462333                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                915339                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents                473585                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  65974                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                  19134                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               22055359                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           150259400                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             677124866                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        163984739                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             11050                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             141797655                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  8461739                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2842470                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2647297                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13853647                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26344198                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21214401                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1696128                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2146370                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  143256850                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2116673                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 143077391                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            262359                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         8135583                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     14293372                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         121607                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     261371159                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.547411                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.874705                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           173167745     66.25%     66.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            45242575     17.31%     83.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            31871715     12.19%     95.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            10265143      3.93%     99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4              823948      0.32%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       261371159                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 7332033     32.77%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                5621223     25.12%     57.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               9411536     42.06%     99.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead              2405      0.01%     99.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite             8745      0.04%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              95878441     67.01%     67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               114347      0.08%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           8549      0.01%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             26131013     18.26%     85.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            20930310     14.63%     99.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead            2708      0.00%     99.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite           9686      0.01%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              143077391                       # Type of FU issued
system.cpu.iq.rate                           0.533476                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    22375974                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.156391                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          570128328                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         153514376                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    140022897                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               35946                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13304                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        11498                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              165427480                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   23548                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           325201                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1431545                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses          741                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18622                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       620213                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        88247                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          6406                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                2573847                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1145032                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                405376                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           145553638                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26344198                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21214401                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1093740                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  17692                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                369492                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18622                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         275358                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       475095                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               750453                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             142177506                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25738555                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            828985                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        180115                       # number of nop insts executed
system.cpu.iew.exec_refs                     46565887                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 26507471                       # Number of branches executed
system.cpu.iew.exec_stores                   20827332                       # Number of stores executed
system.cpu.iew.exec_rate                     0.530121                       # Inst execution rate
system.cpu.iew.wb_sent                      141808684                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     140034395                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  63259988                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95801132                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.522130                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.660326                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         7349911                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1995066                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            716524                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    258476519                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.531549                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.133767                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    185006238     71.58%     71.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     43313968     16.76%     88.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     15459084      5.98%     94.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4363700      1.69%     96.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      6431569      2.49%     98.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1619656      0.63%     99.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       798464      0.31%     99.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       416455      0.16%     99.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1067385      0.41%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    258476519                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            113299811                       # Number of instructions committed
system.cpu.commit.committedOps              137392841                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       45506841                       # Number of memory references committed
system.cpu.commit.loads                      24912653                       # Number of loads committed
system.cpu.commit.membars                      814563                       # Number of memory barriers committed
system.cpu.commit.branches                   26044441                       # Number of branches committed
system.cpu.commit.fp_insts                      11492                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 120215331                       # Number of committed integer instructions.
system.cpu.commit.function_calls              4891729                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         91764545     66.79%     66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          112906      0.08%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc         8549      0.01%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        24909945     18.13%     85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20585408     14.98%     99.99% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead         2708      0.00%     99.99% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite         8780      0.01%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         137392841                       # Class of committed instruction
system.cpu.commit.bw_lim_events               1067385                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    379915503                       # The number of ROB reads
system.cpu.rob.rob_writes                   292367166                       # The number of ROB writes
system.cpu.timesIdled                          894415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         6827048                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   5390025592                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   113144906                       # Number of Instructions Simulated
system.cpu.committedOps                     137237936                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               2.370396                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.370396                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.421870                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.421870                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                155555257                       # number of integer regfile reads
system.cpu.int_regfile_writes                88513526                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      9686                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 502284717                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 53144427                       # number of cc regfile writes
system.cpu.misc_regfile_reads               455456531                       # number of misc regfile reads
system.cpu.misc_regfile_writes                1521074                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            834899                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.950856                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40072104                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            835411                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             47.966934                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         291735500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.950856                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999904                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999904                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         179153223                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        179153223                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23270451                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23270451                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     15550335                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       15550335                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       346358                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        346358                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       441909                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       441909                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460176                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460176                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      38820786                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         38820786                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     39167144                       # number of overall hits
system.cpu.dcache.overall_hits::total        39167144                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       703305                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        703305                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3603558                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3603558                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       176816                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       176816                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        26536                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        26536                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      4306863                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4306863                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4483679                       # number of overall misses
system.cpu.dcache.overall_misses::total       4483679                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  11004555500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  11004555500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 167287466703                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 167287466703                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    367903000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    367903000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       196000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       196000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 178292022203                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 178292022203                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 178292022203                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 178292022203                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23973756                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23973756                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19153893                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19153893                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       523174                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       523174                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       468445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460180                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460180                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     43127649                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     43127649                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43650823                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43650823                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029336                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.029336                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188137                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.188137                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.337968                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.337968                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.056647                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056647                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.099863                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.099863                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.102717                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.102717                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15646.917767                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15646.917767                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46422.859491                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 46422.859491                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13864.297558                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13864.297558                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        49000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        49000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41397.189138                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41397.189138                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39764.671423                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39764.671423                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       631960                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              7043                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    89.728809                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       693774                       # number of writebacks
system.cpu.dcache.writebacks::total            693774                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291761                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       291761                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3304379                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      3304379                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18239                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        18239                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3596140                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3596140                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3596140                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3596140                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       411544                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       411544                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299179                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       299179                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119204                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       119204                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8297                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8297                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       710723                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       710723                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       829927                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       829927                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6158767500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6158767500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14913404483                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14913404483                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1645609500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1645609500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    125434500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    125434500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       192000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       192000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21072171983                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  21072171983                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22717781483                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22717781483                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6282018000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6282018000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6282018000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6282018000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017166                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017166                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017712                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017712                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016480                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016480                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019013                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019013                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14965.028041                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14965.028041                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49847.764994                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49847.764994                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13804.985571                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13804.985571                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15118.054719                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15118.054719                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        48000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        48000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29648.923678                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29648.923678                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27373.228589                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27373.228589                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201818.935329                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201818.935329                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106998.995078                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106998.995078                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           1887711                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.315276                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            64050692                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1888223                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             33.921148                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       14108989500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.315276                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998663                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998663                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          67919712                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         67919712                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     64050692                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        64050692                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      64050692                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         64050692                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     64050692                       # number of overall hits
system.cpu.icache.overall_hits::total        64050692                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1980765                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1980765                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1980765                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1980765                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1980765                       # number of overall misses
system.cpu.icache.overall_misses::total       1980765                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  27590430995                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  27590430995                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  27590430995                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  27590430995                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  27590430995                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  27590430995                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     66031457                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     66031457                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     66031457                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     66031457                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     66031457                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     66031457                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029997                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.029997                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.029997                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.029997                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.029997                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.029997                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13929.179380                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13929.179380                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13929.179380                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13929.179380                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13929.179380                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13929.179380                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2703                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               141                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    19.170213                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      1887711                       # number of writebacks
system.cpu.icache.writebacks::total           1887711                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        92509                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        92509                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        92509                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        92509                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        92509                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        92509                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1888256                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1888256                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1888256                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1888256                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1888256                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1888256                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3009                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3009                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3009                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3009                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24716064497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  24716064497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24716064497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  24716064497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24716064497                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  24716064497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    246809500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    246809500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    246809500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    246809500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028596                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028596                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028596                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.028596                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028596                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.028596                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13089.361028                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13089.361028                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13089.361028                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13089.361028                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13089.361028                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13089.361028                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            98094                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65152.111665                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            5295433                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           163482                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            32.391535                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      91189489000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     7.957155                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     4.692905                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10411.783860                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 54727.677744                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000121                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000072                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158871                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.835078                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994142                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65376                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          313                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5395                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59668                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997559                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43899166                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43899166                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52220                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10081                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          62301                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       693774                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       693774                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1849835                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1849835                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         2788                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         2788                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       161417                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       161417                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1868356                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1868356                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       525524                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       525524                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52220                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10081                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1868356                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       686941                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2617598                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52220                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10081                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1868356                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       686941                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2617598                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           15                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total           21                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       135097                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       135097                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19843                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        19843                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13393                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        13393                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           15                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        19843                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       148490                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168354                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           15                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        19843                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       148490                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168354                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4534500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker      2124500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total      6659000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       144500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       144500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       164000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       164000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12738264500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12738264500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2148357000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2148357000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1551011500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1551011500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4534500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      2124500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2148357000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  14289276000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  16444292000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4534500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker      2124500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2148357000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  14289276000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  16444292000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52235                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10087                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        62322                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       693774                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       693774                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1849835                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1849835                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2793                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2793                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            4                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296514                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296514                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1888199                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1888199                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       538917                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       538917                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52235                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10087                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1888199                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       835431                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2785952                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52235                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10087                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1888199                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       835431                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2785952                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000287                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000595                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.000337                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.001790                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.001790                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.455618                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.455618                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010509                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010509                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024852                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024852                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000287                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000595                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010509                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.177741                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.060430                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000287                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000595                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010509                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.177741                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.060430                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker       302300                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 354083.333333                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 317095.238095                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        28900                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        28900                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        82000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        82000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94289.765872                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94289.765872                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 108267.751852                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 108267.751852                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115807.623385                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115807.623385                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       302300                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 354083.333333                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 108267.751852                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96230.560981                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97676.871354                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       302300                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 354083.333333                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 108267.751852                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96230.560981                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97676.871354                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        90233                       # number of writebacks
system.cpu.l2cache.writebacks::total            90233                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          138                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           15                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total           21                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135097                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       135097                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19818                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19818                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13280                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13280                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           15                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        19818                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       148377                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168216                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           15                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        19818                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       148377                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168216                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3009                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34136                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3009                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61720                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4384500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      2064500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      6449000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        94500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        94500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       144000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       144000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11387294500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11387294500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1948311000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1948311000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1407408500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1407408500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4384500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      2064500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1948311000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12794703000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  14749463000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4384500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      2064500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1948311000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12794703000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14749463000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    209196500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5892920500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6102117000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    209196500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5892920500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6102117000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000287                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000595                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000337                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.001790                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.001790                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455618                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455618                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010496                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010496                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024642                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024642                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000287                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000595                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010496                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177605                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060380                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000287                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000595                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010496                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177605                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.060380                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       292300                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 344083.333333                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 307095.238095                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        18900                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        18900                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84289.765872                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84289.765872                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 98310.172570                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 98310.172570                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105979.555723                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105979.555723                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       292300                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 344083.333333                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 98310.172570                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86231.039851                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87681.689019                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       292300                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 344083.333333                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 98310.172570                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86231.039851                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87681.689019                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189318.614065                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178758.993438                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100371.659485                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98867.741413                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      5481318                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757626                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        46311                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          188                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          188                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         128675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2556003                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       784007                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1887711                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       148986                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2793                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            4                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2797                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296514                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296514                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1888256                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       539126                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq         4612                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp            4                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5670183                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2628937                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29081                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       127780                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8455981                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241706320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98062173                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40348                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       208940                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          340017781                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      135349                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               5917412                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2985660                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.026373                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.160242                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2906919     97.36%     97.36% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              78741      2.64%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2985660                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5397955498                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       298125                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2836300178                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1299640147                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      19000487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      75596896                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30169                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30169                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72888                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72888                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178366                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320992                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2320992                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480117                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             43091500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               325500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                90500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               648000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               47500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6160500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            33869500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187578393                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36712000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36410                       # number of replacements
system.iocache.tags.tagsinuse                1.001800                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         253685816000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.001800                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062613                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062613                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
system.iocache.tags.data_accesses              327996                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
system.iocache.overall_misses::total            36444                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     35734875                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     35734875                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4362724518                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4362724518                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4398459393                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4398459393                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4398459393                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4398459393                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36444                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36444                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36444                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36444                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 162431.250000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162431.250000                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120437.403876                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120437.403876                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120690.906404                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120690.906404                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120690.906404                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120690.906404                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          220                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          220                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36444                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     24734875                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     24734875                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2549742484                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2549742484                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2574477359                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2574477359                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2574477359                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2574477359                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112431.250000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112431.250000                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70388.209033                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70388.209033                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70642.008534                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70642.008534                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70642.008534                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70642.008534                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests        339238                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       139305                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          511                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               34136                       # Transaction distribution
system.membus.trans_dist::ReadResp              67474                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       126423                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8081                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              126                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            134976                       # Transaction distribution
system.membus.trans_dist::ReadExResp           134976                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         33339                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4572                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450012                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       557574                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72869                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72869                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 630443                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16583036                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16746413                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19063533                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             5056                       # Total snoops (count)
system.membus.snoopTraffic                      30848                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            266387                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019149                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.137048                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  261286     98.09%     98.09% # Request fanout histogram
system.membus.snoop_fanout::1                    5101      1.91%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              266387                       # Request fanout histogram
system.membus.reqLayer0.occupancy            84461000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1733999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           877020942                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          984714000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            5968652                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000                       # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3039                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------