path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.501686                       # Number of seconds simulated
sim_ticks                                2501685689500                       # Number of ticks simulated
final_tick                               2501685689500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  57858                       # Simulator instruction rate (inst/s)
host_op_rate                                    74704                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2429415836                       # Simulator tick rate (ticks/s)
host_mem_usage                                 387132                       # Number of bytes of host memory used
host_seconds                                  1029.75                       # Real time elapsed on the host
sim_insts                                    59579009                       # Number of instructions simulated
sim_ops                                      76926775                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    118440096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker        12032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1119872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10085712                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129658608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1119872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1119872                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6569664                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9585736                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14805012                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker          188                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              17498                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             157623                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14980335                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          102651                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               856669                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47344115                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           4810                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker            358                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               447647                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              4031566                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51828496                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          447647                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             447647                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2626095                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1205616                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3831711                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2626095                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47344115                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker           358                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              447647                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             5237182                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               55660207                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        119797                       # number of replacements
system.l2c.tagsinuse                     26022.811009                       # Cycle average of tags in use
system.l2c.total_refs                         1834134                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        150735                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         12.167937                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        14260.921168                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       79.122472                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        1.014068                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           6176.146101                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           5505.607200                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.217604                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.001207                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.094241                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.084009                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.397077                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        144170                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker         12492                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst             1001175                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              378296                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1536133                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          635023                       # number of Writeback hits
system.l2c.Writeback_hits::total               635023                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               45                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  45                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data              8                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            105875                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105875                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         144170                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker          12492                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst              1001175                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               484171                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1642008                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        144170                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker         12492                       # number of overall hits
system.l2c.overall_hits::cpu.inst             1001175                       # number of overall hits
system.l2c.overall_hits::cpu.data              484171                       # number of overall hits
system.l2c.overall_hits::total                1642008                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker          189                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             17378                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             19180                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36761                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           3300                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3300                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               5                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          140292                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140292                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker          189                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              17378                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             159472                       # number of demand (read+write) misses
system.l2c.demand_misses::total                177053                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker          189                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu.inst             17378                       # number of overall misses
system.l2c.overall_misses::cpu.data            159472                       # number of overall misses
system.l2c.overall_misses::total               177053                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      9850500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       752000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    910079500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data   1002096000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1922778000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data       996000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       996000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu.data       104000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       104000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   7365557000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7365557000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      9850500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       752000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    910079500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   8367653000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      9288335000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      9850500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       752000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    910079500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   8367653000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     9288335000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       144359                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker        12506                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst         1018553                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          397476                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1572894                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       635023                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           635023                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         3345                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3345                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data           13                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            13                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        246167                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246167                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       144359                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker        12506                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst          1018553                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           643643                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1819061                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       144359                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker        12506                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1018553                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          643643                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1819061                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001119                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.017061                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.048254                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.023372                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.986547                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.986547                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.384615                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.384615                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.569906                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.569906                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.001119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.017061                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.247765                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.097332                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.001309                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.001119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.017061                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.247765                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.097332                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52304.833927                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data   301.818182                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   301.818182                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data        20800                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        20800                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52460.760337                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52460.760337                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102651                       # number of writebacks
system.l2c.writebacks::total                   102651                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.inst             14                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data             86                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               101                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.inst              14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data              86                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                101                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.inst             14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data             86                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               101                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          188                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        17364                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        19094                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           36660                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         3300                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3300                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       140292                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140292                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker          188                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         17364                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        159386                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176952                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker          188                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        17364                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       159386                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176952                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       584000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    697406000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data    765603000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1471125000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    132880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    132880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       200000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       200000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5622122500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5622122500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker       584000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    697406000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   6387725500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   7093247500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      7532000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker       584000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    697406000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   6387725500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   7093247500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5427000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32346095899                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  32346095899                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5427000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 164110109399                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.048038                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.023307                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986547                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.986547                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.384615                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.384615                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.569906                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.569906                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.097277                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001302                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001119                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.017048                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.247631                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.097277                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     52103903                       # DTB read hits
system.cpu.dtb.read_misses                      93079                       # DTB read misses
system.cpu.dtb.write_hits                    11946241                       # DTB write hits
system.cpu.dtb.write_misses                     25022                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4532                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      5562                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    707                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      2799                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 52196982                       # DTB read accesses
system.cpu.dtb.write_accesses                11971263                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          64050144                       # DTB hits
system.cpu.dtb.misses                          118101                       # DTB misses
system.cpu.dtb.accesses                      64168245                       # DTB accesses
system.cpu.itb.inst_hits                     13717584                       # ITB inst hits
system.cpu.itb.inst_misses                      12272                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2655                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      6863                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 13729856                       # ITB inst accesses
system.cpu.itb.hits                          13717584                       # DTB hits
system.cpu.itb.misses                           12272                       # DTB misses
system.cpu.itb.accesses                      13729856                       # DTB accesses
system.cpu.numCycles                        411352060                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 15654738                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           12362397                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             932839                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10530768                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  8288874                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1329017                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              195537                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           33116930                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      103031700                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    15654738                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9617891                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      22620194                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6706106                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     163882                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               89861042                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2823                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        147160                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       218224                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          462                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13709942                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                998560                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    6868                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          150746244                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.848897                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.234280                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                128142810     85.01%     85.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1478319      0.98%     85.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1855018      1.23%     87.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2695901      1.79%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1893540      1.26%     90.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1191101      0.79%     91.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2951659      1.96%     93.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   850848      0.56%     93.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9687048      6.43%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            150746244                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.038057                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.250471                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 35228906                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              89710063                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  20347806                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1026685                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4432784                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              2275641                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                186729                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              120042439                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                604390                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4432784                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37305734                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37165628                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       46502465                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19251695                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6087938                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              112539597                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  3873                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1013212                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4109157                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            45575                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           117156815                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             517555842                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        517460811                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             95031                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              77687687                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 39469127                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             939790                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         835958                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12443241                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             21685850                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14072237                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1938675                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2482763                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  102391550                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1619583                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 126350622                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            234593                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26254924                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     71509700                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         332277                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     150746244                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.838168                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.542455                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           105470655     69.97%     69.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14086510      9.34%     79.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7371222      4.89%     84.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5923402      3.93%     88.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12762751      8.47%     96.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2810704      1.86%     98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1735902      1.15%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              449258      0.30%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              135840      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       150746244                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   61043      0.69%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      4      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8421186     94.66%     95.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                414230      4.66%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            106530      0.08%      0.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              59762768     47.30%     47.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                95812      0.08%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  38      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                 45      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               9      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2279      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.46% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             53776494     42.56%     90.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12606638      9.98%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              126350622                       # Type of FU issued
system.cpu.iq.rate                           0.307159                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8896463                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.070411                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          412671946                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         130285978                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     87040433                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               24078                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              13182                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10434                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              135127716                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12839                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           636069                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      5970496                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        11101                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        34253                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2273952                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34114355                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1152098                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4432784                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                28604721                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                436722                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           104273041                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            335924                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              21685850                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14072237                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             992808                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  95700                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11591                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          34253                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         552378                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       346914                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               899292                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             123108789                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52799372                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3241833                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        261908                       # number of nop insts executed
system.cpu.iew.exec_refs                     65255060                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11601340                       # Number of branches executed
system.cpu.iew.exec_stores                   12455688                       # Number of stores executed
system.cpu.iew.exec_rate                     0.299278                       # Inst execution rate
system.cpu.iew.wb_sent                      121555618                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      87050867                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47546734                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88572059                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.211621                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.536814                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       59729390                       # The number of committed instructions
system.cpu.commit.commitCommittedOps         77077156                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        27015439                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1287306                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            793496                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    146395876                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.526498                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.504904                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    118626341     81.03%     81.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13714527      9.37%     90.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3991808      2.73%     93.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2249419      1.54%     94.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1746576      1.19%     95.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1042045      0.71%     96.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1550885      1.06%     97.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       665283      0.45%     98.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2808992      1.92%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    146395876                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             59729390                       # Number of instructions committed
system.cpu.commit.committedOps               77077156                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27513639                       # Number of memory references committed
system.cpu.commit.loads                      15715354                       # Number of loads committed
system.cpu.commit.membars                      413068                       # Number of memory barriers committed
system.cpu.commit.branches                    9904424                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68617835                       # Number of committed integer instructions.
system.cpu.commit.function_calls               995976                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2808992                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    245922084                       # The number of ROB reads
system.cpu.rob.rob_writes                   212744706                       # The number of ROB writes
system.cpu.timesIdled                         1895448                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       260605816                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4591931267                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    59579009                       # Number of Instructions Simulated
system.cpu.committedOps                      76926775                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              59579009                       # Number of Instructions Simulated
system.cpu.cpi                               6.904312                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         6.904312                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.144837                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.144837                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                558200782                       # number of integer regfile reads
system.cpu.int_regfile_writes                89400906                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8900                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2982                       # number of floating regfile writes
system.cpu.misc_regfile_reads               135543435                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 912729                       # number of misc regfile writes
system.cpu.icache.replacements                1019271                       # number of replacements
system.cpu.icache.tagsinuse                511.444719                       # Cycle average of tags in use
system.cpu.icache.total_refs                 12598089                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1019783                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  12.353696                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6290137000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.444719                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.998915                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.998915                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     12598089                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12598089                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12598089                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12598089                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12598089                       # number of overall hits
system.cpu.icache.overall_hits::total        12598089                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1111711                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1111711                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1111711                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1111711                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1111711                       # number of overall misses
system.cpu.icache.overall_misses::total       1111711                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16369836984                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16369836984                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16369836984                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16369836984                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16369836984                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16369836984                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13709800                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13709800                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13709800                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13709800                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13709800                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13709800                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081089                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.081089                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.081089                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.081089                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.081089                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.081089                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14724.903310                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14724.903310                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2973484                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               393                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  7566.117048                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        60091                       # number of writebacks
system.cpu.icache.writebacks::total             60091                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91891                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        91891                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        91891                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        91891                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        91891                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        91891                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1019820                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1019820                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1019820                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1019820                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1019820                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1019820                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12187570984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12187570984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12187570984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12187570984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12187570984                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12187570984                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7292000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7292000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7292000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7292000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.074386                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.074386                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.074386                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.074386                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 645895                       # number of replacements
system.cpu.dcache.tagsinuse                511.991565                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 22075422                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 646407                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  34.150964                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               49188000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.991565                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     14216478                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        14216478                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7283636                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7283636                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       286092                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       286092                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       285655                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       285655                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21500114                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21500114                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21500114                       # number of overall hits
system.cpu.dcache.overall_hits::total        21500114                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       747655                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        747655                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2966865                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2966865                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13747                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13747                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           13                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3714520                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3714520                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3714520                       # number of overall misses
system.cpu.dcache.overall_misses::total       3714520                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  11237363500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  11237363500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110154178240                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    224042000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    224042000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       394000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       394000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 121391541740                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 121391541740                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 121391541740                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 121391541740                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14964133                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14964133                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10250501                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10250501                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299839                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       299839                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       285668                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       285668                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     25214634                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     25214634                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     25214634                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     25214634                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049963                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.049963                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289436                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289436                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045848                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045848                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000046                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000046                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.147316                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.147316                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.147316                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.147316                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     17091437                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      7607500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              3024                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             268                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5651.930225                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       574932                       # number of writebacks
system.cpu.dcache.writebacks::total            574932                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       359686                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       359686                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2717440                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2717440                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1386                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1386                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3077126                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3077126                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3077126                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3077126                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       387969                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       387969                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249425                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249425                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12361                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12361                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       637394                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       637394                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       637394                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       637394                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5287973500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5287973500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8908906437                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8908906437                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    165672500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    165672500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       351500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       351500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14196879937                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  14196879937                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14196879937                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  14196879937                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42255772015                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42255772015                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025927                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.025927                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024333                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024333                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041225                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041225                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000046                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000046                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025279                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025279                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025279                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    88053                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------