path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.400978                       # Number of seconds simulated
sim_ticks                                2400977890000                       # Number of ticks simulated
final_tick                               2400977890000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 187249                       # Simulator instruction rate (inst/s)
host_op_rate                                   225312                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7454963168                       # Simulator tick rate (ticks/s)
host_mem_usage                                 414124                       # Number of bytes of host memory used
host_seconds                                   322.06                       # Real time elapsed on the host
sim_insts                                    60306316                       # Number of instructions simulated
sim_ops                                      72565030                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           489736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          6827544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            79168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           799488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker          512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           187904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1451008                       # Number of bytes read from this memory
system.physmem.bytes_read::total            124654688                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       489736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        79168                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       187904                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          756808                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3741376                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1144160                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data        159264                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data       1712392                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6757192                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13864                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            106706                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1237                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             12492                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker            8                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              2936                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             22672                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14512303                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58459                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           286040                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data            39816                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           428098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812413                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47821795                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              203974                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2843651                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               32973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              332984                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               78261                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              604340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51918299                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         203974                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          32973                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          78261                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315208                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1558272                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             476539                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data              66333                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             713206                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2814350                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1558272                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47821795                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             203974                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3320191                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              32973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             399317                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          213                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              78261                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1317546                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54732649                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      13446786                       # Number of read requests accepted
system.physmem.writeReqs                       485691                       # Number of write requests accepted
system.physmem.readBursts                    13446786                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     485691                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                860594304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   3023744                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 109777664                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                3009384                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  438423                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           2870                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              835534                       # Per bank write bursts
system.physmem.perBankRdBursts::1              835708                       # Per bank write bursts
system.physmem.perBankRdBursts::2              835573                       # Per bank write bursts
system.physmem.perBankRdBursts::3              835895                       # Per bank write bursts
system.physmem.perBankRdBursts::4              836820                       # Per bank write bursts
system.physmem.perBankRdBursts::5              838059                       # Per bank write bursts
system.physmem.perBankRdBursts::6              838590                       # Per bank write bursts
system.physmem.perBankRdBursts::7              839423                       # Per bank write bursts
system.physmem.perBankRdBursts::8              841113                       # Per bank write bursts
system.physmem.perBankRdBursts::9              843484                       # Per bank write bursts
system.physmem.perBankRdBursts::10             843775                       # Per bank write bursts
system.physmem.perBankRdBursts::11             843709                       # Per bank write bursts
system.physmem.perBankRdBursts::12             845212                       # Per bank write bursts
system.physmem.perBankRdBursts::13             845578                       # Per bank write bursts
system.physmem.perBankRdBursts::14             844651                       # Per bank write bursts
system.physmem.perBankRdBursts::15             843662                       # Per bank write bursts
system.physmem.perBankWrBursts::0                2614                       # Per bank write bursts
system.physmem.perBankWrBursts::1                2619                       # Per bank write bursts
system.physmem.perBankWrBursts::2                2845                       # Per bank write bursts
system.physmem.perBankWrBursts::3                3084                       # Per bank write bursts
system.physmem.perBankWrBursts::4                3522                       # Per bank write bursts
system.physmem.perBankWrBursts::5                3545                       # Per bank write bursts
system.physmem.perBankWrBursts::6                2950                       # Per bank write bursts
system.physmem.perBankWrBursts::7                2539                       # Per bank write bursts
system.physmem.perBankWrBursts::8                2638                       # Per bank write bursts
system.physmem.perBankWrBursts::9                2619                       # Per bank write bursts
system.physmem.perBankWrBursts::10               2391                       # Per bank write bursts
system.physmem.perBankWrBursts::11               2507                       # Per bank write bursts
system.physmem.perBankWrBursts::12               3740                       # Per bank write bursts
system.physmem.perBankWrBursts::13               3837                       # Per bank write bursts
system.physmem.perBankWrBursts::14               3267                       # Per bank write bursts
system.physmem.perBankWrBursts::15               2529                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2398976781000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                13407440                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   39346                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 467914                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  17777                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    878947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    855123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    852879                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    944479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    861163                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    917283                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2393694                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2315582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3029092                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     97091                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    88809                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    83328                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    80474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    16579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    16189                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    16044                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2624                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     2682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     2704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     2534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     2534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     2591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     2515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     2520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     2531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     2487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       866162                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      997.062961                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     964.716097                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     145.162362                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           8098      0.93%      0.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8963      1.03%      1.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6105      0.70%      2.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          860      0.10%      2.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          965      0.11%      2.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          764      0.09%      2.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7665      0.88%      3.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          291      0.03%      3.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       832451     96.11%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         866162                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          2588                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      5195.817620                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    249325.060826                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287         2587     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.04%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            2588                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          2588                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.255796                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.093626                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.104963                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1                   2      0.08%      0.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   1      0.04%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   3      0.12%      0.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   1      0.04%      0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   2      0.08%      0.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7                   3      0.12%      0.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13                  2      0.08%      0.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14                  2      0.08%      0.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                  3      0.12%      0.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                555     21.45%     22.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  6      0.23%     22.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                738     28.52%     50.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1040     40.19%     91.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                103      3.98%     95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 50      1.93%     97.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 14      0.54%     97.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 11      0.43%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 13      0.50%     98.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  5      0.19%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  7      0.27%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  6      0.23%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  5      0.19%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  6      0.23%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  4      0.15%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  5      0.19%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  1      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            2588                       # Writes before turning the bus around for reads
system.physmem.totQLat                   347055171000                       # Total ticks spent queuing
system.physmem.totMemAccLat              599182408500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  67233930000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25809.53                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44559.53                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         358.43                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.26                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       45.72                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.25                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         7.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         2.52                       # Average write queue length when enqueuing
system.physmem.readRowHits                   12587076                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     40794                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  86.30                       # Row buffer hit rate for writes
system.physmem.avgGap                       172185.95                       # Average gap between requests
system.physmem.pageHitRate                      93.58                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2165163855000                       # Time in different power states
system.physmem.memoryStateTime::REF       80173860000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      155638381250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                3260847240                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                3287337480                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1779232125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1793686125                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0              52225695600                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1              52659235200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               153692640                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               152461440                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          156820070160                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          156820070160                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          104351437575                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          103839738030                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1349049300750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1349498160000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1667640276090                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1668050688435                       # Total energy per rank (pJ)
system.physmem.averagePower::0             694.567634                       # Core power per rank (mW)
system.physmem.averagePower::1             694.738569                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq            15564561                       # Transaction distribution
system.membus.trans_dist::ReadResp           15564561                       # Transaction distribution
system.membus.trans_dist::WriteReq             763190                       # Transaction distribution
system.membus.trans_dist::WriteResp            763190                       # Transaction distribution
system.membus.trans_dist::Writeback             58459                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4572                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4572                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131741                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131741                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382948                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1895349                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4281819                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     28704768                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     28704768                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               32986587                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      2390317                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         7020                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16592808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18990169                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    114819072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total    114819072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               133809241                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            216296                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  216296    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              216296                       # Request fanout histogram
system.membus.reqLayer0.occupancy           410119000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              415500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         14677410500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1676192784                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33189927250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    63154                       # number of replacements
system.l2c.tags.tagsinuse                50400.562310                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1759923                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   128542                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.691424                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2389821916000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36854.968320                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4866.476746                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3677.784289                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993335                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      799.149653                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      805.381857                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.908524                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1731.923626                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     1656.975819                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.562362                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074257                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.056119                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.012194                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.012289                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000105                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.026427                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.025283                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.769052                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65379                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3042                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6071                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55876                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000137                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997604                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17767412                       # Number of tag accesses
system.l2c.tags.data_accesses                17767412                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         8212                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         2860                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             436288                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             179343                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         2016                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker          871                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             118139                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              58618                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        19846                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         6099                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             333250                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             135884                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1301426                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          598065                       # number of Writeback hits
system.l2c.Writeback_hits::total               598065                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               9                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            52319                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            17211                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            44017                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113547                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          8212                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          2860                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              436288                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              231662                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          2016                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker           871                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              118139                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               75829                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         19846                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          6099                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              333250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              179901                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1414973                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         8212                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         2860                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             436288                       # number of overall hits
system.l2c.overall_hits::cpu0.data             231662                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         2016                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker          871                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             118139                       # number of overall hits
system.l2c.overall_hits::cpu1.data              75829                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        19846                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         6099                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             333250                       # number of overall hits
system.l2c.overall_hits::cpu2.data             179901                       # number of overall hits
system.l2c.overall_hits::total                1414973                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7238                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6279                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1237                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1211                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker            8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             2939                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data             2619                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21535                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1091                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           479                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1337                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2907                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         101010                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          11535                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          20861                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133406                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7238                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            107289                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1237                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             12746                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker            8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              2939                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             23480                       # number of demand (read+write) misses
system.l2c.demand_misses::total                154941                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7238                       # number of overall misses
system.l2c.overall_misses::cpu0.data           107289                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1237                       # number of overall misses
system.l2c.overall_misses::cpu1.data            12746                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker            8                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             2939                       # number of overall misses
system.l2c.overall_misses::cpu2.data            23480                       # number of overall misses
system.l2c.overall_misses::total               154941                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     87455000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     91702500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       793250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    215412250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    203455994                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      598893494                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        68997                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       185992                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       254989                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    818099996                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1544671950                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2362771946                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     87455000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    909802496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker       793250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    215412250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   1748127944                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2961665440                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     87455000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    909802496                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker       793250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    215412250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   1748127944                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2961665440                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8213                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         2862                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         443526                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         185622                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         2017                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker          871                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         119376                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          59829                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        19854                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         6099                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         336189                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         138503                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1322961                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       598065                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           598065                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1100                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          483                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1350                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2933                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       153329                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28746                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        64878                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246953                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8213                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         2862                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          443526                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          338951                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         2017                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker          871                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          119376                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           88575                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        19854                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         6099                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          336189                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          203381                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1569914                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8213                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         2862                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         443526                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         338951                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         2017                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker          871                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         119376                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          88575                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        19854                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         6099                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         336189                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         203381                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1569914                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000699                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016319                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.033827                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000496                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010362                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.020241                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000403                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.008742                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.018909                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016278                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991818                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991718                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.990370                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991135                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.658779                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.401273                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.321542                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.540208                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000699                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016319                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.316532                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000496                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010362                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.143901                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000403                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.008742                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.115448                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098694                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000699                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016319                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.316532                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000496                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010362                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.143901                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000403                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.008742                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.115448                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098694                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70699.272433                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75724.607762                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99156.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 73294.402858                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 77684.610157                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 27810.238867                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   144.043841                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   139.111444                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total    87.715514                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70923.276636                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74045.920617                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 17711.137025                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 70699.272433                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71379.452063                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99156.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 73294.402858                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74451.786371                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 19114.794922                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 70699.272433                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71379.452063                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99156.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 73294.402858                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74451.786371                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 19114.794922                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58459                       # number of writebacks
system.l2c.writebacks::total                    58459                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1237                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1211                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker            8                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         2936                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data         2611                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8004                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          479                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1337                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1816                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        11535                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        20861                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         32396                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1237                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        12746                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker            8                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         2936                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        23472                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40400                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1237                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        12746                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker            8                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         2936                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        23472                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40400                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     71795000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     76590000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       694750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    178440250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    170505244                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    498087744                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4790479                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     13376836                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     18167315                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    671834504                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1285363050                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1957197554                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     71795000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    748424504                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       694750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    178440250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1455868294                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2455285298                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     71795000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    748424504                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       694750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    178440250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1455868294                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2455285298                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  24982050000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  25464087500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  50446137500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    975342097                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   9141414000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  10116756097                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  25957392097                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34605501500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60562893597                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000496                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010362                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020241                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000403                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.008733                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018852                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006050                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991718                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.990370                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.619161                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.401273                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.321542                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.131183                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000496                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010362                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.143901                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000403                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.008733                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.115409                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.025734                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000496                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010362                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.143901                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000403                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.008733                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.115409                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.025734                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60774.388564                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60774.388564                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            2539315                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2539315                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763190                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763190                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           598065                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2933                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2933                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           246953                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          246953                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1813392                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5760169                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        30385                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        80672                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7684618                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     57608092                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     84067517                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        48464                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       138604                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              141862677                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           18229                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2196613                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean                   5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                2196613    100.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2196613                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2287106157                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2054352798                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1912625851                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          13149443                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          33486737                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq             15535704                       # Transaction distribution
system.iobus.trans_dist::ReadResp            15535704                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8154                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8154                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30010                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          492                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1000                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          732                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     28704768                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     28704768                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                31087716                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        39305                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        15868                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio          984                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         2000                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          390                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      2390317                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    114819072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total    114819072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                117209389                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              8534000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              1569000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               143000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy            352708000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy         13407440000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           717460000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         33785464750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     6552093                       # DTB read hits
system.cpu0.dtb.read_misses                      5443                       # DTB read misses
system.cpu0.dtb.write_hits                    6067983                       # DTB write hits
system.cpu0.dtb.write_misses                     1816                       # DTB write misses
system.cpu0.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                496                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     22                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5219                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   108                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      162                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 6557536                       # DTB read accesses
system.cpu0.dtb.write_accesses                6069799                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12620076                       # DTB hits
system.cpu0.dtb.misses                           7259                       # DTB misses
system.cpu0.dtb.accesses                     12627335                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    30154576                       # ITB inst hits
system.cpu0.itb.inst_misses                      2994                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                496                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     22                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2367                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                30157570                       # ITB inst accesses
system.cpu0.itb.hits                         30154576                       # DTB hits
system.cpu0.itb.misses                           2994                       # DTB misses
system.cpu0.itb.accesses                     30157570                       # DTB accesses
system.cpu0.numCycles                       109411317                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   29741333                       # Number of instructions committed
system.cpu0.committedOps                     36475405                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             32123717                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4289                       # Number of float alu accesses
system.cpu0.num_func_calls                    1120042                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3813280                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    32123717                       # number of integer instructions
system.cpu0.num_fp_insts                         4289                       # number of float instructions
system.cpu0.num_int_register_reads           59486063                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          21170898                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3327                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                964                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           109224829                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           14221647                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13081203                       # number of memory refs
system.cpu0.num_load_insts                    6727170                       # Number of load instructions
system.cpu0.num_store_insts                   6354033                       # Number of store instructions
system.cpu0.num_idle_cycles              107121976.742744                       # Number of idle cycles
system.cpu0.num_busy_cycles              2289340.257256                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.020924                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.979076                       # Percentage of idle cycles
system.cpu0.Branches                          5305474                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                11839      0.03%      0.03% # Class of executed instruction
system.cpu0.op_class::IntAlu                 23401650     64.04%     64.07% # Class of executed instruction
system.cpu0.op_class::IntMult                   45463      0.12%     64.20% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              1432      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::MemRead                 6727170     18.41%     82.61% # Class of executed instruction
system.cpu0.op_class::MemWrite                6354033     17.39%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  36541587                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   82908                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           899905                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.617888                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           41210869                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           900417                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            45.768648                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7755633000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   495.394938                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     5.639138                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.583812                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.967568                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.011014                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.020672                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999254                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          216                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          154                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         43039595                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        43039595                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     29712798                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7804770                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3693301                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       41210869                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29712798                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7804770                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3693301                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        41210869                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29712798                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7804770                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3693301                       # number of overall hits
system.cpu0.icache.overall_hits::total       41210869                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       444147                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       119626                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       364535                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       928308                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       444147                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       119626                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       364535                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        928308                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       444147                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       119626                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       364535                       # number of overall misses
system.cpu0.icache.overall_misses::total       928308                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1633550000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4883016924                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6516566924                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1633550000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4883016924                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6516566924                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1633550000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4883016924                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6516566924                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     30156945                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7924396                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      4057836                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     42139177                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     30156945                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7924396                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      4057836                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     42139177                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     30156945                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7924396                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      4057836                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     42139177                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014728                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015096                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.089835                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.022030                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014728                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015096                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.089835                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.022030                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014728                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015096                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.089835                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.022030                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13655.476234                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13395.193669                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  7019.832775                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13655.476234                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13395.193669                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  7019.832775                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13655.476234                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13395.193669                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  7019.832775                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3227                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              203                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.896552                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        27890                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        27890                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        27890                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        27890                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        27890                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        27890                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       119626                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       336645                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       456271                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       119626                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       336645                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       456271                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       119626                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       336645                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       456271                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1393831000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3968205684                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5362036684                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1393831000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3968205684                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5362036684                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1393831000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3968205684                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5362036684                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015096                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.082962                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010828                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015096                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.082962                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010828                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015096                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.082962                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010828                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11651.572401                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.508158                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11751.868263                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11651.572401                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.508158                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11751.868263                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11651.572401                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.508158                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11751.868263                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           630395                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997117                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           21342587                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           630907                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            33.828420                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         21757000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.646695                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.878290                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.472132                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971966                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015387                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.012641                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          207                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         92223227                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        92223227                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5368302                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1446025                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4735634                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11549961                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5498373                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1267433                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2446281                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9212087                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        53662                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        14249                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        23655                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        91566                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       122592                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        31381                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        84607                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       238580                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       128647                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        32825                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        85920                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247392                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10866675                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      2713458                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7181915                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        20762048                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10920337                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      2727707                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7205570                       # number of overall hits
system.cpu0.dcache.overall_hits::total       20853614                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       142563                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        45260                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       257630                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       445453                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       154429                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        29884                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       820485                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1004798                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        37003                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17467                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data        41789                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total        96259                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6056                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1445                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         4483                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11984                       # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data       296992                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        75144                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1078115                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1450251                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       333995                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data        92611                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1119904                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1546510                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    611214249                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3612191655                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4223405904                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1124082233                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  26974160361                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  28098242594                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     19515250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     65554993                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     85070243                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   1735296482                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  30586352016                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  32321648498                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   1735296482                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  30586352016                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  32321648498                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5510865                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1491285                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4993264                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     11995414                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5652802                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1297317                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3266766                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10216885                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        90665                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        31716                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        65444                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       187825                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       128648                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        32826                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        89090                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       250564                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       128647                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        32825                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        85920                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247392                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11163667                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2788602                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      8260030                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     22212299                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11254332                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2820318                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8325474                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     22400124                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025869                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030350                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.051596                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037135                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027319                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.023035                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.251161                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.098347                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.408129                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.550731                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.638546                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.512493                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047074                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044020                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.050320                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047828                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026603                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026947                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.130522                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.065290                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029677                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032837                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134515                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.069040                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13504.512793                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14020.850270                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9481.148188                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37614.851861                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32875.872638                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 27964.070981                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13505.363322                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14623.018737                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7098.651786                       # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23092.947967                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28370.212840                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22286.934122                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18737.476995                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27311.583864                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 20899.734562                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        35984                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         7309                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             5054                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            190                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     7.119905                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    38.468421                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       598065                       # number of writebacks
system.cpu0.dcache.writebacks::total           598065                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           80                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       146918                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       146998                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data          655                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       754285                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       754940                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          469                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          469                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          735                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       901203                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       901938                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          735                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       901203                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       901938                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        45180                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       110712                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       155892                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        29229                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        66200                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total        95429                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        13204                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        23805                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        37009                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1445                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         4014                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5459                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        74409                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       176912                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       251321                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data        87613                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       200717                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       288330                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    520028500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1350346488                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1870374988                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1032772017                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2131682211                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3164454228                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    203990750                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    439543502                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    643534252                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     16622750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     51408007                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     68030757                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1552800517                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3482028699                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5034829216                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1756791267                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3921572201                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5678363468                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27292544500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  27798821000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55091365500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1484661903                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  14572262972                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  16056924875                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28777206403                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42371083972                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  71148290375                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.030296                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.022172                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.012996                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.022530                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.020265                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009340                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.416320                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.363746                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.197040                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044020                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.045056                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.021787                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026683                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.021418                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.011314                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031065                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024109                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.012872                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11510.148296                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12196.929764                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11997.889488                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     1733555                       # DTB read hits
system.cpu1.dtb.read_misses                      1889                       # DTB read misses
system.cpu1.dtb.write_hits                    1370998                       # DTB write hits
system.cpu1.dtb.write_misses                      367                       # DTB write misses
system.cpu1.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                248                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     11                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1592                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                    28                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       77                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 1735444                       # DTB read accesses
system.cpu1.dtb.write_accesses                1371365                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          3104553                       # DTB hits
system.cpu1.dtb.misses                           2256                       # DTB misses
system.cpu1.dtb.accesses                      3106809                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7924396                       # ITB inst hits
system.cpu1.itb.inst_misses                      1030                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                248                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     11                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     806                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7925426                       # ITB inst accesses
system.cpu1.itb.hits                          7924396                       # DTB hits
system.cpu1.itb.misses                           1030                       # DTB misses
system.cpu1.itb.accesses                      7925426                       # DTB accesses
system.cpu1.numCycles                       582686408                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7745878                       # Number of instructions committed
system.cpu1.committedOps                      9129746                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              8166989                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1689                       # Number of float alu accesses
system.cpu1.num_func_calls                     287006                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       983778                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     8166989                       # number of integer instructions
system.cpu1.num_fp_insts                         1689                       # number of float instructions
system.cpu1.num_int_register_reads           14466592                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5466665                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1177                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                512                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            32997995                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            3759402                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      3229777                       # number of memory refs
system.cpu1.num_load_insts                    1791377                       # Number of load instructions
system.cpu1.num_store_insts                   1438400                       # Number of store instructions
system.cpu1.num_idle_cycles              548052403.807954                       # Number of idle cycles
system.cpu1.num_busy_cycles              34634004.192046                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.059438                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.940562                       # Percentage of idle cycles
system.cpu1.Branches                          1348409                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 4600      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                  6037827     65.04%     65.09% # Class of executed instruction
system.cpu1.op_class::IntMult                   10088      0.11%     65.20% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               273      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::MemRead                 1791377     19.30%     84.50% # Class of executed instruction
system.cpu1.op_class::MemWrite                1438400     15.50%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                   9282565                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups                5846326                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          4388844                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           249586                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3633950                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2855743                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            78.585093                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 589622                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             15464                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    13911313                       # DTB read hits
system.cpu2.dtb.read_misses                     27890                       # DTB read misses
system.cpu2.dtb.write_hits                    3983127                       # DTB write hits
system.cpu2.dtb.write_misses                     9793                       # DTB write misses
system.cpu2.dtb.flush_tlb                         550                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2737                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      484                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   262                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      640                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                13939203                       # DTB read accesses
system.cpu2.dtb.write_accesses                3992920                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         17894440                       # DTB hits
system.cpu2.dtb.misses                          37683                       # DTB misses
system.cpu2.dtb.accesses                     17932123                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.inst_hits                     4060759                       # ITB inst hits
system.cpu2.itb.inst_misses                      6577                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         550                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    2055                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     2376                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                 4067336                       # ITB inst accesses
system.cpu2.itb.hits                          4060759                       # DTB hits
system.cpu2.itb.misses                           6577                       # DTB misses
system.cpu2.itb.accesses                      4067336                       # DTB accesses
system.cpu2.numCycles                        88050542                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10519234                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      32939379                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    5846326                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           3445365                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     74770225                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 681136                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     80231                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                 505                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              954                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        72091                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles      1265694                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          337                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  4057838                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               153485                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2814                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          87049769                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             0.444404                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            1.631683                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                79735168     91.60%     91.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  627849      0.72%     92.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  697488      0.80%     93.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  764418      0.88%     94.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  855506      0.98%     94.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  578096      0.66%     95.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  986877      1.13%     96.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  299514      0.34%     97.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 2504853      2.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            87049769                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.066397                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.374096                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8593092                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             72401111                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  4830102                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               941679                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                282689                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              738219                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                58888                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              34839136                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               197306                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                282689                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 9053752                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               19270728                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      13147343                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  5254066                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             40040151                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              33787886                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                74120                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents              29496747                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents              37523489                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               1004110                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands           36611560                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            154353600                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        41662755                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups             4122                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             28819307                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 7792237                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            344984                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        287406                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  5085187                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6095255                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            4404078                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           715172                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores         1132058                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  32032092                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             661150                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 38610720                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            45237                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        5536917                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     12037471                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        230168                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     87049769                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.443548                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.240485                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           73601742     84.55%     84.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            4103417      4.71%     89.27% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            2329810      2.68%     91.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2044829      2.35%     94.29% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            2965004      3.41%     97.70% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             800473      0.92%     98.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             744836      0.86%     99.47% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             295465      0.34%     99.81% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             164193      0.19%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       87049769                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                 123164      5.43%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     2      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      5.43% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               1963174     86.51%     91.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               182867      8.06%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            12079      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             20212271     52.35%     52.38% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               34343      0.09%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc           410      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     52.47% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            14161220     36.68%     89.15% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            4190397     10.85%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              38610720                       # Type of FU issued
system.cpu2.iq.rate                          0.438506                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2269207                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.058771                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         166576049                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         38242231                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     29605417                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               9604                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              5150                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         4304                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              40862730                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   5118                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          177793                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1108149                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         2013                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation        17977                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       469749                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      5186465                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked      3515984                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                282689                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               17818885                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               827114                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32812972                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            58820                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6095255                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             4404078                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            482366                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 63304                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents               726253                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents         17977                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        122015                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       106758                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              228773                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             38292590                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             14036165                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           280577                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                       119730                       # number of nop insts executed
system.cpu2.iew.exec_refs                    18176329                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 4221740                       # Number of branches executed
system.cpu2.iew.exec_stores                   4140164                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.434893                       # Inst execution rate
system.cpu2.iew.wb_sent                      34848706                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     29609721                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 17270580                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 30711387                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.336281                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.562351                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        5477647                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         430982                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           191637                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     86152512                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.313795                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.238508                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     77159399     89.56%     89.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4186602      4.86%     94.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1295333      1.50%     95.92% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3       754876      0.88%     96.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       491618      0.57%     97.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       381305      0.44%     97.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       375733      0.44%     98.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       196216      0.23%     98.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1311430      1.52%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     86152512                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            22893469                       # Number of instructions committed
system.cpu2.commit.committedOps              27034243                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8921435                       # Number of memory references committed
system.cpu2.commit.loads                      4987106                       # Number of loads committed
system.cpu2.commit.membars                     117312                       # Number of memory barriers committed
system.cpu2.commit.branches                   3648396                       # Number of branches committed
system.cpu2.commit.fp_insts                      4270                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 23927319                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              341825                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        18080099     66.88%     66.88% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          32299      0.12%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc          410      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        4987106     18.45%     85.45% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3934329     14.55%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         27034243                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1311430                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   116684345                       # The number of ROB reads
system.cpu2.rob.rob_writes                   65897015                       # The number of ROB writes
system.cpu2.timesIdled                         179321                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1000773                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  3544672545                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   22819105                       # Number of Instructions Simulated
system.cpu2.committedOps                     26959879                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              3.858633                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        3.858633                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.259159                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.259159                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                45005013                       # number of integer regfile reads
system.cpu2.int_regfile_writes               19153075                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    47120                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   45464                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                130804455                       # number of cc regfile reads
system.cpu2.cc_regfile_writes                12559622                       # number of cc regfile writes
system.cpu2.misc_regfile_reads              122469878                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                350259                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1536462300750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------