path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.403596                       # Number of seconds simulated
sim_ticks                                2403595690000                       # Number of ticks simulated
final_tick                               2403595690000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 196358                       # Simulator instruction rate (inst/s)
host_op_rate                                   252199                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7823307249                       # Simulator tick rate (ticks/s)
host_mem_usage                                 401444                       # Number of bytes of host memory used
host_seconds                                   307.24                       # Real time elapsed on the host
sim_insts                                    60328186                       # Number of instructions simulated
sim_ops                                      77484426                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           511520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          7050896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            64832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           677568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           187392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1347680                       # Number of bytes read from this memory
system.physmem.bytes_read::total            124659728                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       511520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        64832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       187392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          763744                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3743680                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1298324                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data        159300                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data       1558192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6759496                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             14195                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            110204                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1013                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10587                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              2928                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             21065                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14512388                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58495                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           324581                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data            39825                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           389548                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812449                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47769711                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              212814                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2933478                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               26973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              281898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           186                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               77963                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              560693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51863851                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         212814                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          26973                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          77963                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             317751                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1557533                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             540159                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data              66276                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             648275                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2812243                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1557533                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47769711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             212814                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3473637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              26973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             348173                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          186                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              77963                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1208969                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54676094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      13479442                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       446461                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                    13479442                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     446461                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                    862684288                       # Total number of bytes read from memory
system.physmem.bytesWritten                  28573504                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              109828768                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                2811124                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               2349                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                837727                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                837365                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                837535                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                838843                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                839834                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                839919                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                839832                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                840753                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                841921                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                844340                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               845026                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               846543                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               848256                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               848014                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               846904                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               846630                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  2743                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  2603                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  2565                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  3057                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  3449                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  3230                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  2572                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  2333                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  2233                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  2428                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 2377                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 2821                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 3826                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 3451                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 2698                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 2556                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2402560453500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       8                       # Categorize read packet sizes
system.physmem.readPktSize::3                13443840                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                   35594                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 429373                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  17088                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    871692                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    848345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    868847                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3321058                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2492431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2492072                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2465727                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     13654                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     13341                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     25821                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    38140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    25648                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      671                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      665                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      657                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      651                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       19                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     1917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     1914                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     1909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     1908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        22080                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    39201.023188                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    6463.207550                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   31878.388388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-79           3036     13.75%     13.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-143         1347      6.10%     19.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-207          793      3.59%     23.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-271          589      2.67%     26.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-335          391      1.77%     27.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-399          355      1.61%     29.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-463          279      1.26%     30.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-527          235      1.06%     31.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-591          172      0.78%     32.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-655          146      0.66%     33.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-719          130      0.59%     33.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-783          164      0.74%     34.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-847           77      0.35%     34.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-911           80      0.36%     35.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-975           63      0.29%     35.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1039           74      0.34%     35.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1103           30      0.14%     36.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1167           39      0.18%     36.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1231           22      0.10%     36.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1295           39      0.18%     36.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1359           28      0.13%     36.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1423           83      0.38%     37.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1487           95      0.43%     37.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1551          108      0.49%     37.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1615           17      0.08%     38.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1679           45      0.20%     38.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1743           23      0.10%     38.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1807           32      0.14%     38.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1871           10      0.05%     38.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1935           20      0.09%     38.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1999            6      0.03%     38.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2063           23      0.10%     38.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2127            8      0.04%     38.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2191           15      0.07%     38.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2255            1      0.00%     38.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2319            6      0.03%     38.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2383            4      0.02%     38.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2447           10      0.05%     38.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2511            3      0.01%     38.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2575            2      0.01%     38.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2639            1      0.00%     38.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2703            3      0.01%     38.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2767            5      0.02%     38.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2831            8      0.04%     39.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2895            3      0.01%     39.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2959            3      0.01%     39.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3023            1      0.00%     39.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3087            6      0.03%     39.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3151            2      0.01%     39.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3215            2      0.01%     39.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3279            5      0.02%     39.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3343            6      0.03%     39.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3407            2      0.01%     39.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3471            3      0.01%     39.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3535            1      0.00%     39.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3599            2      0.01%     39.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3663            2      0.01%     39.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3727            2      0.01%     39.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3791            3      0.01%     39.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3855            1      0.00%     39.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4047            3      0.01%     39.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4111            7      0.03%     39.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4367            3      0.01%     39.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4431            1      0.00%     39.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4687            2      0.01%     39.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4815            2      0.01%     39.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4943            1      0.00%     39.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5007            2      0.01%     39.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5135            1      0.00%     39.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5391            2      0.01%     39.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5455            1      0.00%     39.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6287            1      0.00%     39.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6479            1      0.00%     39.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6543            3      0.01%     39.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6799           15      0.07%     39.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6863            2      0.01%     39.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6991            1      0.00%     39.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7055            3      0.01%     39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7183            3      0.01%     39.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7375            2      0.01%     39.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7439            1      0.00%     39.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7695            1      0.00%     39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7759            1      0.00%     39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7951            2      0.01%     39.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8079            1      0.00%     39.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8207            3      0.01%     39.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8463           45      0.20%     39.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8527          150      0.68%     40.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8591           12      0.05%     40.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8975            1      0.00%     40.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9231            1      0.00%     40.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9487            1      0.00%     40.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12047            2      0.01%     40.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14863            1      0.00%     40.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16335            1      0.00%     40.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17423            1      0.00%     40.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17679            1      0.00%     40.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20239            1      0.00%     40.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22799            1      0.00%     40.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24591            1      0.00%     40.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25871            1      0.00%     40.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27663            1      0.00%     40.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29455            1      0.00%     40.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30735            2      0.01%     40.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31247            1      0.00%     40.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33039            1      0.00%     40.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33295            3      0.01%     40.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33807            1      0.00%     40.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34319            1      0.00%     40.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34831            1      0.00%     40.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35855            1      0.00%     40.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37903            1      0.00%     40.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38927            1      0.00%     40.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40207            1      0.00%     40.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40975            1      0.00%     40.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41999            1      0.00%     40.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42767            1      0.00%     40.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47887            1      0.00%     40.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52239            1      0.00%     40.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53263            1      0.00%     40.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53504-53519            1      0.00%     40.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56064-56079            1      0.00%     40.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59392-59407            1      0.00%     40.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65551        13109     59.37%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          22080                       # Bytes accessed per row activation
system.physmem.totQLat                   259652718750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              339530350000                       # Sum of mem lat for all requests
system.physmem.totBusLat                  67397210000                       # Total cycles spent in databus access
system.physmem.totBankLat                 12480421250                       # Total cycles spent in bank access
system.physmem.avgQLat                       19262.87                       # Average queueing delay per request
system.physmem.avgBankLat                      925.89                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  25188.75                       # Average memory access latency
system.physmem.avgRdBW                         358.91                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          11.89                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  45.69                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.17                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.90                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.14                       # Average read queue length over time
system.physmem.avgWrQLen                         0.39                       # Average write queue length over time
system.physmem.readRowHits                   13462207                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     40077                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                   8.98                       # Row buffer hit rate for writes
system.physmem.avgGap                       172524.57                       # Average gap between requests
system.membus.throughput                     55673401                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            13817014                       # Transaction distribution
system.membus.trans_dist::ReadResp           13817014                       # Transaction distribution
system.membus.trans_dist::WriteReq             432240                       # Transaction distribution
system.membus.trans_dist::WriteResp            432240                       # Transaction distribution
system.membus.trans_dist::Writeback             17088                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2349                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2349                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28007                       # Transaction distribution
system.membus.trans_dist::ReadExResp            28007                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       736658                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          234                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951736                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1688628                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26887680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     26887680                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               28576308                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       740538                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          468                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5089172                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      5830178                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107550720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    107550720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           113380898                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              133816346                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           415555000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              219000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         14607219000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1602404901                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        30345557250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.l2c.tags.replacements                    63232                       # number of replacements
system.l2c.tags.tagsinuse                50385.545216                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1748703                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   128626                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.595253                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2375561795000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36863.517049                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000124                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5225.910742                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3838.689123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993318                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      514.601539                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      693.553663                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.833611                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker     0.974677                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1665.560742                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     1574.910611                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.562493                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.079741                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.058574                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.007852                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.010583                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000104                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.025414                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.024031                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.768822                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         8792                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             468268                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             177348                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         2569                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1162                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             128925                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              64565                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        18612                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         4274                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             281840                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             131110                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1290694                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          597529                       # number of Writeback hits
system.l2c.Writeback_hits::total               597529                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              11                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  29                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            61796                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            18660                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            33186                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113642                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          8792                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3229                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              468268                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              239144                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          2569                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1162                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              128925                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               83225                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         18612                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          4274                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              281840                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              164296                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1404336                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         8792                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3229                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             468268                       # number of overall hits
system.l2c.overall_hits::cpu0.data             239144                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         2569                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1162                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             128925                       # number of overall hits
system.l2c.overall_hits::cpu1.data              83225                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        18612                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         4274                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             281840                       # number of overall hits
system.l2c.overall_hits::cpu2.data             164296                       # number of overall hits
system.l2c.overall_hits::total                1404336                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7579                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6466                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1013                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1126                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker            7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             2929                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data             2523                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21648                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1417                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           474                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1014                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2905                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         104500                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9736                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          19132                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133368                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7579                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            110966                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1013                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10862                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              2929                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             21655                       # number of demand (read+write) misses
system.l2c.demand_misses::total                155016                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7579                       # number of overall misses
system.l2c.overall_misses::cpu0.data           110966                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1013                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10862                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             2929                       # number of overall misses
system.l2c.overall_misses::cpu2.data            21655                       # number of overall misses
system.l2c.overall_misses::total               155016                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        88750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     75420750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     83519750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       595250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker        88750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    229132750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    191859499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      580705499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        93996                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       163493                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       257489                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    623287225                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1332698664                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1955985889                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        88750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     75420750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    706806975                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker       595250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker        88750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    229132750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   1524558163                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2536691388                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        88750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     75420750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    706806975                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker       595250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker        88750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    229132750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   1524558163                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2536691388                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8793                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3231                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         475847                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         183814                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         2570                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1162                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         129938                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          65691                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        18619                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         4275                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         284769                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         133633                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1312342                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       597529                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           597529                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1431                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          478                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1025                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2934                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       166296                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28396                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        52318                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247010                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8793                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3231                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          475847                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          350110                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         2570                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1162                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          129938                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           94087                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        18619                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         4275                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          284769                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          185951                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1559352                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8793                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3231                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         475847                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         350110                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         2570                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1162                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         129938                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          94087                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        18619                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         4275                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         284769                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         185951                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1559352                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000114                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000619                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015927                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.035177                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000389                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.007796                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.017141                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000376                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000234                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.010286                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.018880                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016496                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990217                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991632                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.989268                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.990116                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.628398                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.342865                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.365687                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.539930                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000114                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000619                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015927                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.316946                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000389                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007796                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.115446                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000376                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.000234                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.010286                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.116455                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.099411                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000114                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000619                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015927                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.316946                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000389                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007796                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.115446                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000376                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.000234                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.010286                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.116455                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.099411                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        88750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74452.862784                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74173.845471                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85035.714286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        88750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78229.003073                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 76044.193024                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 26824.902947                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   198.303797                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   161.235700                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total    88.636489                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64018.819330                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 69658.094501                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 14666.080986                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        88750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74452.862784                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 65071.531486                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85035.714286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker        88750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78229.003073                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 70402.131748                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 16364.061697                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        88750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74452.862784                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 65071.531486                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85035.714286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker        88750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78229.003073                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 70402.131748                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 16364.061697                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58495                       # number of writebacks
system.l2c.writebacks::total                    58495                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data            12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1013                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1126                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         2928                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data         2511                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7587                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          474                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1014                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1488                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9736                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        19132                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         28868                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1013                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10862                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         2928                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        21643                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            36455                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1013                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10862                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         2928                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        21643                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           36455                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     62622750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     69218750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       506250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    191992000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    159345749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    483837999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4740474                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10141014                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     14881488                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    500926275                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1090069836                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1590996111                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     62622750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    570145025                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       506250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    191992000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1249415585                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2074834110                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     62622750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    570145025                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       506250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    191992000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1249415585                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2074834110                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25122070000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26464740500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  51586810500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    939177000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8518259500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   9457436500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26061247000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34983000000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  61044247000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000389                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007796                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017141                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000376                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000234                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010282                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018790                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005781                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991632                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.989268                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.507157                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.342865                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.365687                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.116870                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000389                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007796                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.115446                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000376                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000234                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010282                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.116391                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.023378                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000389                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007796                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.115446                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000376                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000234                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010282                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.116391                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.023378                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61819.101678                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61473.134991                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65571.038251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63459.079650                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63771.978252                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51450.932108                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 56976.261551                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 55112.793093                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61819.101678                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52489.875253                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65571.038251                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 57728.391859                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 56914.939240                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61819.101678                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52489.875253                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 56914.939240                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58805533                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            1021031                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1021030                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            432240                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           432240                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           264941                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1503                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1506                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            80714                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           80714                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       830128                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2423683                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15492                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        51832                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               3321135                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26541184                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37337186                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21748                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        84756                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           63984874                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             141242678                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          102048                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2176255494                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1870489205                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1849664390                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          10070717                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          30771737                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48764104                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             13809372                       # Transaction distribution
system.iobus.trans_dist::ReadResp            13809372                       # Transaction distribution
system.iobus.trans_dist::WriteReq                2797                       # Transaction distribution
system.iobus.trans_dist::WriteResp               2797                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11494                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           22                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       721570                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       736658                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26887680                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     26887680                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                27624338                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15458                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6052                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           44                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          516                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       717892                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       740538                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107550720                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107550720                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            108291258                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               117209190                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              8031000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              1513000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                22000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               129000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy            361287000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         13443840000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           733861000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         36856295750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8004008                       # DTB read hits
system.cpu0.dtb.read_misses                      6222                       # DTB read misses
system.cpu0.dtb.write_hits                    6595133                       # DTB write hits
system.cpu0.dtb.write_misses                     2001                       # DTB write misses
system.cpu0.dtb.flush_tlb                         279                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                685                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5693                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   118                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8010230                       # DTB read accesses
system.cpu0.dtb.write_accesses                6597134                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14599141                       # DTB hits
system.cpu0.dtb.misses                           8223                       # DTB misses
system.cpu0.dtb.accesses                     14607364                       # DTB accesses
system.cpu0.itb.inst_hits                    32379967                       # ITB inst hits
system.cpu0.itb.inst_misses                      3492                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         279                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                685                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2598                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                32383459                       # ITB inst accesses
system.cpu0.itb.hits                         32379967                       # DTB hits
system.cpu0.itb.misses                           3492                       # DTB misses
system.cpu0.itb.accesses                     32383459                       # DTB accesses
system.cpu0.numCycles                       113662532                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   31896171                       # Number of instructions committed
system.cpu0.committedOps                     42061376                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             37196625                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5021                       # Number of float alu accesses
system.cpu0.num_func_calls                    1200231                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4252287                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    37196625                       # number of integer instructions
system.cpu0.num_fp_insts                         5021                       # number of float instructions
system.cpu0.num_int_register_reads          189594254                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          39319391                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3591                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1432                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     15267333                       # number of memory refs
system.cpu0.num_load_insts                    8373046                       # Number of load instructions
system.cpu0.num_store_insts                   6894287                       # Number of store instructions
system.cpu0.num_idle_cycles              110849279.389256                       # Number of idle cycles
system.cpu0.num_busy_cycles              2813252.610744                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.024751                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.975249                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           891479                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.603901                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           43691974                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           891991                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            48.982528                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       8175687500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   493.614782                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.336202                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.652916                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.964091                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014329                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.020806                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999226                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     31906072                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      8054900                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3731002                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       43691974                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     31906072                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      8054900                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3731002                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        43691974                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     31906072                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      8054900                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3731002                       # number of overall hits
system.cpu0.icache.overall_hits::total       43691974                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       476577                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       130192                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       309459                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       916228                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       476577                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       130192                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       309459                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        916228                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       476577                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       130192                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       309459                       # number of overall misses
system.cpu0.icache.overall_misses::total       916228                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1761830250                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4180298881                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5942129131                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1761830250                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4180298881                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5942129131                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1761830250                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4180298881                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5942129131                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     32382649                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      8185092                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      4040461                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     44608202                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     32382649                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      8185092                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      4040461                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     44608202                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     32382649                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      8185092                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      4040461                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     44608202                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014717                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015906                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076590                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.020539                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014717                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015906                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076590                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.020539                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014717                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015906                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076590                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.020539                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6485.426260                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6485.426260                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6485.426260                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4261                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              235                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.131915                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24229                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        24229                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        24229                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        24229                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        24229                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        24229                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130192                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       285230                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       415422                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       130192                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       285230                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       415422                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       130192                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       285230                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       415422                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1500951750                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3402203278                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4903155028                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1500951750                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3402203278                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4903155028                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1500951750                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3402203278                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4903155028                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015906                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070593                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009313                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015906                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070593                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009313                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015906                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070593                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009313                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11528.755607                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11927.929313                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11802.829479                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11528.755607                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11927.929313                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11802.829479                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11528.755607                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11927.929313                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11802.829479                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           629636                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997119                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           23222123                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           630148                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            36.851855                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         21763000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.117005                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.034615                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.845498                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970932                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015693                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013370                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6875315                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1820667                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4627275                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13323257                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5963983                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1316466                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2129753                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9410202                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131811                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33157                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73317                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       238285                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138270                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34889                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74229                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247388                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12839298                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      3137133                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6757028                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        22733459                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12839298                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      3137133                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6757028                       # number of overall hits
system.cpu0.dcache.overall_hits::total       22733459                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       177356                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        63959                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       269175                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       510490                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       167727                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        28874                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       609519                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       806120                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6458                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1732                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3768                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11958                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            3                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       345083                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        92833                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       878694                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1316610                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       345083                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data        92833                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data       878694                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1316610                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    908429000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3875625037                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4784054037                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    912156249                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22615267762                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  23527424011                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     22739750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     50485499                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     73225249                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        39000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        39000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   1820585249                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  26490892799                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  28311478048                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   1820585249                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  26490892799                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  28311478048                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7052671                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1884626                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4896450                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13833747                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      6131710                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1345340                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2739272                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10216322                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138269                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34889                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77085                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       250243                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138270                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34889                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74232                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247391                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13184381                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      3229966                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7635722                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24050069                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13184381                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      3229966                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7635722                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24050069                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025147                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033937                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.054974                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036902                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027354                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021462                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.222511                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.078905                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046706                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049643                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048881                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047786                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000040                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000012                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026174                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028741                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115077                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.054745                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026174                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028741                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.115077                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.054745                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14203.302115                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14398.161185                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9371.494127                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31590.920863                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37103.466442                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29186.007060                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13129.185912                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13398.486996                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6123.536461                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19611.401646                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30148.029688                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 21503.313850                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19611.401646                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30148.029688                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21503.313850                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         7835                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         2458                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              871                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             50                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.995408                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    49.160000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       597529                       # number of writebacks
system.cpu0.dcache.writebacks::total           597529                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       138849                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       138849                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       556206                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       556206                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          431                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          431                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       695055                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       695055                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       695055                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       695055                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63959                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       130326                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       194285                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28874                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53313                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total        82187                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1732                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3337                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5069                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        92833                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       183639                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       276472                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data        92833                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       183639                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       276472                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    779964000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1680980850                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2460944850                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    849834751                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1771488501                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2621323252                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19274250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38952001                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     58226251                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        33000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        33000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1629798751                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3452469351                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5082268102                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1629798751                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3452469351                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5082268102                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27446152500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28893354250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  56339506750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1446442000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13341405748                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14787847748                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28892594500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42234759998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  71127354498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033937                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026616                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014044                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021462                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019462                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008045                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.049643                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.043290                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020256                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000040                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028741                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024050                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.011496                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028741                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024050                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.011496                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     2098287                       # DTB read hits
system.cpu1.dtb.read_misses                      2070                       # DTB read misses
system.cpu1.dtb.write_hits                    1420937                       # DTB write hits
system.cpu1.dtb.write_misses                      371                       # DTB write misses
system.cpu1.dtb.flush_tlb                         277                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                233                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1726                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                    38                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       78                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 2100357                       # DTB read accesses
system.cpu1.dtb.write_accesses                1421308                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          3519224                       # DTB hits
system.cpu1.dtb.misses                           2441                       # DTB misses
system.cpu1.dtb.accesses                      3521665                       # DTB accesses
system.cpu1.itb.inst_hits                     8185092                       # ITB inst hits
system.cpu1.itb.inst_misses                      1172                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         277                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                233                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     867                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8186264                       # ITB inst accesses
system.cpu1.itb.hits                          8185092                       # DTB hits
system.cpu1.itb.misses                           1172                       # DTB misses
system.cpu1.itb.accesses                      8186264                       # DTB accesses
system.cpu1.numCycles                       580203625                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7980801                       # Number of instructions committed
system.cpu1.committedOps                     10142634                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              9072894                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  2143                       # Number of float alu accesses
system.cpu1.num_func_calls                     304668                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1116676                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     9072894                       # number of integer instructions
system.cpu1.num_fp_insts                         2143                       # number of float instructions
system.cpu1.num_int_register_reads           52281658                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           9864872                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1630                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                514                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      3686646                       # number of memory refs
system.cpu1.num_load_insts                    2191239                       # Number of load instructions
system.cpu1.num_store_insts                   1495407                       # Number of store instructions
system.cpu1.num_idle_cycles              544226668.771142                       # Number of idle cycles
system.cpu1.num_busy_cycles              35976956.228858                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.062007                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.937993                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups                4715473                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          3836739                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           223495                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3141743                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2527502                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            80.449037                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 411571                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             21589                       # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    10976033                       # DTB read hits
system.cpu2.dtb.read_misses                     22752                       # DTB read misses
system.cpu2.dtb.write_hits                    3346841                       # DTB write hits
system.cpu2.dtb.write_misses                     6453                       # DTB write misses
system.cpu2.dtb.flush_tlb                         276                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                521                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2303                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      671                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   173                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      460                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                10998785                       # DTB read accesses
system.cpu2.dtb.write_accesses                3353294                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         14322874                       # DTB hits
system.cpu2.dtb.misses                          29205                       # DTB misses
system.cpu2.dtb.accesses                     14352079                       # DTB accesses
system.cpu2.itb.inst_hits                     4041881                       # ITB inst hits
system.cpu2.itb.inst_misses                      4586                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         276                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                521                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    1634                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     1002                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                 4046467                       # ITB inst accesses
system.cpu2.itb.hits                          4041881                       # DTB hits
system.cpu2.itb.misses                           4586                       # DTB misses
system.cpu2.itb.accesses                      4046467                       # DTB accesses
system.cpu2.numCycles                        88343562                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           9345666                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      32463757                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    4715473                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           2939073                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      6849430                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1758819                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     50954                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles              18707448                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                 397                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              820                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        32452                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles       720275                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          489                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  4040467                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               290046                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2014                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          36916106                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.056921                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.443441                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                30071749     81.46%     81.46% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  384570      1.04%     82.50% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  513519      1.39%     83.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  818109      2.22%     86.11% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  634612      1.72%     87.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  341178      0.92%     88.75% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                 1041484      2.82%     91.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  228835      0.62%     92.19% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 2882050      7.81%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            36916106                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.053377                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.367472                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9928442                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             19318553                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  6233841                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               278394                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               1155918                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              607967                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                53425                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              36920328                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               180410                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               1155918                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                10478416                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                6754031                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      11105712                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  5942637                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1478447                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              34829842                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2448                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                324847                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               890462                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents             131                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands           37304234                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            159387361                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       148242103                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups             3218                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             26430435                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                10873798                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            231762                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        208068                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3242623                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6608021                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3899448                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           530191                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          761841                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  32138723                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             510591                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 34782251                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            56051                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        7186073                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     19057300                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        153940                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     36916106                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.942197                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.600639                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           24329752     65.91%     65.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3820331     10.35%     76.25% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            2317804      6.28%     82.53% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2003808      5.43%     87.96% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            2797781      7.58%     95.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             970796      2.63%     98.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             496090      1.34%     99.51% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             144708      0.39%     99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              35036      0.09%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       36916106                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  19314      1.26%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.26% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               1407095     91.52%     92.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               111138      7.23%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            61377      0.18%      0.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             19718575     56.69%     56.87% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               27760      0.08%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                 10      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              9      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc           371      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     56.95% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            11459171     32.95%     89.89% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3514969     10.11%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              34782251                       # Type of FU issued
system.cpu2.iq.rate                          0.393716                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    1537548                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.044205                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         108096303                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         39840742                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     28020326                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               6981                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              3693                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         3127                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              36254698                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   3724                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          204617                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1527306                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         1908                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         9375                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       562929                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      5348773                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked       344308                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               1155918                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                5077664                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                88593                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32732277                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            60627                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6608021                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3899448                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            368370                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 29616                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2740                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          9375                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        107393                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect        89251                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              196644                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             33865771                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             11188559                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           916480                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        82963                       # number of nop insts executed
system.cpu2.iew.exec_refs                    14669578                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 3700003                       # Number of branches executed
system.cpu2.iew.exec_stores                   3481019                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.383342                       # Inst execution rate
system.cpu2.iew.wb_sent                      33465265                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     28023453                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 16087448                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 29114707                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.317210                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.552554                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        7129352                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         356651                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           170839                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     35759991                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.708498                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.752281                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     27025739     75.58%     75.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4219923     11.80%     87.38% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1248297      3.49%     90.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3       635334      1.78%     92.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       557295      1.56%     94.20% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       319233      0.89%     95.09% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       417712      1.17%     96.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       309905      0.87%     97.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1026553      2.87%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     35759991                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            20506693                       # Number of instructions committed
system.cpu2.commit.committedOps              25335895                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8417234                       # Number of memory references committed
system.cpu2.commit.loads                      5080715                       # Number of loads committed
system.cpu2.commit.membars                      94304                       # Number of memory barriers committed
system.cpu2.commit.branches                   3173719                       # Number of branches committed
system.cpu2.commit.fp_insts                      3091                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 22548127                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              294799                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events              1026553                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    66675347                       # The number of ROB reads
system.cpu2.rob.rob_writes                   66130617                       # The number of ROB writes
system.cpu2.timesIdled                         360964                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       51427456                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  3556668435                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   20451214                       # Number of Instructions Simulated
system.cpu2.committedOps                     25280416                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total             20451214                       # Number of Instructions Simulated
system.cpu2.cpi                              4.319722                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        4.319722                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.231496                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.231496                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               156902302                       # number of integer regfile reads
system.cpu2.int_regfile_writes               29839836                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    22382                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   20836                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                9252861                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                241910                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1279629373750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------