path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.824845                       # Number of seconds simulated
sim_ticks                                2824844935500                       # Number of ticks simulated
final_tick                               2824844935500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 301818                       # Simulator instruction rate (inst/s)
host_op_rate                                   366127                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6933711439                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588164                       # Number of bytes of host memory used
host_seconds                                   407.41                       # Real time elapsed on the host
sim_insts                                   122962678                       # Number of instructions simulated
sim_ops                                     149162687                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           540004                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4201700                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           117312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           902784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         1664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           307648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1658880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker         4224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst           418176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data          2992192                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11145864                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       540004                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       117312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       307648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst       418176                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1383140                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8393280                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8410804                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             16891                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             66171                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1833                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             14106                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           26                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4807                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             25920                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker           66                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst              6534                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data             46753                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                183127                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131145                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               135526                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              191162                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1487409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               41529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              319587                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           589                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              108908                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              587246                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1495                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst              148035                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             1059241                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3945655                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         191162                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          41529                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         108908                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst         148035                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             489634                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2971236                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2977439                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2971236                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             191162                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1493613                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              41529                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             319587                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          589                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             108908                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             587246                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst             148035                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            1059241                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6923094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        100046                       # Number of read requests accepted
system.physmem.writeReqs                        68732                       # Number of write requests accepted
system.physmem.readBursts                      100046                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      68732                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6396992                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5952                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4397632                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6402944                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4398848                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       93                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                6841                       # Per bank write bursts
system.physmem.perBankRdBursts::1                6294                       # Per bank write bursts
system.physmem.perBankRdBursts::2                6670                       # Per bank write bursts
system.physmem.perBankRdBursts::3                6264                       # Per bank write bursts
system.physmem.perBankRdBursts::4                6125                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5943                       # Per bank write bursts
system.physmem.perBankRdBursts::6                6707                       # Per bank write bursts
system.physmem.perBankRdBursts::7                6704                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6491                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6555                       # Per bank write bursts
system.physmem.perBankRdBursts::10               6154                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5521                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5628                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6555                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6152                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5349                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4568                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4266                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4764                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4205                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4158                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4117                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4748                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4286                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4452                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4767                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4196                       # Per bank write bursts
system.physmem.perBankWrBursts::11               3943                       # Per bank write bursts
system.physmem.perBankWrBursts::12               3845                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4709                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4129                       # Per bank write bursts
system.physmem.perBankWrBursts::15               3560                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    2823278667500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  100046                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  68732                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     76462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     20947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2008                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     3963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     3852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     3937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     3856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39183                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      275.487635                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     163.171837                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.896605                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16209     41.37%     41.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9498     24.24%     65.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3856      9.84%     75.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2020      5.16%     80.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1646      4.20%     84.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1041      2.66%     87.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          570      1.45%     88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          566      1.44%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3777      9.64%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39183                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3537                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.251343                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      474.824507                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           3535     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3537                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3537                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.426915                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.022626                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.137247                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                 7      0.20%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                2      0.06%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               5      0.14%      0.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3142     88.83%     89.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              84      2.37%     91.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              38      1.07%     92.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              37      1.05%     93.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              22      0.62%     94.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               9      0.25%     94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              25      0.71%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.17%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              52      1.47%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.23%     97.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.14%     97.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.28%     97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              31      0.88%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.03%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.03%     98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              15      0.42%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              29      0.82%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             1      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             3      0.08%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3537                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1310437500                       # Total ticks spent queuing
system.physmem.totMemAccLat                3184556250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    499765000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13110.54                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31860.54                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.26                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.27                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        28.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                      80619                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     48863                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.09                       # Row buffer hit rate for writes
system.physmem.avgGap                     16727764.68                       # Average gap between requests
system.physmem.pageHitRate                      76.76                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  156219840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   85098750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 402051000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                227525760                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            73199813535                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1622867858250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1876720629855                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.445270                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2640465319000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     91913120000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     20214084000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  140003640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   76213500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 377559000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                217734480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            72425693970                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1619952048750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1872971316060                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.534243                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2641598541500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     91913120000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     19069290500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     4956                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                4956                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples         4956                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           4956    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         4956                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples  57378111376                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.254714                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -14615003624    -25.47%    -25.47% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    71993115000    125.47%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  57378111376                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         2714     66.86%     66.86% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1345     33.14%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         4059                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4956                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4956                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4059                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4059                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total         9015                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12035291                       # DTB read hits
system.cpu0.dtb.read_misses                      4159                       # DTB read misses
system.cpu0.dtb.write_hits                    9387286                       # DTB write hits
system.cpu0.dtb.write_misses                      797                       # DTB write misses
system.cpu0.dtb.flush_tlb                         170                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     344                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2853                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   725                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      165                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12039450                       # DTB read accesses
system.cpu0.dtb.write_accesses                9388083                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21422577                       # DTB hits
system.cpu0.dtb.misses                           4956                       # DTB misses
system.cpu0.dtb.accesses                     21427533                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     2296                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                2296                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples         2296                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           2296    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         2296                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples  57378111376                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.254717                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -14615152624    -25.47%    -25.47% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    71993264000    125.47%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  57378111376                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1260     74.03%     74.03% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          442     25.97%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         1702                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2296                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2296                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1702                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1702                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         3998                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    57357196                       # ITB inst hits
system.cpu0.itb.inst_misses                      2296                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         170                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     344                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1708                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                57359492                       # ITB inst accesses
system.cpu0.itb.hits                         57357196                       # DTB hits
system.cpu0.itb.misses                           2296                       # DTB misses
system.cpu0.itb.accesses                     57359492                       # DTB accesses
system.cpu0.numCycles                        69413201                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3088                       # number of quiesce instructions executed
system.cpu0.committedInsts                   55950800                       # Number of instructions committed
system.cpu0.committedOps                     67895777                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             59559088                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4429                       # Number of float alu accesses
system.cpu0.num_func_calls                    5748539                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7418498                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    59559088                       # number of integer instructions
system.cpu0.num_fp_insts                         4429                       # number of float instructions
system.cpu0.num_int_register_reads          109971177                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          41296104                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3323                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1108                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           206667117                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25287808                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     21990141                       # number of memory refs
system.cpu0.num_load_insts                   12179891                       # Number of load instructions
system.cpu0.num_store_insts                   9810250                       # Number of store instructions
system.cpu0.num_idle_cycles              65532353.686303                       # Number of idle cycles
system.cpu0.num_busy_cycles              3880847.313697                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.055909                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.944091                       # Percentage of idle cycles
system.cpu0.Branches                         13556608                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2177      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 46939668     68.04%     68.05% # Class of executed instruction
system.cpu0.op_class::IntMult                   49866      0.07%     68.12% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              3817      0.01%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.12% # Class of executed instruction
system.cpu0.op_class::MemRead                12179891     17.66%     85.78% # Class of executed instruction
system.cpu0.op_class::MemWrite                9810250     14.22%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68985669                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           833415                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.996599                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           46053704                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           833927                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            55.225102                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.718128                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.522887                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.743086                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data    15.012497                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.936949                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022506                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011217                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.029321                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        193158108                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       193158108                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11428921                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      3665380                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4294725                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data      6439389                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25828415                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9038925                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      2620658                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      3331215                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data      3935728                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18926526                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       169435                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        54580                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        74986                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data        86424                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       385425                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210127                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74901                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        77543                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        87725                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       450296                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       211418                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76881                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        80173                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data        91598                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460070                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20467846                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      6286038                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7625940                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     10375117                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        44754941                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20637281                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      6340618                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7700926                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     10461541                       # number of overall hits
system.cpu0.dcache.overall_hits::total       45140366                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       163054                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        56550                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data        94465                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data       206057                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       520126                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       128070                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        30037                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data        97212                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      1098174                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1353493                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        50296                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17954                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32256                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data        38131                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       138637                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3902                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2617                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3585                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         7920                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18024                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data           25                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           27                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       291124                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        86587                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       191677                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      1304231                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1873619                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       341420                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       104541                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data       223933                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      1342362                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2012256                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1025638000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1410367000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3709040500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6145045500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1809360000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6517744997                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  77695281478                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  86022386475                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     36347500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49512000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    113107500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    198967000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       883000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       883000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   2834998000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data   7928111997                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data  81404321978                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  92167431975                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   2834998000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data   7928111997                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data  81404321978                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  92167431975                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11591975                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721930                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4389190                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data      6645446                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26348541                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9166995                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      2650695                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3428427                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data      5033902                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     20280019                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       219731                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72534                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107242                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       124555                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       524062                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       214029                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77518                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        81128                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        95645                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       468320                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211420                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76881                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        80173                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        91623                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460097                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     20758970                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      6372625                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7817617                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     11679348                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     46628560                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     20978701                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      6445159                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7924859                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     11803903                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     47152622                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014066                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015194                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021522                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031007                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.019740                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013971                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011332                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.028355                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.218156                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.066740                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228898                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.247525                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.300778                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.306138                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264543                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018231                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033760                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.044189                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.082806                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038487                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000273                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000059                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.014024                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013587                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024519                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.111670                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.040182                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016275                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016220                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.028257                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113722                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.042675                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18136.834660                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14930.048166                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18000.070369                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11814.532440                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60237.706828                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.712309                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70749.518271                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63555.841423                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13888.995032                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        35320                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32741.612482                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.832651                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62415.570538                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 49192.195412                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27118.527659                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.946703                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60642.600117                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 45803.034989                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       501934                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        34859                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            12379                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            549                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.547217                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    63.495446                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       692123                       # number of writebacks
system.cpu0.dcache.writebacks::total           692123                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15084                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        94480                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       109639                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        44242                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1010049                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1054291                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1596                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2333                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5503                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9432                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data           75                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data        59326                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      1104529                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1163930                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data           75                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data        59326                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      1104529                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1163930                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56475                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        79381                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       111577                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       247433                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30037                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52970                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88125                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       171132                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17691                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22463                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28075                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        68229                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1021                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1252                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2417                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4690                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           25                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           25                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        86512                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       132351                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data       199702                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       418565                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       104203                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       154814                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data       227777                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       486794                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3539                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5604                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8403                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17546                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4346                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6631                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13861                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6423                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9950                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15034                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31407                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    967480000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1154731000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1737821000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3860032000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1779323000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3530687000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6386469938                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11696479938                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    234355500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    312434500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    488593000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1035383000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     16564500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     21022000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     38674500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76261000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       858000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       858000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2746803000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4685418000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8124290938                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15556511938                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2981158500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   4997852500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8612883938                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16591894938                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    629109500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1118645000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1808848000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3556602500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    629109500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1118645000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1808848000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3556602500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015174                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018086                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016790                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009391                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011332                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015450                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017506                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008438                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.243899                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.209461                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.225402                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.130193                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.013171                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.015432                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.025271                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010015                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000273                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000054                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013576                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016930                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017099                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.008977                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016168                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019535                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019297                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.010324                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15575.082678                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15600.312004                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59237.706828                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.464791                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72470.580857                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68347.707840                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15175.116153                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16223.800196                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 16790.734824                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        34320                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        34320                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31750.543277                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.455221                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40682.070976                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37166.298993                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28609.142731                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.949216                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37812.790308                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.016931                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215262.168273                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.612903                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97946.364627                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 112426.633166                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 120317.147798                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 113242.350431                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          1977299                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.446081                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           94017501                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1977811                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            47.536140                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      12783647500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   433.555541                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.959616                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    24.981248                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst    41.949675                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.846788                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021406                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048791                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.081933                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998918                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         98016418                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        98016418                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     56629047                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     17886534                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     10324474                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst      9177446                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       94017501                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     56629047                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     17886534                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     10324474                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst      9177446                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        94017501                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     56629047                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     17886534                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     10324474                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst      9177446                       # number of overall hits
system.cpu0.icache.overall_hits::total       94017501                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       729851                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       205937                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       497244                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst       588038                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2021070                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       729851                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       205937                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       497244                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst       588038                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2021070                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       729851                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       205937                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       497244                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst       588038                       # number of overall misses
system.cpu0.icache.overall_misses::total      2021070                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2906684000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7063507000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8486116487                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18456307487                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2906684000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   7063507000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst   8486116487                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18456307487                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2906684000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   7063507000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst   8486116487                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18456307487                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     57358898                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     18092471                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     10821718                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst      9765484                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     96038571                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     57358898                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     18092471                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     10821718                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst      9765484                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     96038571                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     57358898                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     18092471                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     10821718                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst      9765484                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     96038571                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012724                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011382                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045949                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.060216                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.021044                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012724                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011382                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045949                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.060216                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.021044                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012724                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011382                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045949                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.060216                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.021044                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14114.433055                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.313689                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14431.238265                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9131.948664                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.313689                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14431.238265                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9131.948664                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.313689                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14431.238265                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9131.948664                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         7577                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              331                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.891239                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1977299                       # number of writebacks
system.cpu0.icache.writebacks::total          1977299                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43222                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        43222                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst        43222                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        43222                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst        43222                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        43222                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       205937                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       497244                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       544816                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1247997                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       205937                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       497244                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst       544816                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1247997                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       205937                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       497244                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst       544816                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1247997                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2700747000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6566264000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7404656989                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16671667989                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2700747000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6566264000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7404656989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16671667989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2700747000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6566264000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7404656989                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16671667989                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012995                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.012995                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.012995                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.740437                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.740437                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.740437                       # average overall mshr miss latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     1898                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                1898                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          494                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1404                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         1898                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           1898    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         1898                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1607                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13317.672682                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11568.146418                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7309.305815                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1216     75.67%     75.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          390     24.27%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1607                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1115     69.38%     69.38% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          492     30.62%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1607                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1898                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1898                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1607                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1607                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         3505                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3875521                       # DTB read hits
system.cpu1.dtb.read_misses                      1673                       # DTB read misses
system.cpu1.dtb.write_hits                    2730525                       # DTB write hits
system.cpu1.dtb.write_misses                      225                       # DTB write misses
system.cpu1.dtb.flush_tlb                         151                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     137                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1104                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   238                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       65                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3877194                       # DTB read accesses
system.cpu1.dtb.write_accesses                2730750                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6606046                       # DTB hits
system.cpu1.dtb.misses                           1898                       # DTB misses
system.cpu1.dtb.accesses                      6607944                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                      937                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                 937                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2          756                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples          937                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0            937    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total          937                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          679                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12754.050074                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11061.595827                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6405.303661                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143          193     28.42%     28.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::6144-8191            2      0.29%     28.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287          178     26.22%     54.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335           59      8.69%     63.62% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383          121     17.82%     81.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575          122     17.97%     99.41% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-26623            4      0.59%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          679                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          498     73.34%     73.34% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          181     26.66%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          679                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total          937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          679                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          679                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         1616                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    18092471                       # ITB inst hits
system.cpu1.itb.inst_misses                       937                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         151                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     137                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     710                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                18093408                       # ITB inst accesses
system.cpu1.itb.hits                         18092471                       # DTB hits
system.cpu1.itb.misses                            937                       # DTB misses
system.cpu1.itb.accesses                     18093408                       # DTB accesses
system.cpu1.numCycles                       144009903                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   17421457                       # Number of instructions committed
system.cpu1.committedOps                     20899652                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             18577744                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1420                       # Number of float alu accesses
system.cpu1.num_func_calls                    1993615                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2230860                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    18577744                       # number of integer instructions
system.cpu1.num_fp_insts                         1420                       # number of float instructions
system.cpu1.num_int_register_reads           34369524                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          13035923                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1160                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                260                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            76091406                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            7577340                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      6800165                       # number of memory refs
system.cpu1.num_load_insts                    3918117                       # Number of load instructions
system.cpu1.num_store_insts                   2882048                       # Number of store instructions
system.cpu1.num_idle_cycles              136636530.804008                       # Number of idle cycles
system.cpu1.num_busy_cycles              7373372.195992                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.051200                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.948800                       # Percentage of idle cycles
system.cpu1.Branches                          4337141                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   23      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 14685999     68.30%     68.30% # Class of executed instruction
system.cpu1.op_class::IntMult                   16352      0.08%     68.37% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               955      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::MemRead                 3918117     18.22%     86.60% # Class of executed instruction
system.cpu1.op_class::MemWrite                2882048     13.40%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  21503494                       # Class of executed instruction
system.cpu2.branchPred.lookups                5770264                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          2970192                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           504477                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3340147                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                1745677                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            52.263478                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                1611184                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            331954                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups         670735                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits            637081                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           33654                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted        21230                       # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    12712                       # Table walker walks requested
system.cpu2.dtb.walker.walksShort               12712                       # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8004                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4708                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        12712                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          12712    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        12712                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples         2182                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 12059.578368                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 10400.362655                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev  6359.555797                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::2048-4095           13      0.60%      0.60% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::4096-6143          665     30.48%     31.07% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::6144-8191            1      0.05%     31.12% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::10240-12287          773     35.43%     66.54% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::12288-14335          182      8.34%     74.89% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::14336-16383          171      7.84%     82.72% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::22528-24575          366     16.77%     99.50% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-26623           11      0.50%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total         2182                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000052000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000052000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000052000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K         1365     62.56%     62.56% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M          817     37.44%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total         2182                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12712                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12712                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2182                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2182                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total        14894                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                     4621518                       # DTB read hits
system.cpu2.dtb.read_misses                     11435                       # DTB read misses
system.cpu2.dtb.write_hits                    3537262                       # DTB write hits
system.cpu2.dtb.write_misses                     1277                       # DTB write misses
system.cpu2.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                     162                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    1476                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      227                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   324                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      121                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                 4632953                       # DTB read accesses
system.cpu2.dtb.write_accesses                3538539                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                          8158780                       # DTB hits
system.cpu2.dtb.misses                          12712                       # DTB misses
system.cpu2.dtb.accesses                      8171492                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                     1416                       # Table walker walks requested
system.cpu2.itb.walker.walksShort                1416                       # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1          256                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1160                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples         1416                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0           1416    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total         1416                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples          870                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 12294.252874                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 10677.468386                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev  6303.110021                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::4096-6143          282     32.41%     32.41% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::6144-8191            1      0.11%     32.53% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::10240-12287          251     28.85%     61.38% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::12288-14335           36      4.14%     65.52% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::14336-16383          152     17.47%     82.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::16384-18431            1      0.11%     83.10% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::22528-24575          145     16.67%     99.77% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-26623            2      0.23%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total          870                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000037500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000037500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000037500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K          614     70.57%     70.57% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M          256     29.43%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total          870                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1416                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1416                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          870                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total          870                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total         2286                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    10823576                       # ITB inst hits
system.cpu2.itb.inst_misses                      1416                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                     162                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                     879                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     1762                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                10824992                       # ITB inst accesses
system.cpu2.itb.hits                         10823576                       # DTB hits
system.cpu2.itb.misses                           1416                       # DTB misses
system.cpu2.itb.accesses                     10824992                       # DTB accesses
system.cpu2.numCycles                      1395003781                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                   20361751                       # Number of instructions committed
system.cpu2.committedOps                     24653563                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                      1458677                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                      555                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                  4254696736                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             68.510993                       # CPI: cycles per instruction
system.cpu2.ipc                              0.014596                       # IPC: instructions per cycle
system.cpu2.op_class_0::No_OpClass                 53      0.00%      0.00% # Class of committed instruction
system.cpu2.op_class_0::IntAlu               16404326     66.54%     66.54% # Class of committed instruction
system.cpu2.op_class_0::IntMult                 20837      0.08%     66.62% # Class of committed instruction
system.cpu2.op_class_0::IntDiv                      0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatAdd                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatCmp                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatCvt                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatMult                   0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatDiv                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::FloatSqrt                   0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAdd                     0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdAlu                     0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdCmp                     0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdCvt                     0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMisc                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMult                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdShift                   0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdSqrt                    0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     66.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMisc            1376      0.01%     66.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMult               0      0.00%     66.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     66.63% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     66.63% # Class of committed instruction
system.cpu2.op_class_0::MemRead               4532751     18.39%     85.02% # Class of committed instruction
system.cpu2.op_class_0::MemWrite              3694220     14.98%    100.00% # Class of committed instruction
system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu2.op_class_0::total                24653563                       # Class of committed instruction
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                       42378126                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     1352625655                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               13252062                       # Number of BP lookups
system.cpu3.branchPred.condPredicted          7208218                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect           300007                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups             8273793                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                4241536                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            51.264710                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                3096631                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect             16788                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups        2038250                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits           1978281                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses           59969                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted        18256                       # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                    33989                       # Table walker walks requested
system.cpu3.dtb.walker.walksShort               33989                       # Table walker walks initiated with short descriptors
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11190                       # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         8109                       # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore        14690                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples        19299                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean   517.177056                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev  3689.691447                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-16383        19111     99.03%     99.03% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::16384-32767          146      0.76%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-49151           30      0.16%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::49152-65535            4      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-81919            3      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::81920-98303            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::98304-114687            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::147456-163839            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total        19299                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples         6381                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev  9136.863267                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-32767         6254     98.01%     98.01% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-65535          124      1.94%     99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-98303            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-163839            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::360448-393215            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total         6381                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples  -8047359064                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean     0.134723                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-1  -8096058564    100.61%    100.61% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::2-3     33943000     -0.42%    100.18% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-5      7702500     -0.10%    100.09% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::6-7      2846000     -0.04%    100.05% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-9      1530000     -0.02%    100.03% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::10-11       743500     -0.01%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-13       398000     -0.00%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::14-15       810000     -0.01%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-17       216000     -0.00%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::18-19       164500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-21        85000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::22-23        84500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-25        64500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::26-27        35000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-29        17500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::30-31        59500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total  -8047359064                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K         1874     70.21%     70.21% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::1M          795     29.79%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total         2669                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33989                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33989                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2669                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2669                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total        36658                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                     7187448                       # DTB read hits
system.cpu3.dtb.read_misses                     29423                       # DTB read misses
system.cpu3.dtb.write_hits                    5346423                       # DTB write hits
system.cpu3.dtb.write_misses                     4566                       # DTB write misses
system.cpu3.dtb.flush_tlb                         162                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                    1921                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                      451                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                   735                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                      408                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                 7216871                       # DTB read accesses
system.cpu3.dtb.write_accesses                5350989                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                         12533871                       # DTB hits
system.cpu3.dtb.misses                          33989                       # DTB misses
system.cpu3.dtb.accesses                     12567860                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                     4586                       # Table walker walks requested
system.cpu3.itb.walker.walksShort                4586                       # Table walker walks initiated with short descriptors
system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1476                       # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2630                       # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore          480                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples         4106                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1386.751096                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev  5919.935544                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-8191         3869     94.23%     94.23% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::8192-16383          140      3.41%     97.64% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::16384-24575           51      1.24%     98.88% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::24576-32767           18      0.44%     99.32% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-40959            9      0.22%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::40960-49151            8      0.19%     99.73% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::49152-57343            3      0.07%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::57344-65535            2      0.05%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-73727            1      0.02%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::73728-81919            1      0.02%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::81920-90111            2      0.05%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::106496-114687            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total         4106                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples         1793                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 12167.875070                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean  9929.586957                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev  7490.636626                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-4095           25      1.39%      1.39% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::4096-8191          685     38.20%     39.60% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::8192-12287          343     19.13%     58.73% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::12288-16383          337     18.80%     77.52% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::16384-20479           34      1.90%     79.42% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::20480-24575          327     18.24%     97.66% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::24576-28671           25      1.39%     99.05% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::28672-32767            2      0.11%     99.16% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-36863            8      0.45%     99.61% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::36864-40959            3      0.17%     99.78% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::40960-45055            1      0.06%     99.83% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::45056-49151            1      0.06%     99.89% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::49152-53247            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total         1793                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples  -8048628564                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     0.273756                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev     0.444979                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0    -5842963052     72.60%     72.60% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1    -2207299512     27.42%    100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2        1197000     -0.01%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3         240000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4         159500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5          37500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total  -8048628564                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K          959     73.04%     73.04% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::1M          354     26.96%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total         1313                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4586                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4586                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1313                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1313                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total         5899                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                     9766986                       # ITB inst hits
system.cpu3.itb.inst_misses                      4586                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                         162                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                    1310                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                      793                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                 9771572                       # ITB inst accesses
system.cpu3.itb.hits                          9766986                       # DTB hits
system.cpu3.itb.misses                           4586                       # DTB misses
system.cpu3.itb.accesses                      9771572                       # DTB accesses
system.cpu3.numCycles                        57688006                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles          20811649                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                      52033022                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   13252062                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches           9316448                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                     33930227                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                1581201                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                     68181                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                 837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles              231                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles       120341                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        80383                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                  9765486                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes               207700                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                   2399                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples          55802907                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.126480                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.271736                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                41696580     74.72%     74.72% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                 1836235      3.29%     78.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                 1165184      2.09%     80.10% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 3688211      6.61%     86.71% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                  906128      1.62%     88.33% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                  549241      0.98%     89.32% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 2914438      5.22%     94.54% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                  602830      1.08%     95.62% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                 2444060      4.38%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total            55802907                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.229720                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.901973                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                14568551                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles             31866325                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                  7772560                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles               890718                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                704494                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved              971899                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred                87220                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts              44590073                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts               289455                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles                704494                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                15048291                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                3770246                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles      21829644                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                  8174749                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles              6275200                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts              42740400                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                 1148                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents                970300                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                 89126                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents               4852570                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.RenamedOperands           44469975                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            196242063                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups        47658053                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups             4195                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps             37088424                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                 7381551                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts            715073                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts        665430                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                  5054867                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads             7671703                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores            5900822                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          1096118                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         1546348                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                  41143800                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded             502182                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                 39136171                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued            53747                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined        5932287                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     13678209                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved         53132                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples     55802907                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.701329                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.406589                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0           40242389     72.12%     72.12% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1            5178782      9.28%     81.40% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2            3976738      7.13%     88.52% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3            3203416      5.74%     94.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4            1255770      2.25%     96.51% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5             764374      1.37%     97.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6             832269      1.49%     99.37% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7             238251      0.43%     99.80% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8             110918      0.20%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total       55802907                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                  55578      9.37%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                279414     47.11%     56.48% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite               258161     43.52%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu             26095745     66.68%     66.68% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult               29921      0.08%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc          2385      0.01%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead             7397516     18.90%     85.66% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite            5610518     14.34%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total              39136171                       # Type of FU issued
system.cpu3.iq.rate                          0.678411                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                     593153                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.015156                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads         134713370                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes         47601786                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses     37987762                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads               8779                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes              5136                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses         3873                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses              39724534                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                   4706                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads          167566                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      1160486                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses         1105                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation        29281                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores       565962                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads       108568                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked        42515                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                704494                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                3163832                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles               480485                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts           41688387                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts            67679                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts              7671703                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts             5900822                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts            259528                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                 22774                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents               451647                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents         29281                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect        127480                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect       130164                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts              257644                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts             38819012                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts              7269209                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts           283254                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        42405                       # number of nop insts executed
system.cpu3.iew.exec_refs                    12824644                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                 7229166                       # Number of branches executed
system.cpu3.iew.exec_stores                   5555435                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.672913                       # Inst execution rate
system.cpu3.iew.wb_sent                      38534594                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                     37991635                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                 19895864                       # num instructions producing a value
system.cpu3.iew.wb_consumers                 34654258                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      0.658571                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.574125                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts        5941608                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls         449050                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts           213879                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples     54520380                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.655522                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.547792                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0     40723432     74.69%     74.69% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1      6130706     11.24%     85.94% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2      3105147      5.70%     91.63% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      1318175      2.42%     94.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4       725189      1.33%     95.38% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5       499185      0.92%     96.30% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6       937323      1.72%     98.02% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7       226618      0.42%     98.43% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8       854605      1.57%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total     54520380                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts            29254285                       # Number of instructions committed
system.cpu3.commit.committedOps              35739310                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      11846077                       # Number of memory references committed
system.cpu3.commit.loads                      6511217                       # Number of loads committed
system.cpu3.commit.membars                     174051                       # Number of memory barriers committed
system.cpu3.commit.branches                   6823843                       # Number of branches committed
system.cpu3.commit.fp_insts                      3728                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                 31222167                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             1239499                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu        23861884     66.77%     66.77% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult          28964      0.08%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc         2385      0.01%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead        6511217     18.22%     85.07% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite       5334860     14.93%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total         35739310                       # Class of committed instruction
system.cpu3.commit.bw_lim_events               854605                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                    89694977                       # The number of ROB reads
system.cpu3.rob.rob_writes                   84644260                       # The number of ROB writes
system.cpu3.timesIdled                         227108                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                        1885099                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                  5160958859                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                   29228670                       # Number of Instructions Simulated
system.cpu3.committedOps                     35713695                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.973679                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.973679                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.506668                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.506668                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                42269766                       # number of integer regfile reads
system.cpu3.int_regfile_writes               24060528                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                    14520                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                   12259                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                137213612                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                14769581                       # number of cc regfile writes
system.cpu3.misc_regfile_reads               75722157                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                336126                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59010                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105436                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67865                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159093                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480317                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             27737500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               101500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               203000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                19500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             3864000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            22351500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            78673017                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            48334000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            15512000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36409                       # number of replacements
system.iocache.tags.tagsinuse                1.005569                       # Cycle average of tags in use
system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         249219554509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.005569                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062848                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062848                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
system.iocache.tags.data_accesses              328227                       # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
system.iocache.demand_hits::total                  29                       # number of demand (read+write) hits
system.iocache.overall_hits::realview.ide           29                       # number of overall hits
system.iocache.overall_hits::total                 29                       # number of overall hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
system.iocache.overall_misses::total            36444                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     17512919                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     17512919                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   1907451098                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   1907451098                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   1924964017                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1924964017                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   1924964017                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1924964017                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36473                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36473                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36473                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36473                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide     0.999205                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 70333.008032                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52699.298190                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 52819.778756                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 52819.778756                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 52819.778756                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 52819.778756                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36160                       # number of writebacks
system.iocache.writebacks::total                36160                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          148                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          148                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        15187                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        15187                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        15335                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        15335                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        15335                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        15335                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     10112919                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     10112919                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1147424968                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1147424968                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1157537887                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1157537887                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1157537887                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1157537887                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.594378                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.419252                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.419252                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.420448                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.420448                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.420448                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.420448                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75553.102522                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75483.396609                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75483.396609                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75483.396609                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75483.396609                       # average overall mshr miss latency
system.l2c.tags.replacements                   103654                       # number of replacements
system.l2c.tags.tagsinuse                65094.562604                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5149240                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168905                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.486013                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              80133862000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   49018.245060                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971846                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4276.002230                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2253.870491                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.966972                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      903.622290                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      882.214681                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    22.046662                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1923.753709                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data      720.306234                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    49.949258                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     3365.651463                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     1676.961612                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.747959                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.065247                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.034391                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.013788                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013462                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000336                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.029354                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.010991                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.000762                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.051356                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.025588                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993264                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           64                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65187                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           64                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2167                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7607                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55305                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000977                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994675                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45502395                       # Number of tag accesses
system.l2c.tags.data_accesses                45502395                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         4144                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         2033                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         1722                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker          868                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        13393                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         1189                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker        21091                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker         4127                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  48567                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       692123                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          692123                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1939703                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1939703                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               2                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              11                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              42                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  67                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data            17                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                19                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            66572                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            17866                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            28004                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data            44210                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156652                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        721971                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        204101                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        492422                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst        538161                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1956655                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       211223                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        72596                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       101112                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data       137861                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           522792                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4144                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          2033                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              721971                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              277795                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          1722                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker           868                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              204101                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               90462                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         13393                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          1189                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              492422                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              129116                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker         21091                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker          4127                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst              538161                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data              182071                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2684666                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4144                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         2033                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             721971                       # number of overall hits
system.l2c.overall_hits::cpu0.data             277795                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         1722                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker          868                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             204101                       # number of overall hits
system.l2c.overall_hits::cpu1.data              90462                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        13393                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         1189                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             492422                       # number of overall hits
system.l2c.overall_hits::cpu2.data             129116                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker        21091                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker         4127                       # number of overall hits
system.l2c.overall_hits::cpu3.inst             538161                       # number of overall hits
system.l2c.overall_hits::cpu3.data             182071                       # number of overall hits
system.l2c.overall_hits::total                2684666                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           26                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker           66                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   97                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1115                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           373                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           575                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data           724                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2787                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            8                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               8                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          60371                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          11796                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          24381                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data          43155                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139703                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         7874                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1833                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         4814                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst         6539                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           21060                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6029                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2591                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data         1983                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data         4202                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          14805                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7874                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             66400                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1833                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             14387                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           26                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4814                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             26364                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker           66                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst              6539                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data             47357                       # number of demand (read+write) misses
system.l2c.demand_misses::total                175665                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7874                       # number of overall misses
system.l2c.overall_misses::cpu0.data            66400                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1833                       # number of overall misses
system.l2c.overall_misses::cpu1.data            14387                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           26                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4814                       # number of overall misses
system.l2c.overall_misses::cpu2.data            26364                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker           66                       # number of overall misses
system.l2c.overall_misses::cpu3.inst             6539                       # number of overall misses
system.l2c.overall_misses::cpu3.data            47357                       # number of overall misses
system.l2c.overall_misses::total               175665                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3451000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker      9023500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       12607000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       157000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       156000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data      1012500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1325500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data       317500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       317500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1517126000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   3110079500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data   5724450000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10351655500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    241264500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    638292500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst    866843998                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1746400998                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    341211500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data    263338500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data    578680000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1183230000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    241264500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1858337500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      3451000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    638292500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3373418000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker      9023500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst    866843998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data   6303130000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     13293893498                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    241264500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1858337500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      3451000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    638292500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3373418000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker      9023500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst    866843998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data   6303130000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    13293893498                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4147                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         2034                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         1723                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker          868                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        13419                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         1189                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker        21157                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker         4127                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              48664                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       692123                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       692123                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1939703                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1939703                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1127                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          375                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          586                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data          766                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2854                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data           25                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            27                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       126943                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        29662                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        52385                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data        87365                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296355                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       729845                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       205934                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       497236                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst       544700                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1977715                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       217252                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        75187                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       103095                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data       142063                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       537597                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4147                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         2034                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          729845                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          344195                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         1723                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker          868                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          205934                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          104849                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        13419                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         1189                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          497236                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          155480                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker        21157                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker         4127                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst          544700                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data          229428                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2860331                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4147                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         2034                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         729845                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         344195                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         1723                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker          868                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         205934                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         104849                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        13419                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         1189                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         497236                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         155480                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker        21157                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker         4127                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst         544700                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data         229428                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2860331                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001993                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989352                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.994667                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.981229                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.945170                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.976524                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.320000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.296296                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.475576                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.397681                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.465419                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.493962                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.471404                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010789                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008901                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.009682                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.012005                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010649                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.027751                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034461                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019235                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.029578                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027539                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010789                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.192914                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.008901                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.137216                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.009682                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.169565                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.012005                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.206413                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061414                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010789                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.192914                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.008901                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.137216                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.009682                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.169565                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.012005                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.206413                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061414                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 129969.072165                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   420.911528                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   271.304348                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  1398.480663                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   475.601005                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 39687.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 39687.500000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128613.597830                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.605348                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132648.592284                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74097.589171                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131622.749591                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.880764                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132565.223735                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82925.023647                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131691.045928                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132798.033283                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137715.373632                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79920.972644                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 129167.825120                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 132590.880764                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 127955.469580                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 132565.223735                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 133098.169225                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 75677.531085                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 129167.825120                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 132590.880764                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 127955.469580                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 132565.223735                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 133098.169225                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 75677.531085                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               94985                       # number of writebacks
system.l2c.writebacks::total                    94985                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data           18                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data           42                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           60                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data             42                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data            42                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           26                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           66                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              93                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          373                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          575                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data          724                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1672                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            8                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            8                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        11796                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        24381                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data        43155                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         79332                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1833                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4811                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         6534                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        13178                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2591                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1965                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4160                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         8716                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1833                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        14387                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           26                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4811                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        26346                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker           66                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst         6534                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data        47315                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           101319                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1833                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        14387                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           26                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4811                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        26346                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker           66                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst         6534                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data        47315                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          101319                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3539                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         5604                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         8403                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        17546                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4346                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6631                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        13861                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6423                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data         9950                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        15034                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        31407                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     11677000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     25361500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39113500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     49225500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    113700500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       550500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       550500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399166000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2866269500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5292900000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9558335500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222934500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    590022000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    800986002                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1613942502                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    315301500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    241631500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    531826001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1088759001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    222934500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1714467500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    590022000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   3107901000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst    800986002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data   5824726001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  12272714003                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    222934500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1714467500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    590022000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   3107901000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst    800986002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data   5824726001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  12272714003                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    584851500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1048585500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1703789000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3337226000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    584851500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1048585500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1703789000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3337226000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001911                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.994667                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.981229                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.945170                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.585844                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.320000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.296296                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.397681                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.465419                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.493962                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.267692                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006663                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034461                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019060                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029283                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016213                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.137216                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.206230                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.035422                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.137216                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.206230                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.035422                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 125559.139785                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67993.297587                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68023.478261                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68002.691388                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68812.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68812.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118613.597830                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.605348                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122648.592284                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120485.245550                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122472.492184                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121691.045928                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122967.684478                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127842.788702                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124914.984052                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119167.825120                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117964.814393                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123105.273190                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 121129.442681                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119167.825120                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117964.814393                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123105.273190                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 121129.442681                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165258.971461                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 187113.758030                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.609663                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.677761                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91055.815040                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 105385.477387                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 113329.054144                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 106257.394848                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
system.membus.trans_dist::ReadResp              76256                       # Transaction distribution
system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131145                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8918                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4561                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1773                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137930                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137930                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36142                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        21008                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       485390                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       592842                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        93962                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        93962                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 686804                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17249660                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17412785                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2320704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2320704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19733489                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              305                       # Total snoops (count)
system.membus.snoop_fanout::samples            422579                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  422579    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              422579                       # Request fanout histogram
system.membus.reqLayer0.occupancy            54358000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              678498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           480577516                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          576478500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy             796581                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5652843                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2841066                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        44935                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            620                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             111947                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2627538                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       760857                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1977299                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          146342                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2855                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            27                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2881                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296355                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296355                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1977848                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       537745                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        15186                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5950911                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2624542                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        25489                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       101525                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8702467                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    253157304                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97861113                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41336                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       179388                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              351239141                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          193521                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4203916                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021594                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.145353                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4113137     97.84%     97.84% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  90779      2.16%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4203916                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3441095952                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           260919                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1872616750                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         760133706                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11021467                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          48273206                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------