path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.403852                       # Number of seconds simulated
sim_ticks                                2403852457500                       # Number of ticks simulated
final_tick                               2403852457500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 165592                       # Simulator instruction rate (inst/s)
host_op_rate                                   212680                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6597855857                       # Simulator tick rate (ticks/s)
host_mem_usage                                 469068                       # Number of bytes of host memory used
host_seconds                                   364.34                       # Real time elapsed on the host
sim_insts                                    60331653                       # Number of instructions simulated
sim_ops                                      77487544                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           512456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          7048216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            63936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           680960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker          576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           186944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1348288                       # Number of bytes read from this memory
system.physmem.bytes_read::total            124660704                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       512456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        63936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       186944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          763336                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3743808                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1298564                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data        159248                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data       1558004                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6759624                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             14219                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            110164                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               999                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10640                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker            9                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              2921                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             21067                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14512407                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58497                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           324641                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data            39812                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           389501                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812451                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47764609                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              213181                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2932050                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               26597                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              283279                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           240                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               77769                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              560886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51858717                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         213181                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          26597                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          77769                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             317547                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1557420                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             540201                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data              66247                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             648128                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2811996                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1557420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47764609                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             213181                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3472251                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              26597                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             349526                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          240                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              77769                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1209014                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54670713                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      13446501                       # Number of read requests accepted
system.physmem.writeReqs                       446412                       # Number of write requests accepted
system.physmem.readBursts                    13446501                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     446412                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                860576000                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                        64                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   2816640                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 109567680                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                2811588                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        1                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  402376                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           2365                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              835689                       # Per bank write bursts
system.physmem.perBankRdBursts::1              835334                       # Per bank write bursts
system.physmem.perBankRdBursts::2              835514                       # Per bank write bursts
system.physmem.perBankRdBursts::3              835992                       # Per bank write bursts
system.physmem.perBankRdBursts::4              837083                       # Per bank write bursts
system.physmem.perBankRdBursts::5              837766                       # Per bank write bursts
system.physmem.perBankRdBursts::6              837910                       # Per bank write bursts
system.physmem.perBankRdBursts::7              839140                       # Per bank write bursts
system.physmem.perBankRdBursts::8              840643                       # Per bank write bursts
system.physmem.perBankRdBursts::9              843328                       # Per bank write bursts
system.physmem.perBankRdBursts::10             843395                       # Per bank write bursts
system.physmem.perBankRdBursts::11             843892                       # Per bank write bursts
system.physmem.perBankRdBursts::12             845429                       # Per bank write bursts
system.physmem.perBankRdBursts::13             846004                       # Per bank write bursts
system.physmem.perBankRdBursts::14             844795                       # Per bank write bursts
system.physmem.perBankRdBursts::15             844586                       # Per bank write bursts
system.physmem.perBankWrBursts::0                2674                       # Per bank write bursts
system.physmem.perBankWrBursts::1                2534                       # Per bank write bursts
system.physmem.perBankWrBursts::2                2538                       # Per bank write bursts
system.physmem.perBankWrBursts::3                3024                       # Per bank write bursts
system.physmem.perBankWrBursts::4                3410                       # Per bank write bursts
system.physmem.perBankWrBursts::5                3131                       # Per bank write bursts
system.physmem.perBankWrBursts::6                2493                       # Per bank write bursts
system.physmem.perBankWrBursts::7                2267                       # Per bank write bursts
system.physmem.perBankWrBursts::8                2164                       # Per bank write bursts
system.physmem.perBankWrBursts::9                2378                       # Per bank write bursts
system.physmem.perBankWrBursts::10               2328                       # Per bank write bursts
system.physmem.perBankWrBursts::11               2803                       # Per bank write bursts
system.physmem.perBankWrBursts::12               3718                       # Per bank write bursts
system.physmem.perBankWrBursts::13               3446                       # Per bank write bursts
system.physmem.perBankWrBursts::14               2595                       # Per bank write bursts
system.physmem.perBankWrBursts::15               2507                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2402816386500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                13410864                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   35637                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 429313                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  17099                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    877452                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    853858                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    853065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    937219                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    861122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    912169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2402802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2330624                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3052022                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     86874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    80661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    76244                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    73288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    16615                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    16291                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    16173                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     2396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     2417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     2368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     2356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     2413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     2343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     2346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     2344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     2313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       866032                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      996.952353                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     964.296727                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     145.584191                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           8288      0.96%      0.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8846      1.02%      1.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6189      0.71%      2.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          800      0.09%      2.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          916      0.11%      2.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          687      0.08%      2.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7828      0.90%      3.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          243      0.03%      3.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       832235     96.10%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         866032                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          2414                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      5570.207125                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    258157.496677                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287         2413     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.04%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            2414                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          2414                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.231152                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.108696                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.979905                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   1      0.04%      0.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   2      0.08%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   1      0.04%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   1      0.04%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7                   2      0.08%      0.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9                   1      0.04%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12                  1      0.04%      0.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14                  1      0.04%      0.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                  7      0.29%      0.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                485     20.09%     20.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 15      0.62%     21.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                872     36.12%     57.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                845     35.00%     92.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 52      2.15%     94.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 24      0.99%     95.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 26      1.08%     96.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 34      1.41%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 13      0.54%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  5      0.21%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  6      0.25%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.04%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  6      0.25%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  7      0.29%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  2      0.08%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  4      0.17%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            2414                       # Writes before turning the bus around for reads
system.physmem.totQLat                   345783645500                       # Total ticks spent queuing
system.physmem.totMemAccLat              597905520500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  67232500000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25715.51                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44465.51                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         358.00                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       45.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         7.51                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         4.43                       # Average write queue length when enqueuing
system.physmem.readRowHits                   12586631                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     37847                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  85.95                       # Row buffer hit rate for writes
system.physmem.avgGap                       172952.67                       # Average gap between requests
system.physmem.pageHitRate                      93.58                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2167477603250                       # Time in different power states
system.physmem.memoryStateTime::REF       80269800000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      156101819250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     55667977                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            13781620                       # Transaction distribution
system.membus.trans_dist::ReadResp           13781620                       # Transaction distribution
system.membus.trans_dist::WriteReq             432153                       # Transaction distribution
system.membus.trans_dist::WriteResp            432153                       # Transaction distribution
system.membus.trans_dist::Writeback             17099                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2365                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2365                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28041                       # Transaction distribution
system.membus.trans_dist::ReadExResp            28041                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       731786                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          214                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951729                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1683729                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26821728                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     26821728                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               28505457                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       735662                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          428                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5092356                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      5828446                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107286912                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    107286912                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           113115358                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              133817603                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           416874000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              199500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         14576510500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1596663785                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33229062000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    63248                       # number of replacements
system.l2c.tags.tagsinuse                50398.234461                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1749256                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   128641                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.597966                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2375562300000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36845.662788                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000124                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5231.089770                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3832.891832                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993317                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      496.025776                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      690.296020                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.797358                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1694.464698                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     1598.012760                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.562220                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.079820                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.058485                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.007569                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.010533                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000134                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.025855                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.024384                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.769016                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65389                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2635                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6488                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55889                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997757                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17683113                       # Number of tag accesses
system.l2c.tags.data_accesses                17683113                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         8690                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3137                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             468117                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             177120                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         2623                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1184                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             129717                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              64377                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        18993                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         4195                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             281260                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             131724                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1291137                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          597632                       # number of Writeback hits
system.l2c.Writeback_hits::total               597632                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              12                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  30                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             4                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 4                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            62001                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            18409                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            33201                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113611                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          8690                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3137                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              468117                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              239121                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          2623                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1184                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              129717                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               82786                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         18993                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          4195                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              281260                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              164925                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1404748                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         8690                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3137                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             468117                       # number of overall hits
system.l2c.overall_hits::cpu0.data             239121                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         2623                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1184                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             129717                       # number of overall hits
system.l2c.overall_hits::cpu1.data              82786                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        18993                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         4195                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             281260                       # number of overall hits
system.l2c.overall_hits::cpu2.data             164925                       # number of overall hits
system.l2c.overall_hits::total                1404748                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7593                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6464                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              999                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1119                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker            9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             2922                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data             2560                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21670                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1416                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           469                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1019                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         104452                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9794                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          19124                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133370                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7593                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            110916                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               999                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10913                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker            9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              2922                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             21684                       # number of demand (read+write) misses
system.l2c.demand_misses::total                155040                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7593                       # number of overall misses
system.l2c.overall_misses::cpu0.data           110916                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              999                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10913                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker            9                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             2922                       # number of overall misses
system.l2c.overall_misses::cpu2.data            21684                       # number of overall misses
system.l2c.overall_misses::total               155040                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     70879750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     85596750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       673000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    220789250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    196778249                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      574791499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        93996                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       139494                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       233490                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    710505727                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1408534646                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2119040373                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     70879750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    796102477                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker       673000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    220789250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   1605312895                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2693831872                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     70879750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    796102477                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker       673000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    220789250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   1605312895                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2693831872                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8691                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3139                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         475710                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         183584                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         2624                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1184                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         130716                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          65496                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        19002                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         4195                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         284182                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         134284                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1312807                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       597632                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           597632                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1430                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          473                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1031                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2934                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       166453                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28203                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        52325                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246981                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8691                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3139                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          475710                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          350037                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         2624                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1184                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          130716                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           93699                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        19002                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         4195                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          284182                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          186609                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1559788                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8691                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3139                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         475710                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         350037                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         2624                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1184                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         130716                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          93699                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        19002                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         4195                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         284182                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         186609                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1559788                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015961                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.035210                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.007643                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.017085                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.010282                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.019064                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016507                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990210                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991543                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.988361                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.989775                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.627516                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.347268                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.365485                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.540001                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015961                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.316869                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007643                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.116469                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.010282                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.116200                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.099398                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015961                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.316869                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007643                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.116469                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000474                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.010282                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.116200                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.099398                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70950.700701                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76493.967828                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75561.002738                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 76866.503516                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 26524.757683                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   200.417910                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   136.893032                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total    80.402893                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72544.999694                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73652.721502                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 15888.433478                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 70950.700701                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72949.920004                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 75561.002738                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74032.138674                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 17375.076574                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 70950.700701                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72949.920004                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74777.777778                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 75561.002738                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74032.138674                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 17375.076574                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58497                       # number of writebacks
system.l2c.writebacks::total                    58497                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data            13                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          999                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1119                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker            9                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         2921                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data         2547                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7596                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          469                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1019                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1488                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9794                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        19124                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         28918                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          999                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10913                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker            9                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         2921                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        21671                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            36514                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          999                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10913                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker            9                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         2921                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        21671                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           36514                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     58206250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     71681250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    184124500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    164011999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    478648999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4690469                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10191019                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     14881488                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    586577273                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1169906854                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1756484127                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     58206250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    658258523                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    184124500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1333918853                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2235133126                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     58206250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    658258523                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       562500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    184124500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1333918853                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2235133126                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25072597000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26177785500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  51250382500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    933416100                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8516272500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   9449688600                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26006013100                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34694058000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60700071100                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017085                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018967                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005786                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991543                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.988361                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.507157                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347268                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.365485                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.117086                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.116469                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.116131                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.023410                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007643                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.116469                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000474                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010279                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.116131                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.023410                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61213.045024                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61213.045024                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58808825                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            1019736                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1019735                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            432153                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           432153                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           265208                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1504                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1508                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            80528                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           80528                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       830481                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2419466                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15414                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52803                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               3318164                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26553408                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37366366                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21516                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        86504                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           64027794                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             141267007                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          100732                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2176624753                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1870991697                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1845922726                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          10050964                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          31304739                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48758959                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             13773981                       # Transaction distribution
system.iobus.trans_dist::ReadResp            13773981                       # Transaction distribution
system.iobus.trans_dist::WriteReq                2776                       # Transaction distribution
system.iobus.trans_dist::WriteResp               2776                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11410                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3028                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          254                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       716788                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       731786                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26821728                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     26821728                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                27553514                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15374                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          508                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       713112                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       735662                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107286912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107286912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            108022574                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               117209343                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              7968000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              1514000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               127000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy            358898000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         13410864000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           729010000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         33767373000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7995700                       # DTB read hits
system.cpu0.dtb.read_misses                      6195                       # DTB read misses
system.cpu0.dtb.write_hits                    6594454                       # DTB write hits
system.cpu0.dtb.write_misses                     1984                       # DTB write misses
system.cpu0.dtb.flush_tlb                         556                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                675                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5669                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   121                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      209                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8001895                       # DTB read accesses
system.cpu0.dtb.write_accesses                6596438                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14590154                       # DTB hits
system.cpu0.dtb.misses                           8179                       # DTB misses
system.cpu0.dtb.accesses                     14598333                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    32327896                       # ITB inst hits
system.cpu0.itb.inst_misses                      3449                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         556                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                675                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2626                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                32331345                       # ITB inst accesses
system.cpu0.itb.hits                         32327896                       # DTB hits
system.cpu0.itb.misses                           3449                       # DTB misses
system.cpu0.itb.accesses                     32331345                       # DTB accesses
system.cpu0.numCycles                       113683212                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   31852389                       # Number of instructions committed
system.cpu0.committedOps                     42022034                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             37405417                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4937                       # Number of float alu accesses
system.cpu0.num_func_calls                    1199046                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4246321                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    37405417                       # number of integer instructions
system.cpu0.num_fp_insts                         4937                       # number of float instructions
system.cpu0.num_int_register_reads          193890675                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          39514617                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3572                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1366                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     15257672                       # number of memory refs
system.cpu0.num_load_insts                    8364380                       # Number of load instructions
system.cpu0.num_store_insts                   6893292                       # Number of store instructions
system.cpu0.num_idle_cycles              110986808.765580                       # Number of idle cycles
system.cpu0.num_busy_cycles              2696403.234420                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.023719                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.976281                       # Percentage of idle cycles
system.cpu0.Branches                          5614656                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                14792      0.04%      0.04% # Class of executed instruction
system.cpu0.op_class::IntAlu                 26773719     63.60%     63.63% # Class of executed instruction
system.cpu0.op_class::IntMult                   49650      0.12%     63.75% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.75% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              1431      0.00%     63.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.76% # Class of executed instruction
system.cpu0.op_class::MemRead                 8364380     19.87%     83.63% # Class of executed instruction
system.cpu0.op_class::MemWrite                6893292     16.37%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  42097264                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           891512                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.602542                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           43658005                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           892024                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            48.942635                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       8184230000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   494.829489                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.587272                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst     9.185782                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.966464                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014819                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.017941                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999224                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         45465874                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        45465874                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     31854091                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      8059411                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3744503                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       43658005                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     31854091                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      8059411                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3744503                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        43658005                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     31854091                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      8059411                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3744503                       # number of overall hits
system.cpu0.icache.overall_hits::total       43658005                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       476451                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       130983                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       308401                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       915835                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       476451                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       130983                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       308401                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        915835                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       476451                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       130983                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       308401                       # number of overall misses
system.cpu0.icache.overall_misses::total       915835                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1767573750                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4161599099                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5929172849                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1767573750                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4161599099                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5929172849                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1767573750                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4161599099                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5929172849                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     32330542                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      8190394                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      4052904                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     44573840                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     32330542                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      8190394                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      4052904                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     44573840                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     32330542                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      8190394                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      4052904                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     44573840                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014737                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015992                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076094                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.020546                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014737                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015992                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076094                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.020546                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014737                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015992                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076094                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.020546                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13494.680607                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13494.116747                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6474.062303                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13494.680607                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13494.116747                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6474.062303                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13494.680607                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13494.116747                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6474.062303                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2820                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              202                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.960396                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23800                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        23800                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        23800                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        23800                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        23800                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        23800                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130983                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       284601                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       415584                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       130983                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       284601                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       415584                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       130983                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       284601                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       415584                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1505220250                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3386666286                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4891886536                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1505220250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3386666286                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4891886536                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1505220250                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3386666286                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4891886536                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009323                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009323                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015992                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070222                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009323                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.113748                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.113748                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11491.722208                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11899.699179                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.113748                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           629833                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997118                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           23224733                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           630345                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            36.844479                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.042290                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.061376                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.893452                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970786                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015745                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013464                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         98835293                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        98835293                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6864775                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1819119                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4641948                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13325842                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5963046                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1314313                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2132881                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9410240                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131790                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33007                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73476                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       238273                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138256                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34751                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74378                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247385                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12827821                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      3133432                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6774829                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        22736082                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12827821                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      3133432                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6774829                       # number of overall hits
system.cpu0.dcache.overall_hits::total       22736082                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       177118                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        63752                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       270474                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       511344                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       167883                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        28676                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       609650                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       806209                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6466                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1744                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3730                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11940                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       345001                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        92428                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       880124                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1317553                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       345001                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data        92428                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data       880124                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1317553                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    907525000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3898427279                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4805952279                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    994225242                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22938892543                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  23933117785                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     22894750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49919498                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     72814248                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        52000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        52000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   1901750242                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  26837319822                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  28739070064                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   1901750242                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  26837319822                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  28739070064                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7041893                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1882871                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4912422                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13837186                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      6130929                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1342989                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2742531                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10216449                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138256                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34751                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77206                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       250213                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138256                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34751                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74382                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247389                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13172822                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      3225860                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7654953                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24053635                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13172822                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      3225860                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7654953                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24053635                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025152                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033859                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055059                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036954                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027383                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021352                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.222295                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.078913                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046768                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050186                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048312                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047719                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000054                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000016                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026190                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028652                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114974                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.054776                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026190                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028652                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.114974                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.054776                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9398.667588                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6098.345729                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         8069                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3116                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              905                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             48                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.916022                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    64.916667                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       597632                       # number of writebacks
system.cpu0.dcache.writebacks::total           597632                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       139480                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       139480                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       556328                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       556328                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          406                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          406                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       695808                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       695808                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       695808                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       695808                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63752                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       130994                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       194746                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28676                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53322                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total        81998                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1744                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3324                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5068                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        92428                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       184316                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       276744                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data        92428                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       184316                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       276744                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    779830000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1694363864                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2474193864                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    934250758                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1848694495                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2782945253                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19406250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38393502                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57799752                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        44000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        44000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1714080758                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3543058359                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5257139117                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1714080758                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3543058359                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5257139117                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27392049000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28579464500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55971513500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1440396400                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13339396963                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14779793363                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28832445400                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41918861463                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70751306863                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033859                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026666                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014074                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021352                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019443                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008026                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050186                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.043054                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020255                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000054                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028652                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024078                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.011505                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028652                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024078                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.011505                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     2096038                       # DTB read hits
system.cpu1.dtb.read_misses                      2089                       # DTB read misses
system.cpu1.dtb.write_hits                    1418402                       # DTB write hits
system.cpu1.dtb.write_misses                      376                       # DTB write misses
system.cpu1.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1770                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                    37                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       79                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 2098127                       # DTB read accesses
system.cpu1.dtb.write_accesses                1418778                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          3514440                       # DTB hits
system.cpu1.dtb.misses                           2465                       # DTB misses
system.cpu1.dtb.accesses                      3516905                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     8190394                       # ITB inst hits
system.cpu1.itb.inst_misses                      1200                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     949                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8191594                       # ITB inst accesses
system.cpu1.itb.hits                          8190394                       # DTB hits
system.cpu1.itb.misses                           1200                       # DTB misses
system.cpu1.itb.accesses                      8191594                       # DTB accesses
system.cpu1.numCycles                       584767176                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7979697                       # Number of instructions committed
system.cpu1.committedOps                     10128513                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              9101420                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  2019                       # Number of float alu accesses
system.cpu1.num_func_calls                     304592                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1114093                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     9101420                       # number of integer instructions
system.cpu1.num_fp_insts                         2019                       # number of float instructions
system.cpu1.num_int_register_reads           53054873                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           9892627                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1441                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                580                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      3681879                       # number of memory refs
system.cpu1.num_load_insts                    2189240                       # Number of load instructions
system.cpu1.num_store_insts                   1492639                       # Number of store instructions
system.cpu1.num_idle_cycles              548440957.661697                       # Number of idle cycles
system.cpu1.num_busy_cycles              36326218.338303                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.062121                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.937879                       # Percentage of idle cycles
system.cpu1.Branches                          1446987                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 5386      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                  6616988     64.14%     64.19% # Class of executed instruction
system.cpu1.op_class::IntMult                   11601      0.11%     64.31% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               298      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.31% # Class of executed instruction
system.cpu1.op_class::MemRead                 2189240     21.22%     85.53% # Class of executed instruction
system.cpu1.op_class::MemWrite                1492639     14.47%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  10316152                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups                4788852                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          3906949                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           223643                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3181584                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2530711                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            79.542486                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 413887                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             21714                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    10930564                       # DTB read hits
system.cpu2.dtb.read_misses                     23215                       # DTB read misses
system.cpu2.dtb.write_hits                    3350483                       # DTB write hits
system.cpu2.dtb.write_misses                     6482                       # DTB write misses
system.cpu2.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                543                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2337                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      733                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   153                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      461                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                10953779                       # DTB read accesses
system.cpu2.dtb.write_accesses                3356965                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         14281047                       # DTB hits
system.cpu2.dtb.misses                          29697                       # DTB misses
system.cpu2.dtb.accesses                     14310744                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.inst_hits                     4054306                       # ITB inst hits
system.cpu2.itb.inst_misses                      4589                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                543                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    1707                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                      958                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                 4058895                       # ITB inst accesses
system.cpu2.itb.hits                          4054306                       # DTB hits
system.cpu2.itb.misses                           4589                       # DTB misses
system.cpu2.itb.accesses                      4058895                       # DTB accesses
system.cpu2.numCycles                        88316329                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           9351504                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      32524106                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    4788852                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           2944598                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      6861719                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1761177                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     50498                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles              19190819                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                 265                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              860                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        33145                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles       719724                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          402                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  4052907                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               289738                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2002                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          37419321                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.044533                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.431855                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                30562706     81.68%     81.68% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  385991      1.03%     82.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  516133      1.38%     84.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  820285      2.19%     86.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  630351      1.68%     87.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  341631      0.91%     88.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                 1045289      2.79%     91.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  230176      0.62%     92.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 2886759      7.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            37419321                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.054224                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.368268                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9979534                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             19757337                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  6196813                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               326068                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               1158658                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              609699                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                52950                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              36983425                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               178083                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               1158658                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                10528432                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                6814826                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      11435729                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  5959486                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1521262                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              34891179                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                   96                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                325442                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               887620                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents             163                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands           37432161                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            161024301                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       148452649                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups             3370                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             26548024                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                10884136                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            285664                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        261962                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3325772                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6628163                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3904378                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           525369                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          781342                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  32207136                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             505175                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 34773283                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            55288                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        7195240                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     19128466                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        148705                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     37419321                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.929287                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.589860                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           24716493     66.05%     66.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3990546     10.66%     76.72% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            2313548      6.18%     82.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            1974351      5.28%     88.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            2779950      7.43%     95.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             967650      2.59%     98.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             497474      1.33%     99.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             144778      0.39%     99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              34531      0.09%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       37419321                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  19609      1.29%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               1392955     91.52%     92.81% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               109452      7.19%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             8340      0.02%      0.02% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             19803061     56.95%     56.97% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               28127      0.08%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  3      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              3      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     57.05% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc           386      0.00%     57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            11414599     32.83%     89.88% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3518761     10.12%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              34773283                       # Type of FU issued
system.cpu2.iq.rate                          0.393736                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    1522017                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.043770                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         108565265                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         39912731                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     28072202                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               7477                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              4009                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         3345                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              36282976                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   3984                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          206198                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1536367                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         2104                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         9509                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       563915                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      5287425                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked       344896                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               1158658                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                5187034                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                87972                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32794480                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            61964                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6628163                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3904378                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            362952                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 29501                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2651                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          9509                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        107755                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect        89629                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              197384                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             33857007                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             11143266                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           916276                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        82169                       # number of nop insts executed
system.cpu2.iew.exec_refs                    14628489                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 3765120                       # Number of branches executed
system.cpu2.iew.exec_stores                   3485223                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.383361                       # Inst execution rate
system.cpu2.iew.wb_sent                      33455826                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     28075547                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 16112995                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 29113416                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.317898                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.553456                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        7147493                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         356470                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           171471                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     36260461                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.700277                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.736744                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     27338017     75.39%     75.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4438533     12.24%     87.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1258858      3.47%     91.11% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3       640995      1.77%     92.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       514559      1.42%     94.29% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       318215      0.88%     95.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       418287      1.15%     96.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       309870      0.85%     97.18% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1023127      2.82%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     36260461                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            20554943                       # Number of instructions committed
system.cpu2.commit.committedOps              25392373                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8432259                       # Number of memory references committed
system.cpu2.commit.loads                      5091796                       # Number of loads committed
system.cpu2.commit.membars                      94283                       # Number of memory barriers committed
system.cpu2.commit.branches                   3240263                       # Number of branches committed
system.cpu2.commit.fp_insts                      3299                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 22648524                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              295510                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        16933133     66.69%     66.69% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          26595      0.10%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc          386      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.79% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5091796     20.05%     86.84% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3340463     13.16%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         25392373                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1023127                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    67255841                       # The number of ROB reads
system.cpu2.rob.rob_writes                   66282532                       # The number of ROB writes
system.cpu2.timesIdled                         358696                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       50897008                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  3546076715                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   20499567                       # Number of Instructions Simulated
system.cpu2.committedOps                     25336997                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              4.308205                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        4.308205                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.232115                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.232115                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               157113831                       # number of integer regfile reads
system.cpu2.int_regfile_writes               29893796                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    46822                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   45178                       # number of floating regfile writes
system.cpu2.misc_regfile_reads               67223937                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                297064                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1535534030000                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------