path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.824861                       # Number of seconds simulated
sim_ticks                                2824861157500                       # Number of ticks simulated
final_tick                               2824861157500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 318305                       # Simulator instruction rate (inst/s)
host_op_rate                                   386131                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7310787662                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588068                       # Number of bytes of host memory used
host_seconds                                   386.40                       # Real time elapsed on the host
sim_insts                                   122991731                       # Number of instructions simulated
sim_ops                                     149199638                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           541668                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4133796                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           101440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           929920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           334208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1678016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker         4352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst           417280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data          3020416                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11164360                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       541668                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       101440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       334208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst       417280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1394596                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8401024                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8418548                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             16917                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             65110                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1585                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             14530                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           32                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5222                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             26219                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker           68                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst              6520                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data             47194                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                183416                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131266                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               135647                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            68                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              191750                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1463363                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               35910                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              329191                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              118310                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              594017                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1541                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst              147717                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             1069226                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3952180                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         191750                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          35910                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         118310                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst         147717                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             493687                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2973960                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6203                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2980163                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2973960                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             191750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1469566                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              35910                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             329191                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             118310                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             594017                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1541                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst             147717                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            1069226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6932344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        101370                       # Number of read requests accepted
system.physmem.writeReqs                        69810                       # Number of write requests accepted
system.physmem.readBursts                      101370                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      69810                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6481472                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6208                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4467008                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6487680                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4467840                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       97                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                6935                       # Per bank write bursts
system.physmem.perBankRdBursts::1                6436                       # Per bank write bursts
system.physmem.perBankRdBursts::2                6583                       # Per bank write bursts
system.physmem.perBankRdBursts::3                6249                       # Per bank write bursts
system.physmem.perBankRdBursts::4                6342                       # Per bank write bursts
system.physmem.perBankRdBursts::5                6194                       # Per bank write bursts
system.physmem.perBankRdBursts::6                6523                       # Per bank write bursts
system.physmem.perBankRdBursts::7                6688                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6445                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6967                       # Per bank write bursts
system.physmem.perBankRdBursts::10               6205                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5540                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5538                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6823                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6219                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5586                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4692                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4257                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4659                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4198                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4374                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4446                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4601                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4285                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4489                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5118                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4303                       # Per bank write bursts
system.physmem.perBankWrBursts::11               3737                       # Per bank write bursts
system.physmem.perBankWrBursts::12               3765                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4849                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4212                       # Per bank write bursts
system.physmem.perBankWrBursts::15               3812                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
system.physmem.totGap                    2823294888500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  101370                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  69810                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     77482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21030                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       584                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3783                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     3900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     3967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39513                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      277.080657                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     164.075754                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     309.106343                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16212     41.03%     41.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9667     24.47%     65.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3869      9.79%     75.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2066      5.23%     80.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1631      4.13%     84.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          996      2.52%     87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          644      1.63%     88.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          576      1.46%     90.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3852      9.75%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39513                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3600                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.123611                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      470.848490                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           3598     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3600                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3600                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.388056                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.044932                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       10.866321                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                 5      0.14%      0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 1      0.03%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                2      0.06%      0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               4      0.11%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3199     88.86%     89.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              88      2.44%     91.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              45      1.25%     92.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              29      0.81%     93.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              26      0.72%     94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               9      0.25%     94.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              30      0.83%     95.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               4      0.11%     95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              51      1.42%     97.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.22%     97.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.17%     97.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.22%     97.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              35      0.97%     98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.06%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              15      0.42%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              27      0.75%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             1      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.06%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3600                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1317228500                       # Total ticks spent queuing
system.physmem.totMemAccLat                3216097250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    506365000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13006.71                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31756.71                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.30                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.92                       # Average write queue length when enqueuing
system.physmem.readRowHits                      81828                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49728                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.80                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.23                       # Row buffer hit rate for writes
system.physmem.avgGap                     16493135.23                       # Average gap between requests
system.physmem.pageHitRate                      76.90                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  156575160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   85288500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 405210000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                230117760                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           179783588400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            73297208295                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1624589512500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1878547500615                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.380132                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2640349085250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     91913900000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     20348745750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  142143120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   77405625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 384696000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                222166800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           179783588400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            72817182225                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1617846694500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1871273876670                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.628012                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2641092160250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     91913900000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     19603403000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     4961                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                4961                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples         4961                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           4961    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         4961                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples  53085056580                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.356184                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -18908069420    -35.62%    -35.62% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    71993126000    135.62%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  53085056580                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         2703     66.58%     66.58% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1357     33.42%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         4060                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4961                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4961                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4060                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4060                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total         9021                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    11954071                       # DTB read hits
system.cpu0.dtb.read_misses                      4163                       # DTB read misses
system.cpu0.dtb.write_hits                    9292740                       # DTB write hits
system.cpu0.dtb.write_misses                      798                       # DTB write misses
system.cpu0.dtb.flush_tlb                         171                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     343                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2861                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   729                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      164                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                11958234                       # DTB read accesses
system.cpu0.dtb.write_accesses                9293538                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21246811                       # DTB hits
system.cpu0.dtb.misses                           4961                       # DTB misses
system.cpu0.dtb.accesses                     21251772                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     2298                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                2298                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples         2298                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           2298    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         2298                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples  53085056580                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.356187                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -18908211420    -35.62%    -35.62% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    71993268000    135.62%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  53085056580                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1259     73.88%     73.88% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          445     26.12%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         1704                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2298                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2298                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1704                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1704                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         4002                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    57099385                       # ITB inst hits
system.cpu0.itb.inst_misses                      2298                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         171                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     343                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1710                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                57101683                       # ITB inst accesses
system.cpu0.itb.hits                         57099385                       # DTB hits
system.cpu0.itb.misses                           2298                       # DTB misses
system.cpu0.itb.accesses                     57101683                       # DTB accesses
system.cpu0.numCycles                        69056574                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3089                       # number of quiesce instructions executed
system.cpu0.committedInsts                   55687288                       # Number of instructions committed
system.cpu0.committedOps                     67533449                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             59242376                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4494                       # Number of float alu accesses
system.cpu0.num_func_calls                    5745250                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7381553                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    59242376                       # number of integer instructions
system.cpu0.num_fp_insts                         4494                       # number of float instructions
system.cpu0.num_int_register_reads          109364811                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          41080412                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3324                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1172                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           205588674                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25205684                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     21809022                       # number of memory refs
system.cpu0.num_load_insts                   12095983                       # Number of load instructions
system.cpu0.num_store_insts                   9713039                       # Number of store instructions
system.cpu0.num_idle_cycles              65267085.823243                       # Number of idle cycles
system.cpu0.num_busy_cycles              3789488.176757                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.054875                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.945125                       # Percentage of idle cycles
system.cpu0.Branches                         13519145                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2178      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 46763414     68.14%     68.14% # Class of executed instruction
system.cpu0.op_class::IntMult                   50008      0.07%     68.22% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              3788      0.01%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.22% # Class of executed instruction
system.cpu0.op_class::MemRead                12095983     17.63%     85.85% # Class of executed instruction
system.cpu0.op_class::MemWrite                9713039     14.15%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68628410                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           834050                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.996936                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           46064647                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           834562                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            55.196195                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   476.071339                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data    12.092828                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.251514                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data    17.581255                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929827                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.023619                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.012210                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.034338                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        193245600                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       193245600                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11356239                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      3664672                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4328495                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data      6495255                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25844661                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      8949597                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      2623161                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      3363595                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data      3984568                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18920921                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       168479                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        54501                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        74889                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data        87939                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       385808                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       206884                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74620                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        78611                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        90103                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       450218                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       207827                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76598                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        81511                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data        94149                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460085                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20305836                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      6287833                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7692090                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     10479823                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        44765582                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20474315                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      6342334                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7766979                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     10567762                       # number of overall hits
system.cpu0.dcache.overall_hits::total       45151390                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       160139                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        56826                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data        95747                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data       208800                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       521512                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       126331                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        30845                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data        98242                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      1106881                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1362299                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        49119                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17960                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32621                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data        39358                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       139058                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3523                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2624                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3843                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8172                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18162                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data           29                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       286470                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        87671                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       193989                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      1315681                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1883811                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       335589                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       105631                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data       226610                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      1355039                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2022869                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1016905000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1429116000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3734563000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6180584000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1885381500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6608027497                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  78360383850                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  86853792847                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     34848000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     54990000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    117390000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    207228000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data      1140000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1140000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   2902286500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data   8037143497                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data  82094946850                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  93034376847                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   2902286500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data   8037143497                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data  82094946850                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  93034376847                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11516378                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721498                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4424242                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data      6704055                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26366173                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9075928                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      2654006                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3461837                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data      5091449                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     20283220                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       217598                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72461                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107510                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       127297                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       524866                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       210407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77244                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        82454                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        98275                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       468380                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       207827                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76598                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        81511                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        94178                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460114                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     20592306                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      6375504                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7886079                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     11795504                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     46649393                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     20809904                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      6447965                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7993589                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     11922801                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     47174259                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013905                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015270                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021641                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031145                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.019780                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013919                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011622                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.028379                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.217400                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.067164                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.225733                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.247857                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.303423                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.309182                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264940                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016744                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033970                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.046608                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.083154                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038776                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000308                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013912                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013751                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024599                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.111541                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.040382                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016126                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016382                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.028349                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113651                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.042881                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17895.065639                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14925.961127                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17885.838123                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11851.278590                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61124.379964                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67262.754189                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70793.864788                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63755.308377                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13280.487805                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14309.133489                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14364.904552                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11409.976875                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 39310.344828                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 39310.344828                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 33104.293324                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41430.923903                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62397.303640                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 49386.258413                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27475.707889                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35466.852729                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60584.932869                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 45991.300893                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       511062                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        35422                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            12707                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            565                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.218934                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    62.693805                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       691780                       # number of writebacks
system.cpu0.dcache.writebacks::total           691780                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           78                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15282                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        95646                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       111006                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        44715                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1018039                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1062754                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1598                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2366                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5437                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9401                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data           78                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data        59997                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      1113685                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1173760                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data           78                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data        59997                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      1113685                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1173760                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56748                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        80465                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       113154                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       250367                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30845                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53527                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88842                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       173214                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17682                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22890                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28901                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        69473                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1026                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1477                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2735                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5238                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           29                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        87593                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       133992                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data       201996                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       423581                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       105275                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       156882                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data       230897                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       493054                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3437                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5496                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8482                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17415                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2787                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4251                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6706                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13744                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6224                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9747                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15188                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31159                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    958493000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1169060000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1757320500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3884873500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1854536500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3569217500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6426569434                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11850323434                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    232220000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    318179000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    509429500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1059828500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     15415000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     25315500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     42891000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     83621500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data      1111000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1111000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2813029500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4738277500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8183889934                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15735196934                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3045249500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   5056456500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8693319434                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16795025434                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    605676500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1091329500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1833276500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3530282500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    494376000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    836760000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1430842452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2761978452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1100052500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1928089500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3264118952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6292260952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015249                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018187                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016878                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009496                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011622                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015462                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017449                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008540                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.244021                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.212910                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.227036                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.132363                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.013283                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.017913                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.027830                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.011183                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000308                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013739                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016991                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017125                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.009080                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016327                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019626                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019366                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.010452                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16890.339748                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14528.801342                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15530.343603                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15516.715462                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60124.379964                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66680.693855                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72337.063934                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68414.351230                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13133.129736                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13900.349498                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17626.708418                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15255.257438                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15024.366472                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17139.810427                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15682.266910                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15964.394807                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32114.775153                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35362.391038                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40515.108883                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37148.023481                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28926.616006                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32230.953838                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37650.205217                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34063.257643                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176222.432354                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198567.958515                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.290733                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.044502                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177386.437029                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196838.390967                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213367.499553                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.851281                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176743.653599                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197813.634965                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214914.337108                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.400911                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1988229                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.436135                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           93879079                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1988741                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            47.205282                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      12780860000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   432.331889                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.896673                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    29.513324                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst    38.694249                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.844398                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021283                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.057643                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.075575                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998899                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         97900719                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        97900719                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     56377741                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     17889109                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     10408050                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst      9204179                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       93879079                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     56377741                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     17889109                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     10408050                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst      9204179                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        93879079                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     56377741                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     17889109                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     10408050                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst      9204179                       # number of overall hits
system.cpu0.icache.overall_hits::total       93879079                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       723348                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       206297                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       502765                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst       600441                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2032851                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       723348                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       206297                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       502765                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst       600441                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2032851                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       723348                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       206297                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       502765                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst       600441                       # number of overall misses
system.cpu0.icache.overall_misses::total      2032851                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2881008500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7184305500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8639566483                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18704880483                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2881008500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   7184305500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst   8639566483                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18704880483                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2881008500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   7184305500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst   8639566483                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18704880483                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     57101089                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     18095406                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     10910815                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst      9804620                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     95911930                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     57101089                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     18095406                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     10910815                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst      9804620                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     95911930                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     57101089                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     18095406                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     10910815                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst      9804620                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     95911930                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012668                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011401                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.046080                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.061241                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.021195                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012668                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011401                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.046080                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.061241                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.021195                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012668                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011401                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.046080                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.061241                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.021195                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13965.343655                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14289.589570                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14388.701776                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9201.304219                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13965.343655                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14289.589570                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14388.701776                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9201.304219                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13965.343655                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14289.589570                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14388.701776                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9201.304219                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         7220                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              329                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.945289                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1988229                       # number of writebacks
system.cpu0.icache.writebacks::total          1988229                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        44061                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        44061                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst        44061                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        44061                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst        44061                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        44061                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       206297                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       502765                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       556380                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1265442                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       206297                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       502765                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst       556380                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1265442                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       206297                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       502765                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst       556380                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1265442                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2674711500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6681541500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7547458483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16903711483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2674711500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6681541500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7547458483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16903711483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2674711500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6681541500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7547458483                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16903711483                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.046080                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.056747                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013194                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.046080                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.056747                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.013194                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011401                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.046080                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.056747                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.013194                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12965.343655                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13289.591559                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13565.294373                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13357.950410                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12965.343655                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13289.591559                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13565.294373                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13357.950410                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12965.343655                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13289.591559                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13565.294373                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13357.950410                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     1881                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                1881                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          484                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1397                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         1881                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           1881    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         1881                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1593                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14363.151287                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12650.519591                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6659.719490                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-6143          280     17.58%     17.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::6144-8191           51      3.20%     20.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::10240-12287          461     28.94%     49.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-14335           64      4.02%     53.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::14336-16383          240     15.07%     68.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-18431           70      4.39%     73.20% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::22528-24575          406     25.49%     98.68% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-26623           21      1.32%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1593                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1111     69.74%     69.74% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          482     30.26%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1593                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1881                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1881                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1593                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1593                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         3474                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3874640                       # DTB read hits
system.cpu1.dtb.read_misses                      1654                       # DTB read misses
system.cpu1.dtb.write_hits                    2733455                       # DTB write hits
system.cpu1.dtb.write_misses                      227                       # DTB write misses
system.cpu1.dtb.flush_tlb                         150                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     133                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1091                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   239                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       64                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3876294                       # DTB read accesses
system.cpu1.dtb.write_accesses                2733682                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6608095                       # DTB hits
system.cpu1.dtb.misses                           1881                       # DTB misses
system.cpu1.dtb.accesses                      6609976                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                      931                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                 931                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          177                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2          754                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples          931                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0            931    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total          931                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          674                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13750.741840                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12141.602155                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6305.334498                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143          145     21.51%     21.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.15%     21.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287          171     25.37%     47.03% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335           42      6.23%     53.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383          173     25.67%     78.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575          137     20.33%     99.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-26623            5      0.74%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          674                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          497     73.74%     73.74% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          177     26.26%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          674                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          931                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total          931                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          674                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          674                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         1605                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    18095406                       # ITB inst hits
system.cpu1.itb.inst_misses                       931                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         150                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     133                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     705                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                18096337                       # ITB inst accesses
system.cpu1.itb.hits                         18095406                       # DTB hits
system.cpu1.itb.misses                            931                       # DTB misses
system.cpu1.itb.accesses                     18096337                       # DTB accesses
system.cpu1.numCycles                       144011073                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   17425922                       # Number of instructions committed
system.cpu1.committedOps                     20908303                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             18576861                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1355                       # Number of float alu accesses
system.cpu1.num_func_calls                    1992339                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2240244                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    18576861                       # number of integer instructions
system.cpu1.num_fp_insts                         1355                       # number of float instructions
system.cpu1.num_int_register_reads           34373942                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          13031779                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1159                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                196                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            76108520                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            7595432                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      6800589                       # number of memory refs
system.cpu1.num_load_insts                    3916596                       # Number of load instructions
system.cpu1.num_store_insts                   2883993                       # Number of store instructions
system.cpu1.num_idle_cycles              136777457.840207                       # Number of idle cycles
system.cpu1.num_busy_cycles              7233615.159793                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.050230                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.949770                       # Percentage of idle cycles
system.cpu1.Branches                          4344988                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   22      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 14692274     68.30%     68.30% # Class of executed instruction
system.cpu1.op_class::IntMult                   16424      0.08%     68.38% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               958      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.38% # Class of executed instruction
system.cpu1.op_class::MemRead                 3916596     18.21%     86.59% # Class of executed instruction
system.cpu1.op_class::MemWrite                2883993     13.41%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  21510267                       # Class of executed instruction
system.cpu2.branchPred.lookups                5796775                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          2983658                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           509824                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3342660                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2404944                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            71.947012                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                1622496                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            331360                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    13089                       # Table walker walks requested
system.cpu2.dtb.walker.walksShort               13089                       # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8217                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4872                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        13089                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          13089    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        13089                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples         2190                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 13303.881279                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 11625.278622                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev  8511.286061                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767         2189     99.95%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total         2190                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000052000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000052000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000052000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K         1357     61.96%     61.96% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M          833     38.04%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total         2190                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        13089                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        13089                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2190                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2190                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total        15279                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                     4658776                       # DTB read hits
system.cpu2.dtb.read_misses                     11701                       # DTB read misses
system.cpu2.dtb.write_hits                    3572503                       # DTB write hits
system.cpu2.dtb.write_misses                     1388                       # DTB write misses
system.cpu2.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                     167                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    1490                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      207                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   330                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      125                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                 4670477                       # DTB read accesses
system.cpu2.dtb.write_accesses                3573891                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                          8231279                       # DTB hits
system.cpu2.dtb.misses                          13089                       # DTB misses
system.cpu2.dtb.accesses                      8244368                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                     1368                       # Table walker walks requested
system.cpu2.itb.walker.walksShort                1368                       # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1          248                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1120                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples         1368                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0           1368    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total         1368                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples          861                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 13222.996516                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 11667.249033                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev  6172.725517                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::4096-6143          213     24.74%     24.74% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::6144-8191            1      0.12%     24.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::10240-12287          235     27.29%     52.15% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::12288-14335           37      4.30%     56.45% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::14336-16383          216     25.09%     81.53% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::22528-24575          156     18.12%     99.65% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-26623            3      0.35%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total          861                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000037500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000037500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000037500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K          613     71.20%     71.20% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M          248     28.80%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total          861                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1368                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1368                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          861                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total          861                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total         2229                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    10912675                       # ITB inst hits
system.cpu2.itb.inst_misses                      1368                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                     167                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                     871                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     1750                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                10914043                       # ITB inst accesses
system.cpu2.itb.hits                         10912675                       # DTB hits
system.cpu2.itb.misses                           1368                       # DTB misses
system.cpu2.itb.accesses                     10914043                       # DTB accesses
system.cpu2.numCycles                      1393518293                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                   20499509                       # Number of instructions committed
system.cpu2.committedOps                     24824986                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                      1466668                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                      563                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                  4256214875                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             67.978130                       # CPI: cycles per instruction
system.cpu2.ipc                              0.014711                       # IPC: instructions per cycle
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                       42617577                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     1350900716                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               13279535                       # Number of BP lookups
system.cpu3.branchPred.condPredicted          7247058                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect           312507                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups             8265977                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                6247053                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            75.575495                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                3099050                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect             16324                       # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                    33115                       # Table walker walks requested
system.cpu3.dtb.walker.walksShort               33115                       # Table walker walks initiated with short descriptors
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11558                       # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7619                       # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore        13938                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples        19177                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean   468.973249                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev  3138.682305                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-8191        18760     97.83%     97.83% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::8192-16383          261      1.36%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::16384-24575           95      0.50%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::24576-32767           29      0.15%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-40959           11      0.06%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::40960-49151           11      0.06%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::49152-57343            5      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-73727            4      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total        19177                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples         6222                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 13175.506268                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 10775.791198                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev  8313.068780                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-16383         4548     73.10%     73.10% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::16384-32767         1554     24.98%     98.07% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-49151          108      1.74%     99.81% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::49152-65535            9      0.14%     99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-147455            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::147456-163839            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total         6222                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples  -8045387064                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean     1.137184                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-1  -8091405064    100.57%    100.57% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::2-3     33349500     -0.41%    100.16% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-5      6720000     -0.08%    100.07% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::6-7      2348000     -0.03%    100.04% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-9      1216500     -0.02%    100.03% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::10-11       680000     -0.01%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-13       415500     -0.01%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::14-15       841500     -0.01%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-17       133000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::18-19       159500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-21        77000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::22-23        11000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-25        34000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::26-27        10000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-29         3500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::30-31        19000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total  -8045387064                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K         1814     68.95%     68.95% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::1M          817     31.05%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total         2631                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33115                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33115                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2631                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2631                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total        35746                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                     7259419                       # DTB read hits
system.cpu3.dtb.read_misses                     28704                       # DTB read misses
system.cpu3.dtb.write_hits                    5430970                       # DTB write hits
system.cpu3.dtb.write_misses                     4411                       # DTB write misses
system.cpu3.dtb.flush_tlb                         162                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                    1937                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                      485                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                   827                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                      313                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                 7288123                       # DTB read accesses
system.cpu3.dtb.write_accesses                5435381                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                         12690389                       # DTB hits
system.cpu3.dtb.misses                          33115                       # DTB misses
system.cpu3.dtb.accesses                     12723504                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                     4611                       # Table walker walks requested
system.cpu3.itb.walker.walksShort                4611                       # Table walker walks initiated with short descriptors
system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1576                       # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2936                       # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore           99                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples         4512                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1190.824468                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev  4827.188758                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-8191         4272     94.68%     94.68% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::8192-16383          112      2.48%     97.16% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::16384-24575           85      1.88%     99.05% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::24576-32767           29      0.64%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-40959            6      0.13%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::40960-49151            4      0.09%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::49152-57343            1      0.02%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::57344-65535            1      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-73727            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::73728-81919            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total         4512                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples         1416                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 13825.918079                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 11456.247028                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev  8136.352957                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-4095           24      1.69%      1.69% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::4096-8191          390     27.54%     29.24% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::8192-12287          346     24.44%     53.67% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::12288-16383          256     18.08%     71.75% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::16384-20479           18      1.27%     73.02% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::20480-24575          314     22.18%     95.20% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::24576-28671           43      3.04%     98.23% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::28672-32767            4      0.28%     98.52% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-36863            3      0.21%     98.73% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::36864-40959            3      0.21%     98.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::40960-45055            8      0.56%     99.51% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::45056-49151            3      0.21%     99.72% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::53248-57343            1      0.07%     99.79% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::57344-61439            2      0.14%     99.93% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::61440-65535            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total         1416                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples  -3903952768                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     0.701862                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev     0.456296                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0    -1162140296     29.77%     29.77% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1    -2743359472     70.27%    100.04% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2        1351500     -0.03%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3         161000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4          34500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total  -3903952768                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K          967     73.42%     73.42% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::1M          350     26.58%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total         1317                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4611                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4611                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1317                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1317                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total         5928                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                     9805675                       # ITB inst hits
system.cpu3.itb.inst_misses                      4611                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                         162                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                    1315                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                      717                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                 9810286                       # ITB inst accesses
system.cpu3.itb.hits                          9805675                       # DTB hits
system.cpu3.itb.misses                           4611                       # DTB misses
system.cpu3.itb.accesses                      9810286                       # DTB accesses
system.cpu3.numCycles                        58198080                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles          21004644                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                      52275874                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   13279535                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches           9346103                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                     34135840                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                1598180                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                     75752                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                 771                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles              231                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles       170446                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        76408                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles          496                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                  9804624                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes               214264                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                   2206                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples          56263657                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.123824                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.271758                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                42100278     74.83%     74.83% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                 1838046      3.27%     78.09% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                 1170997      2.08%     80.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 3679420      6.54%     86.71% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                  917674      1.63%     88.35% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                  559385      0.99%     89.34% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 2919080      5.19%     94.53% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                  600185      1.07%     95.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                 2478592      4.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total            56263657                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.228178                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.898241                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                14695652                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles             32129586                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                  7839305                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles               889993                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                708923                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved              981902                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred                91350                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts              45004399                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts               298008                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles                708923                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                15180574                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                3814501                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles      22072917                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                  8236779                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles              6249745                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts              43123968                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                  829                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents                908553                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                 90362                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents               4872933                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.RenamedOperands           44747932                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            198117330                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups        48138419                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups             3926                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps             37260005                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                 7487927                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts            723224                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts        671648                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                  5026285                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads             7752515                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores            6007333                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          1093193                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         1517567                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                  41462674                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded             517140                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                 39449683                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued            52518                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined        6046914                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     13857480                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved         54926                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples     56263657                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.701157                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.409344                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0           40631196     72.22%     72.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1            5180458      9.21%     81.42% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2            3984831      7.08%     88.51% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3            3217649      5.72%     94.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4            1270759      2.26%     96.48% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5             778914      1.38%     97.87% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6             843481      1.50%     99.37% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7             242828      0.43%     99.80% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8             113541      0.20%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total       56263657                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                  56843      9.40%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                285724     47.25%     56.65% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite               262185     43.35%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu             26236947     66.51%     66.51% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult               29772      0.08%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.58% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc          2427      0.01%     66.59% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.59% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     66.59% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.59% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead             7477838     18.96%     85.54% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite            5702609     14.46%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total              39449683                       # Type of FU issued
system.cpu3.iq.rate                          0.677852                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                     604752                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.015330                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads         135811723                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes         48051371                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses     38283859                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads               8570                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes              4586                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses         3750                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses              40049753                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                   4598                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads          172364                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      1182055                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses         1378                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation        29890                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores       609761                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads       109360                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked        44921                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                708923                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                3187363                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles               509464                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts           42027375                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts            77349                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts              7752515                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts             6007333                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts            267430                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                 22605                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents               480734                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents         29890                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect        141333                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect       125701                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts              267034                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts             39117599                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts              7344612                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts           299061                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        47561                       # number of nop insts executed
system.cpu3.iew.exec_refs                    12987668                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                 7261479                       # Number of branches executed
system.cpu3.iew.exec_stores                   5643056                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.672146                       # Inst execution rate
system.cpu3.iew.wb_sent                      38828070                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                     38287609                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                 20013510                       # num instructions producing a value
system.cpu3.iew.wb_consumers                 34846989                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      0.657884                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.574325                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts        6062120                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls         462214                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts           222319                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples     54968801                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.654162                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.550259                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0     41122825     74.81%     74.81% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1      6168562     11.22%     86.03% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2      3091321      5.62%     91.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      1317611      2.40%     94.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4       712190      1.30%     95.35% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5       498110      0.91%     96.26% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6       959967      1.75%     98.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7       230353      0.42%     98.42% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8       867862      1.58%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total     54968801                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts            29404628                       # Number of instructions committed
system.cpu3.commit.committedOps              35958516                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      11968032                       # Number of memory references committed
system.cpu3.commit.loads                      6570460                       # Number of loads committed
system.cpu3.commit.membars                     179741                       # Number of memory barriers committed
system.cpu3.commit.branches                   6849330                       # Number of branches committed
system.cpu3.commit.fp_insts                      3728                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                 31415410                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             1242435                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu        23959277     66.63%     66.63% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult          28780      0.08%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.71% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc         2427      0.01%     66.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.72% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead        6570460     18.27%     84.99% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite       5397572     15.01%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total         35958516                       # Class of committed instruction
system.cpu3.commit.bw_lim_events               867862                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                    90498066                       # The number of ROB reads
system.cpu3.rob.rob_writes                   85338530                       # The number of ROB writes
system.cpu3.timesIdled                         230176                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                        1934423                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                  5160447116                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                   29379012                       # Number of Instructions Simulated
system.cpu3.committedOps                     35932900                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.980941                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.980941                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.504811                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.504811                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                42612953                       # number of integer regfile reads
system.cpu3.int_regfile_writes               24236017                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                    14441                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                   12266                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                138314528                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                14822107                       # number of cc regfile writes
system.cpu3.misc_regfile_reads               76357386                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                345684                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30184                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30184                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59010                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105436                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178388                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67865                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159093                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480341                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             27687500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               101500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               207000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                20000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             3849500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            22107000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            78684521                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            47950000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            15518000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36442                       # number of replacements
system.iocache.tags.tagsinuse                1.005646                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         249220700509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.005646                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.062853                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.062853                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          252                       # number of overall misses
system.iocache.overall_misses::total              252                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     18163419                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     18163419                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   1911698102                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   1911698102                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     18163419                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     18163419                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     18163419                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     18163419                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 72077.059524                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52774.351314                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 52774.351314                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 72077.059524                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 72077.059524                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 72077.059524                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 72077.059524                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          151                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        15216                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        15216                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          151                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          151                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          151                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          151                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     10613419                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     10613419                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1150219969                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1150219969                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     10613419                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     10613419                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     10613419                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     10613419                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.599206                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.599206                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.420053                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.420053                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.599206                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.599206                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.599206                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.599206                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75592.795018                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75592.795018                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70287.543046                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70287.543046                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70287.543046                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104080                       # number of replacements
system.l2c.tags.tagsinuse                65088.554606                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5171027                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169261                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.550611                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              80144379500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48906.749682                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971842                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4329.107732                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2210.968865                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      681.890061                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      812.278170                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    23.892428                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2284.499706                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data      774.800315                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    49.745028                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     3338.045671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     1675.605011                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.746258                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.066057                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.033737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.010405                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.012394                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000365                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.034859                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.011823                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.000759                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.050935                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.025568                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993173                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           57                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65124                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           57                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2187                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7581                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55275                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000870                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.993713                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45699914                       # Number of tag accesses
system.l2c.tags.data_accesses                45699914                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         4201                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         2120                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         1932                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker          979                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        14517                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         1275                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker        20680                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker         4699                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  50403                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       691780                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          691780                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1950249                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1950249                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data               9                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              41                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  64                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data            18                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                18                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            65881                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            18156                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            28270                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data            44610                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156917                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        715440                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        204709                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        497529                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst        549741                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1967419                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       206758                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        72962                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       102827                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data       140471                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           523018                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4201                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          2120                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              715440                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              272639                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          1932                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker           979                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              204709                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               91118                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         14517                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          1275                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              497529                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              131097                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker         20680                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker          4699                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst              549741                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data              185081                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2697757                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4201                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         2120                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             715440                       # number of overall hits
system.l2c.overall_hits::cpu0.data             272639                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         1932                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker          979                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             204709                       # number of overall hits
system.l2c.overall_hits::cpu1.data              91118                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        14517                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         1275                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             497529                       # number of overall hits
system.l2c.overall_hits::cpu2.data             131097                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker        20680                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker         4699                       # number of overall hits
system.l2c.overall_hits::cpu3.inst             549741                       # number of overall hits
system.l2c.overall_hits::cpu3.data             185081                       # number of overall hits
system.l2c.overall_hits::total                2697757                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           32                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker           68                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  104                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1107                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           356                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           578                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data           711                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2752                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data           11                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              11                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          59334                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          12332                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          24667                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data          43485                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139818                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         7900                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1585                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         5227                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst         6525                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           21237                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6023                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2494                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data         2004                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data         4314                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          14835                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7900                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             65357                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1585                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             14826                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           32                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5227                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             26671                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker           68                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst              6525                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data             47799                       # number of demand (read+write) misses
system.l2c.demand_misses::total                175994                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7900                       # number of overall misses
system.l2c.overall_misses::cpu0.data            65357                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1585                       # number of overall misses
system.l2c.overall_misses::cpu1.data            14826                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           32                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5227                       # number of overall misses
system.l2c.overall_misses::cpu2.data            26671                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker           68                       # number of overall misses
system.l2c.overall_misses::cpu3.inst             6525                       # number of overall misses
system.l2c.overall_misses::cpu3.data            47799                       # number of overall misses
system.l2c.overall_misses::total               175994                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      4285500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker      9038500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       13324000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       235500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       156000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data       936000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1327500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data       395000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       395000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1589408500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   3144749000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data   5760624000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10494781500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    208351000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    691825500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst    869517499                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1769693999                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    324671000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data    266991500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data    590548000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1182210500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    208351000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1914079500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      4285500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    691825500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3411740500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker      9038500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst    869517499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data   6351172000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     13460009999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    208351000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1914079500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      4285500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    691825500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3411740500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker      9038500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst    869517499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data   6351172000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    13460009999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4204                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         2121                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         1932                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker          979                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        14549                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         1275                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker        20748                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker         4699                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              50507                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       691780                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       691780                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1950249                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1950249                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1116                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          357                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          591                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data          752                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2816                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data           29                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            29                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       125215                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        30488                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        52937                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data        88095                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296735                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       723340                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       206294                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       502756                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst       556266                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1988656                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       212781                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        75456                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       104831                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data       144785                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       537853                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4204                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         2121                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          723340                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337996                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         1932                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker          979                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          206294                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          105944                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        14549                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         1275                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          502756                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          157768                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker        20748                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker         4699                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst          556266                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data          232880                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2873751                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4204                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         2121                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         723340                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337996                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         1932                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker          979                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         206294                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         105944                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        14549                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         1275                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         502756                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         157768                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker        20748                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker         4699                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst         556266                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data         232880                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2873751                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000714                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002199                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003277                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.002059                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991935                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.997199                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.978003                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.945479                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.977273                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.379310                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.379310                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.473857                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.404487                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.465969                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.493615                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.471188                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010922                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007683                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.010397                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.011730                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010679                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028306                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033052                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019116                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.029796                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027582                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010922                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.193366                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007683                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.139942                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002199                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.010397                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.169052                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003277                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.011730                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.205252                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061242                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000471                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010922                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.193366                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007683                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.139942                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002199                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.010397                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.169052                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003277                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.011730                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.205252                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061242                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 133921.875000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 132919.117647                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 128115.384615                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   661.516854                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   269.896194                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  1316.455696                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   482.376453                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 35909.090909                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 35909.090909                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128884.892961                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127488.101512                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132473.818558                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75060.303394                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131451.735016                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132356.131624                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 133259.386820                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 83330.696379                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130180.834002                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 133229.291417                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 136891.052388                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79690.630266                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131451.735016                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 129102.893565                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 133921.875000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 132356.131624                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 127919.481834                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 132919.117647                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 133259.386820                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 132872.486872                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 76479.936810                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131451.735016                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 129102.893565                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 133921.875000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 132356.131624                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 127919.481834                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 132919.117647                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 133259.386820                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 132872.486872                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 76479.936810                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95076                       # number of writebacks
system.l2c.writebacks::total                    95076                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data           19                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data           44                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           63                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data             44                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 69                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data            44                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                69                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           32                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           68                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             100                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          356                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          578                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data          711                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1645                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data           11                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           11                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        12332                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        24667                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data        43485                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         80484                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1585                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5226                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         6520                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        13331                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2494                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1985                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4270                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         8749                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1585                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        14826                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           32                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5226                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        26652                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker           68                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst         6520                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data        47755                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           102664                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1585                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        14826                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           32                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5226                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        26652                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker           68                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst         6520                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data        47755                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          102664                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3437                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         5496                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         8482                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        17415                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2787                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4251                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6706                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        13744                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6224                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data         9747                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        15188                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        31159                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3965500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      8358500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     12324000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     24216000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39310000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     48348000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    111874000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       754000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       754000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1466088500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2898079000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5325773501                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9689941001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    192501000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    639457000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    803848503                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1635806503                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    299731000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    244920500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    542449002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1087100502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    192501000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1765819500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3965500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    639457000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   3142999500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      8358500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst    803848503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data   5868222503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  12425172006                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    192501000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1765819500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3965500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    639457000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   3142999500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      8358500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst    803848503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data   5868222503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  12425172006                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    562695000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1022622000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1727239500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3312556500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    462306000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    787872000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1353651000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2603829000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1025001000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1810494000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   3080890500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5916385500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002199                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003277                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001980                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.997199                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.978003                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.945479                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.584162                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.379310                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.379310                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.404487                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.465969                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.493615                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.271232                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007683                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.010395                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011721                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006704                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033052                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.018935                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029492                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016267                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007683                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.139942                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002199                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010395                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.168932                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003277                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011721                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.205063                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.035725                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007683                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.139942                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002199                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010395                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.168932                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003277                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011721                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.205063                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.035725                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total       123240                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.471910                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68010.380623                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        68000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68008.510638                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68545.454545                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68545.454545                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118884.892961                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117488.101512                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122473.807083                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120395.867514                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121451.735016                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122360.696517                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123289.647699                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122706.961443                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120180.834002                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 123385.642317                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127037.237002                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124254.257858                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121451.735016                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119102.893565                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122360.696517                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117927.341288                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123289.647699                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122881.844896                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 121027.546228                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121451.735016                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119102.893565                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122360.696517                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117927.341288                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123289.647699                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122881.844896                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 121027.546228                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163716.904277                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186066.593886                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.875973                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190212.833764                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165879.440258                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185338.038109                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201856.695497                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.051804                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164685.250643                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185748.845799                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.309455                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.258577                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
system.membus.trans_dist::ReadResp              76472                       # Transaction distribution
system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131266                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9256                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4564                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             11                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1783                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138006                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138006                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36358                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        21008                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       486411                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       593863                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        94027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 687890                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17273980                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17437105                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2322624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2322624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19759729                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              308                       # Total snoops (count)
system.membus.snoop_fanout::samples            423370                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  423370    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              423370                       # Request fanout histogram
system.membus.reqLayer0.occupancy            54054500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              683000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           487802765                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          583127250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy             785081                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5675245                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2851889                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        45299                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            358                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          358                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             112467                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2639200                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       761596                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1988229                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          147548                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2816                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            29                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2845                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296735                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296735                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1988790                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       538004                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        15216                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5983726                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2626321                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26876                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       102356                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8739279                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    254557176                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97876281                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        44416                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       183100                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              352660973                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          192738                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4203717                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021388                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.144675                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4113806     97.86%     97.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  89911      2.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4203717                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3488536999                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           176919                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1898856602                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         770188700                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11632976                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          48177210                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------