path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.401127                       # Number of seconds simulated
sim_ticks                                2401127269500                       # Number of ticks simulated
final_tick                               2401127269500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 142330                       # Simulator instruction rate (inst/s)
host_op_rate                                   182788                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5664980832                       # Simulator tick rate (ticks/s)
host_mem_usage                                 401540                       # Number of bytes of host memory used
host_seconds                                   423.85                       # Real time elapsed on the host
sim_insts                                    60327009                       # Number of instructions simulated
sim_ops                                      77475387                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           511520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          7145552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            78912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           687680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           173184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1243936                       # Number of bytes read from this memory
system.physmem.bytes_read::total            124660496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       511520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        78912                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       173184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          763616                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3744064                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1523456                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data        157860                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data       1334500                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6759880                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             14195                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            111683                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1233                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10745                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              2706                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             19444                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14512400                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58501                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           380864                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data            39465                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           333625                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812455                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47818820                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              213033                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2975916                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               32865                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              286399                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           160                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               72126                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              518063                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51917488                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         213033                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          32865                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          72126                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             318024                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1559294                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             634475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data              65744                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             555781                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2815294                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1559294                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47818820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             213033                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3610391                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              32865                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             352143                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              72126                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1073844                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54732782                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      12420439                       # Total number of read requests seen
system.physmem.writeReqs                       390212                       # Total number of write requests seen
system.physmem.cpureqs                          53603                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    794908096                       # Total number of bytes read from memory
system.physmem.bytesWritten                  24973568                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              101274592                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                2588168                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        1                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               2354                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                776339                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                775940                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                776092                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                776425                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                777292                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                776809                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                775620                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                775424                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                775584                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                776041                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               775688                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               776201                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               777483                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               777433                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               776149                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               775918                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 25457                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 25320                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 25407                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 25903                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 26305                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 26088                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 25428                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 23374                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 23183                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 23262                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                21306                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                21574                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                24629                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                24259                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                23496                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                25221                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       14413                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2400092064000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       8                       # Categorize read packet sizes
system.physmem.readPktSize::3                12386304                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                   34127                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 373090                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  17122                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    803531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    778993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    809862                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3060255                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2298083                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2298065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2262695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     12148                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     12111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     22591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    33065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    22584                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1615                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1614                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1614                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1612                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     16974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    16970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    16964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    16959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    16952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    16947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    16944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    16942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    16934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    16933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    16925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    16922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    16920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    14497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    14485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    14475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    14454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    14452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    14449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    14443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    14437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    14427                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        20861                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    39302.074493                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    6009.687839                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   33098.413312                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95           3004     14.40%     14.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159         1328      6.37%     20.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223          811      3.89%     24.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287          565      2.71%     27.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351          381      1.83%     29.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415          362      1.74%     30.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479          265      1.27%     32.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543          238      1.14%     33.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607          172      0.82%     34.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671          151      0.72%     34.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735          130      0.62%     35.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799          127      0.61%     36.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863           66      0.32%     36.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927           86      0.41%     36.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991           45      0.22%     37.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055           78      0.37%     37.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119           36      0.17%     37.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183           26      0.12%     37.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247           22      0.11%     37.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311           43      0.21%     38.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375           28      0.13%     38.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439           87      0.42%     38.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503          101      0.48%     39.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567           96      0.46%     39.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631           23      0.11%     39.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695           38      0.18%     39.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759           20      0.10%     39.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823           38      0.18%     40.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887           12      0.06%     40.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951           22      0.11%     40.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015            8      0.04%     40.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079           17      0.08%     40.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143           10      0.05%     40.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207            9      0.04%     40.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271            4      0.02%     40.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335            3      0.01%     40.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399            5      0.02%     40.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463            9      0.04%     40.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527            4      0.02%     40.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591            4      0.02%     40.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655            2      0.01%     40.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719            2      0.01%     40.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783            6      0.03%     40.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847            3      0.01%     40.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911            7      0.03%     40.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975            1      0.00%     40.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039            2      0.01%     40.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103            4      0.02%     40.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167            1      0.00%     40.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231            3      0.01%     40.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295            3      0.01%     40.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359            8      0.04%     40.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423            2      0.01%     40.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487            3      0.01%     40.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551            1      0.00%     40.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615            3      0.01%     40.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679            2      0.01%     40.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743            2      0.01%     40.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807            2      0.01%     40.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871            1      0.00%     40.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999            1      0.00%     40.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063            1      0.00%     40.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127            6      0.03%     40.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191            2      0.01%     40.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383            3      0.01%     40.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703            1      0.00%     40.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767            2      0.01%     40.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831            2      0.01%     40.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959            1      0.00%     40.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023            1      0.00%     41.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151            1      0.00%     41.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471            1      0.00%     41.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535            1      0.00%     41.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559            1      0.00%     41.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815            4      0.02%     41.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943            1      0.00%     41.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071            2      0.01%     41.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7135            1      0.00%     41.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391            2      0.01%     41.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455            1      0.00%     41.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711            2      0.01%     41.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903            3      0.01%     41.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031            1      0.00%     41.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095            1      0.00%     41.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223            2      0.01%     41.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11167            1      0.00%     41.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11807            1      0.00%     41.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319            1      0.00%     41.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15199            1      0.00%     41.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463            1      0.00%     41.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19487            1      0.00%     41.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31007            1      0.00%     41.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33567            2      0.01%     41.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823            1      0.00%     41.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567        12093     57.97%     99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::127424-127455            1      0.00%     99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103          181      0.87%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          20861                       # Bytes accessed per row activation
system.physmem.totQLat                   241895050750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              315493767000                       # Sum of mem lat for all requests
system.physmem.totBusLat                  62102190000                       # Total cycles spent in databus access
system.physmem.totBankLat                 11496526250                       # Total cycles spent in bank access
system.physmem.avgQLat                       19475.57                       # Average queueing delay per request
system.physmem.avgBankLat                      925.61                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  25401.18                       # Average memory access latency
system.physmem.avgRdBW                         331.06                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          10.40                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  42.18                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.08                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.67                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.13                       # Average read queue length over time
system.physmem.avgWrQLen                         0.40                       # Average write queue length over time
system.physmem.readRowHits                   12404411                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    385376                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  98.76                       # Row buffer hit rate for writes
system.physmem.avgGap                       187351.30                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     55731119                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            12759502                       # Transaction distribution
system.membus.trans_dist::ReadResp           12759502                       # Transaction distribution
system.membus.trans_dist::WriteReq             375940                       # Transaction distribution
system.membus.trans_dist::WriteResp            375940                       # Transaction distribution
system.membus.trans_dist::Writeback             17122                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2354                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2354                       # Transaction distribution
system.membus.trans_dist::ReadExReq             26440                       # Transaction distribution
system.membus.trans_dist::ReadExResp            26440                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       736482                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       836280                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          224                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1572986                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     24772608                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     24772608                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave       736482                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port     25608888                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio          224                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               26345594                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       740439                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      4772328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      5513215                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     99090432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     99090432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave       740439                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port    103862760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           104603647                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              133817510                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           420513000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy         13413227250                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.6                       # Layer utilization (%)
system.membus.reqLayer3.occupancy              209500                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1495675396                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        27962648500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
system.l2c.replacements                         63244                       # number of replacements
system.l2c.tagsinuse                     50337.430960                       # Cycle average of tags in use
system.l2c.total_refs                         1749337                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        128639                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.598808                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2374950539000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36831.801957                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       0.000018                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000124                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5222.807479                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          3773.258681                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       0.993312                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           729.926692                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           767.531716                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.dtb.walker       5.853930                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst          1434.252547                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data          1571.004504                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.562009                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.079694                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.057575                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.011138                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.011712                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.dtb.walker      0.000089                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.021885                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.023972                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.768088                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         9056                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3360                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             461135                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             166289                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         2625                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1208                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             135286                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              65788                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        18369                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         4267                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             282351                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             141179                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1290913                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          597640                       # number of Writeback hits
system.l2c.Writeback_hits::total               597640                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            60771                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            19509                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            33371                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113651                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          9056                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3360                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              461135                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              227060                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          2625                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1208                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              135286                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               85297                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         18369                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          4267                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              282351                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              174550                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1404564                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         9056                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3360                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             461135                       # number of overall hits
system.l2c.overall_hits::cpu0.data             227060                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         2625                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1208                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             135286                       # number of overall hits
system.l2c.overall_hits::cpu1.data              85297                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        18369                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         4267                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             282351                       # number of overall hits
system.l2c.overall_hits::cpu2.data             174550                       # number of overall hits
system.l2c.overall_hits::total                1404564                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7579                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6397                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1233                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1202                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker            6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             2707                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data             2549                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21677                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1420                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           474                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1010                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         106049                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9819                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          17491                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133359                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7579                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            112446                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1233                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             11021                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              2707                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             20040                       # number of demand (read+write) misses
system.l2c.demand_misses::total                155036                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7579                       # number of overall misses
system.l2c.overall_misses::cpu0.data           112446                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1233                       # number of overall misses
system.l2c.overall_misses::cpu1.data            11021                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             2707                       # number of overall misses
system.l2c.overall_misses::cpu2.data            20040                       # number of overall misses
system.l2c.overall_misses::total               155036                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        89000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     89818000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     89084500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       505000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    211342500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    194046000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      584885000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       114000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data        91000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       205000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    617735500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1222387000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1840122500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        89000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     89818000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    706820000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker       505000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    211342500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   1416433000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2425007500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        89000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     89818000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    706820000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker       505000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    211342500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   1416433000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2425007500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9057                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3362                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         468714                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         172686                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         2626                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1208                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         136519                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          66990                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        18375                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         4267                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         285058                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         143728                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1312590                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       597640                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           597640                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1434                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          478                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1023                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2935                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       166820                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        29328                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        50862                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247010                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9057                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3362                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          468714                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          339506                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         2626                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1208                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          136519                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           96318                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        18375                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         4267                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          285058                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          194590                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1559600                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9057                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3362                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         468714                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         339506                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         2626                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1208                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         136519                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          96318                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        18375                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         4267                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         285058                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         194590                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1559600                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000110                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000595                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016170                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.037044                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009032                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.017943                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000327                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.009496                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.017735                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016515                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990237                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991632                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.987292                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.989438                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.635709                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.334800                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.343891                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.539893                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000110                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000595                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016170                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.331205                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009032                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.114423                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000327                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.009496                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.102986                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.099408                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000110                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000595                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016170                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.331205                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009032                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.114423                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000327                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.009496                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.102986                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.099408                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72845.093268                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74113.560732                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84166.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78072.589583                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 76126.324049                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 26981.824053                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   240.506329                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data    90.099010                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total    70.592287                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 62912.261941                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 69886.627408                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 13798.262584                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72845.093268                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 64133.926141                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84166.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78072.589583                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 70680.289421                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 15641.576795                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72845.093268                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 64133.926141                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84166.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78072.589583                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 70680.289421                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 15641.576795                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58501                       # number of writebacks
system.l2c.writebacks::total                    58501                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1233                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1202                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         2706                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data         2539                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7687                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          474                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1010                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1484                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9819                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        17491                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         27310                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1233                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        11021                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         2706                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        20030                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            34997                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1233                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        11021                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         2706                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        20030                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           34997                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     74352750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     74070750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       430000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    177633750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    161814500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    488378000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4740474                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10101010                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     14841484                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    495712276                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1004156094                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1499868370                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     74352750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    569783026                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       430000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    177633750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1165970594                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1988246370                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     74352750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    569783026                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       430000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    177633750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1165970594                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1988246370                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25115656000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26467069000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  51582725000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    935834000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   9813018750                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  10748852750                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26051490000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  36280087750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  62331577750                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009032                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017943                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000327                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.009493                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.017665                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005856                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991632                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.987292                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.505622                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.334800                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.343891                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.110562                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009032                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.114423                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000327                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.009493                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.102934                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.022440                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009032                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.114423                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000327                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.009493                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.102934                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.022440                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60302.311436                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61622.920133                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65644.401330                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63731.587239                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63532.977755                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50485.006212                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57409.873306                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 54920.116075                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60302.311436                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51699.757372                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65644.401330                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58211.212881                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 56811.908735                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60302.311436                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51699.757372                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65644.401330                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58211.212881                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 56811.908735                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58868329                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            1038711                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1038710                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            375940                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           375940                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           275281                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1501                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1503                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            80190                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           80190                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side       843862                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side      2343005                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma        15512                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma        51160                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count                      3253539                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side     26980864                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side     38469375                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma        21900                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma        84004                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size                  65556143                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             141250094                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          100256                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2175069728                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1900577406                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1863798035                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          10055959                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          30318675                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48814240                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             12751762                       # Transaction distribution
system.iobus.trans_dist::ReadResp            12751762                       # Transaction distribution
system.iobus.trans_dist::WriteReq                2783                       # Transaction distribution
system.iobus.trans_dist::WriteResp               2783                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11428                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          262                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       721384                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       736482                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     24772608                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     24772608                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio        11428                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio         3102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio          262                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio       721384                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side     24772608                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                25509090                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          524                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       717707                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       740439                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     99090432                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     99090432                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio        15392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio         6204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio          524                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio       717707                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side     99090432                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             99830871                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               117209202                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              7987000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              1551000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               131000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy            361193000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         12386304000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           733699000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         24772608000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.0                       # Layer utilization (%)
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8064428                       # DTB read hits
system.cpu0.dtb.read_misses                      6238                       # DTB read misses
system.cpu0.dtb.write_hits                    6663212                       # DTB write hits
system.cpu0.dtb.write_misses                     2045                       # DTB write misses
system.cpu0.dtb.flush_tlb                         279                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                678                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5690                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   114                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8070666                       # DTB read accesses
system.cpu0.dtb.write_accesses                6665257                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14727640                       # DTB hits
system.cpu0.dtb.misses                           8283                       # DTB misses
system.cpu0.dtb.accesses                     14735923                       # DTB accesses
system.cpu0.itb.inst_hits                    32885888                       # ITB inst hits
system.cpu0.itb.inst_misses                      3493                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         279                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                678                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2597                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                32889381                       # ITB inst accesses
system.cpu0.itb.hits                         32885888                       # DTB hits
system.cpu0.itb.misses                           3493                       # DTB misses
system.cpu0.itb.accesses                     32889381                       # DTB accesses
system.cpu0.numCycles                       114194187                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   32400694                       # Number of instructions committed
system.cpu0.committedOps                     42604041                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             37748945                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5021                       # Number of float alu accesses
system.cpu0.num_func_calls                    1185552                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4241024                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    37748945                       # number of integer instructions
system.cpu0.num_fp_insts                         5021                       # number of float instructions
system.cpu0.num_int_register_reads          192241357                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          39867524                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3591                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1432                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     15390684                       # number of memory refs
system.cpu0.num_load_insts                    8430090                       # Number of load instructions
system.cpu0.num_store_insts                   6960594                       # Number of store instructions
system.cpu0.num_idle_cycles              13437222906.022394                       # Number of idle cycles
system.cpu0.num_busy_cycles              -13323028719.022394                       # Number of busy cycles
system.cpu0.not_idle_fraction             -116.669938                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                  117.669938                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
system.cpu0.icache.replacements                891212                       # number of replacements
system.cpu0.icache.tagsinuse               511.602596                       # Cycle average of tags in use
system.cpu0.icache.total_refs                44302670                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                891724                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 49.682043                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            8165076000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   482.545707                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst    22.025938                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst     7.030951                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.942472                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.043019                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst     0.013732                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999224                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     32419122                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      8206609                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3676939                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       44302670                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     32419122                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      8206609                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3676939                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        44302670                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     32419122                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      8206609                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3676939                       # number of overall hits
system.cpu0.icache.overall_hits::total       44302670                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       469447                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       136775                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       309614                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       915836                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       469447                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       136775                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       309614                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        915836                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       469447                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       136775                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       309614                       # number of overall misses
system.cpu0.icache.overall_misses::total       915836                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1859465000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4163389481                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6022854481                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1859465000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4163389481                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6022854481                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1859465000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4163389481                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6022854481                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     32888569                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      8343384                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3986553                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     45218506                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     32888569                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      8343384                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3986553                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     45218506                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     32888569                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      8343384                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3986553                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     45218506                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014274                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016393                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.077665                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.020254                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014274                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016393                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.077665                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.020254                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014274                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016393                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.077665                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.020254                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.064888                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13447.032373                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6576.346072                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.064888                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13447.032373                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6576.346072                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.064888                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13447.032373                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6576.346072                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3767                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              253                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.889328                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24103                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        24103                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        24103                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        24103                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        24103                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        24103                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       136775                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       285511                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       422286                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       136775                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       285511                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       422286                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       136775                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       285511                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       422286                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1585915000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3389983577                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4975898577                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1585915000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3389983577                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4975898577                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1585915000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3389983577                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4975898577                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016393                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.071619                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009339                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016393                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.071619                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009339                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016393                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.071619                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009339                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11595.064888                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11873.390437                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11783.243056                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11595.064888                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11873.390437                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11783.243056                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11595.064888                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11873.390437                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11783.243056                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                629902                       # number of replacements
system.cpu0.dcache.tagsinuse               511.997116                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                23235714                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                630414                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 36.857865                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              21763000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   495.218177                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data    10.352055                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data     6.426883                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.967223                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.020219                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data     0.012553                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6947687                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1880449                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4482403                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13310539                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5976316                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1357235                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2102606                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9436157                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       130925                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        34235                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73479                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       238639                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137233                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        36022                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74133                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247388                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12924003                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      3237684                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6585009                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        22746696                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12924003                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      3237684                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6585009                       # number of overall hits
system.cpu0.dcache.overall_hits::total       22746696                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       166378                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        65203                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       287520                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       519101                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       168254                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        29806                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       582137                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       780197                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6308                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1787                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3867                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11962                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       334632                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        95009                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       869657                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1299298                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       334632                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data        95009                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data       869657                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1299298                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    929063500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   4173310500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5102374000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    913104500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  20713365411                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  21626469911                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     23449000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     51231000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     74680000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        26000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   1842168000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  24886675911                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  26728843911                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   1842168000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  24886675911                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  26728843911                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7114065                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1945652                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4769923                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13829640                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      6144570                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1387041                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2684743                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10216354                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       137233                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        36022                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77346                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       250601                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       137233                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        36022                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74135                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247390                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13258635                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      3332693                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7454666                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24045994                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13258635                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      3332693                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7454666                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24045994                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.023387                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033512                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.060278                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037535                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027383                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021489                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.216832                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.076367                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045966                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049609                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.049996                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047733                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000027                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025239                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028508                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116659                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.054034                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.025239                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028508                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.116659                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.054034                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14248.784565                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14514.852880                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9829.250955                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30634.922499                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35581.599196                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 27719.242590                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13121.992166                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13248.254461                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6243.103160                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19389.405214                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28616.656810                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20571.757912                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19389.405214                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 28616.656810                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 20571.757912                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        10003                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3430                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             1178                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             49                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.491511                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       597640                       # number of writebacks
system.cpu0.dcache.writebacks::total           597640                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       147191                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       147191                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       530305                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       530305                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          415                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          415                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       677496                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       677496                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       677496                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       677496                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        65203                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       140329                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       205532                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        29806                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        51832                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total        81638                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1787                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3452                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5239                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        95009                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       192161                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       287170                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data        95009                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       192161                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       287170                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    798657500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1814845381                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2613502881                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    853492500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1663883074                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2517375574                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19875000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     39692503                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     59567503                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1652150000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3478728455                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5130878455                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1652150000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3478728455                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5130878455                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27438525500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28895903000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  56334428500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1439019500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13930302419                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  15369321919                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28877545000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42826205419                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  71703750419                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033512                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.029420                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014862                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021489                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019306                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007991                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.049609                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.044631                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020906                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000027                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028508                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.025777                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.011943                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028508                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.025777                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.011943                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     2160353                       # DTB read hits
system.cpu1.dtb.read_misses                      2072                       # DTB read misses
system.cpu1.dtb.write_hits                    1463428                       # DTB write hits
system.cpu1.dtb.write_misses                      375                       # DTB write misses
system.cpu1.dtb.flush_tlb                         277                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                240                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1741                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                    41                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       78                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 2162425                       # DTB read accesses
system.cpu1.dtb.write_accesses                1463803                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          3623781                       # DTB hits
system.cpu1.dtb.misses                           2447                       # DTB misses
system.cpu1.dtb.accesses                      3626228                       # DTB accesses
system.cpu1.itb.inst_hits                     8343384                       # ITB inst hits
system.cpu1.itb.inst_misses                      1170                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         277                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                240                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     867                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8344554                       # ITB inst accesses
system.cpu1.itb.hits                          8343384                       # DTB hits
system.cpu1.itb.misses                           1170                       # DTB misses
system.cpu1.itb.accesses                      8344554                       # DTB accesses
system.cpu1.numCycles                       576594127                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    8139213                       # Number of instructions committed
system.cpu1.committedOps                     10387341                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              9296011                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  2143                       # Number of float alu accesses
system.cpu1.num_func_calls                     319457                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1149983                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     9296011                       # number of integer instructions
system.cpu1.num_fp_insts                         2143                       # number of float instructions
system.cpu1.num_int_register_reads           53626328                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          10059981                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1630                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                514                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      3800206                       # number of memory refs
system.cpu1.num_load_insts                    2257531                       # Number of load instructions
system.cpu1.num_store_insts                   1542675                       # Number of store instructions
system.cpu1.num_idle_cycles              550949024.070645                       # Number of idle cycles
system.cpu1.num_busy_cycles              25645102.929355                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.044477                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.955523                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups                4706679                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          3828645                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           220746                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3114772                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2519361                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            80.884283                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 411150                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             21524                       # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    10881090                       # DTB read hits
system.cpu2.dtb.read_misses                     22334                       # DTB read misses
system.cpu2.dtb.write_hits                    3233578                       # DTB write hits
system.cpu2.dtb.write_misses                     5962                       # DTB write misses
system.cpu2.dtb.flush_tlb                         276                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                521                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2292                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      695                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   165                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      471                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                10903424                       # DTB read accesses
system.cpu2.dtb.write_accesses                3239540                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         14114668                       # DTB hits
system.cpu2.dtb.misses                          28296                       # DTB misses
system.cpu2.dtb.accesses                     14142964                       # DTB accesses
system.cpu2.itb.inst_hits                     3988029                       # ITB inst hits
system.cpu2.itb.inst_misses                      4597                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         276                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                521                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    1713                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                      994                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                 3992626                       # ITB inst accesses
system.cpu2.itb.hits                          3988029                       # DTB hits
system.cpu2.itb.misses                           4597                       # DTB misses
system.cpu2.itb.accesses                      3992626                       # DTB accesses
system.cpu2.numCycles                        88357796                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           9310481                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      32575007                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    4706679                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           2930511                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      6844695                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1834626                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     50535                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles              18792292                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                 211                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              834                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        32689                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles       721380                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          412                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3986556                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               271694                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2030                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          37012176                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.054575                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.442886                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                30172484     81.52%     81.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  383589      1.04%     82.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  509700      1.38%     83.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  816595      2.21%     86.14% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  649845      1.76%     87.90% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  340688      0.92%     88.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                 1002283      2.71%     91.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  233105      0.63%     92.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 2903887      7.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            37012176                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.053268                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.368672                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9923582                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             19398911                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  6192413                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               289708                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               1206624                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              608704                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                53227                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              36668894                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               179672                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               1206624                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                10457732                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                6796532                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      11090349                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  5929465                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1530564                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              34717207                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2441                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                375073                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               892617                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents             118                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands           37295857                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            158754403                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       158727276                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups            27127                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             25598469                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                11697387                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            231672                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        208131                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3300393                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6518889                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3789656                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           530954                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          691805                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  31588093                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             511099                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 34136489                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            54725                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        7434189                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     19599124                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        154239                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     37012176                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.922304                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.578312                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           24481195     66.14%     66.14% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3912173     10.57%     76.71% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            2318887      6.27%     82.98% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2014061      5.44%     88.42% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            2743513      7.41%     95.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             884212      2.39%     98.22% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             492586      1.33%     99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             130661      0.35%     99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              34888      0.09%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       37012176                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  18493      1.21%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               1405660     91.60%     92.81% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               110389      7.19%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            61311      0.18%      0.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             19306288     56.56%     56.74% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               26277      0.08%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  7      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 1      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              6      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc           369      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            11344167     33.23%     90.05% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3398057      9.95%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              34136489                       # Type of FU issued
system.cpu2.iq.rate                          0.386344                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    1534543                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.044953                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         106895526                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         39538518                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     27366143                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               7075                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              3717                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         3145                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              35605938                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   3783                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          206498                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1561517                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         1841                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         9166                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       566678                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      5349938                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked       380447                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               1206624                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                5097630                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                92333                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32182024                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            61203                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6518889                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3789656                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            368677                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 31621                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2335                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          9166                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        105355                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect        88176                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              193531                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             33238932                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             11092763                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           897557                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        82832                       # number of nop insts executed
system.cpu2.iew.exec_refs                    14457569                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 3671446                       # Number of branches executed
system.cpu2.iew.exec_stores                   3364806                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.376186                       # Inst execution rate
system.cpu2.iew.wb_sent                      32811396                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     27369288                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 15602510                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 28268763                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.309755                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.551935                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        7374898                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         356860                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           168297                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     35805367                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.685358                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.714033                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     27231349     76.05%     76.05% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4142496     11.57%     87.62% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1257531      3.51%     91.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3       645964      1.80%     92.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       562986      1.57%     94.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       317406      0.89%     95.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       386660      1.08%     96.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       302677      0.85%     97.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       958298      2.68%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     35805367                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            19842604                       # Number of instructions committed
system.cpu2.commit.committedOps              24539507                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8180350                       # Number of memory references committed
system.cpu2.commit.loads                      4957372                       # Number of loads committed
system.cpu2.commit.membars                      94561                       # Number of memory barriers committed
system.cpu2.commit.branches                   3152552                       # Number of branches committed
system.cpu2.commit.fp_insts                      3091                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 21772655                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              294654                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events               958298                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    66237138                       # The number of ROB reads
system.cpu2.rob.rob_writes                   65080734                       # The number of ROB writes
system.cpu2.timesIdled                         362582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       51345620                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  3559271384                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   19787102                       # Number of Instructions Simulated
system.cpu2.committedOps                     24484005                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total             19787102                       # Number of Instructions Simulated
system.cpu2.cpi                              4.465424                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        4.465424                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.223943                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.223943                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               153570043                       # number of integer regfile reads
system.cpu2.int_regfile_writes               29228694                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    22407                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   20832                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                8993137                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                241651                       # number of misc regfile writes
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1181598504500                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------