path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.542296                       # Number of seconds simulated
sim_ticks                                2542295570500                       # Number of ticks simulated
final_tick                               2542295570500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  70655                       # Simulator instruction rate (inst/s)
host_op_rate                                    90914                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2978397497                       # Simulator tick rate (ticks/s)
host_mem_usage                                 409668                       # Number of bytes of host memory used
host_seconds                                   853.58                       # Real time elapsed on the host
sim_insts                                    60309877                       # Number of instructions simulated
sim_ops                                      77602149                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           504448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4169680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           296128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4925148                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131008300                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       504448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       296128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          800576                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3787072                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1346312                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1669800                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6803184                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7882                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             65185                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4627                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             76962                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293509                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59173                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           336578                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           417450                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813201                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47638256                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              198422                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1640124                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           378                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              116481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1937284                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51531498                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         198422                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         116481                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314903                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1489627                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             529565                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             656808                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2676000                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1489627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47638256                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             198422                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2169689                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          378                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             116481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2594092                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54207499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293509                       # Total number of read requests seen
system.physmem.writeReqs                       813201                       # Total number of write requests seen
system.physmem.cpureqs                         218507                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    978784576                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52044864                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              131008300                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6803184                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       14                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4684                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                956235                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                955738                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                955673                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                956489                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                956267                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                955445                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                955564                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                956162                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                956093                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                955609                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               955524                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               955926                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               956035                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               955433                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               955318                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               955984                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50833                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50416                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50435                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51159                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50911                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50191                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50281                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50860                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51366                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 50906                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50808                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51188                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51253                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50731                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                50630                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51233                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     1856479                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2542294418500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      43                       # Categorize read packet sizes
system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154650                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                2610507                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  59173                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 4684                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                   1054657                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    991834                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    961504                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3604952                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2718225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2722186                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2700242                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     60067                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59423                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    110017                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   160496                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   109935                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    10065                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     9993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    11014                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     8845                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                   346840685210                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              440008538960                       # Sum of mem lat for all requests
system.physmem.totBusLat                  76467475000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16700378750                       # Total cycles spent in bank access
system.physmem.avgQLat                       22678.97                       # Average queueing delay per request
system.physmem.avgBankLat                     1091.99                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  28770.96                       # Average memory access latency
system.physmem.avgRdBW                         385.00                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.47                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.53                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                         1.14                       # Average write queue length over time
system.physmem.readRowHits                   15218397                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    794710                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.73                       # Row buffer hit rate for writes
system.physmem.avgGap                       157840.70                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         64418                       # number of replacements
system.l2c.tagsinuse                     51401.261729                       # Cycle average of tags in use
system.l2c.total_refs                         1905310                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        129810                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         14.677683                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2531415043500                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36947.323889                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       9.916328                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000349                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5145.662568                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          3278.560293                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      13.240870                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3059.988680                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2946.568751                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.563771                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000151                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.078517                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.050027                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000202                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.046692                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.044961                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.784321                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        32362                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7566                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             491236                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             213718                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30461                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6864                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             480165                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             173950                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1436322                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          608473                       # number of Writeback hits
system.l2c.Writeback_hits::total               608473                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              19                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  33                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             4                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            57779                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            55086                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112865                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         32362                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7566                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              491236                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              271497                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30461                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6864                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              480165                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              229036                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1549187                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        32362                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7566                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             491236                       # number of overall hits
system.l2c.overall_hits::cpu0.data             271497                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30461                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6864                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             480165                       # number of overall hits
system.l2c.overall_hits::cpu1.data             229036                       # number of overall hits
system.l2c.overall_hits::total                1549187                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           20                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7773                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6102                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4633                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4618                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23163                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1544                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1370                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2914                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          60061                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          73152                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133213                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7773                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             66163                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4633                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             77770                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156376                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           20                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7773                       # number of overall misses
system.l2c.overall_misses::cpu0.data            66163                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4633                       # number of overall misses
system.l2c.overall_misses::cpu1.data            77770                       # number of overall misses
system.l2c.overall_misses::total               156376                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1354500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    429697500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    347820500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       983000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    271281500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    271043000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1322298000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       251500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       204000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       455500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3137999000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3639162500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6777161500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1354500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    429697500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3485819500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       983000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    271281500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3910205500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8099459500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1354500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    429697500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3485819500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       983000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    271281500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3910205500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8099459500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        32382                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7568                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         499009                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         219820                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30476                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6864                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         484798                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         178568                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1459485                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       608473                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           608473                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1563                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1384                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2947                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       117840                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       128238                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246078                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        32382                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7568                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          499009                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337660                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30476                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6864                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          484798                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          306806                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1705563                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        32382                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7568                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         499009                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337660                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30476                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6864                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         484798                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         306806                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1705563                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000618                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000264                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015577                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.027759                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000492                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009557                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.025861                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015871                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987844                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989884                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.988802                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.509683                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.570439                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541345                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000618                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015577                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.195946                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000492                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009557                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.253483                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.091686                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000618                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015577                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.195946                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000492                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009557                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.253483                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.091686                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        67725                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55280.779622                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 57001.065225                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 65533.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58554.176559                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58692.724123                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 57086.646807                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   162.888601                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   148.905109                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   156.314345                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52246.865687                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49747.956310                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50874.625600                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        67725                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55280.779622                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52685.330169                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 65533.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 58554.176559                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 50279.098624                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51794.773495                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        67725                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55280.779622                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52685.330169                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 65533.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 58554.176559                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 50279.098624                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51794.773495                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59173                       # number of writebacks
system.l2c.writebacks::total                    59173                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            20                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             20                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            20                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           20                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7763                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6063                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4627                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4598                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23088                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1544                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1370                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2914                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        60061                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        73152                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133213                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7763                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        66124                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4627                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        77750                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156301                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7763                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        66124                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4627                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        77750                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156301                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1106788                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    332555399                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    270417799                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       796028                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    213310327                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    212900467                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1031180060                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15532986                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13701370                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29234356                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2388927373                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2728057055                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5116984428                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1106788                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93252                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    332555399                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2659345172                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       796028                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    213310327                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2940957522                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6148164488                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1106788                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93252                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    332555399                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2659345172                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       796028                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    213310327                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2940957522                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6148164488                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5050907                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  84173719776                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82789281508                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166968052191                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  10449638570                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  13171042406                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  23620680976                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76254                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76254                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5050907                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  94623358346                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  95960323914                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190588733167                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000618                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000264                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015557                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027582                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000492                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009544                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025749                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015819                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987844                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.989884                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.988802                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.509683                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.570439                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541345                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000618                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015557                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.195830                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000492                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009544                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.253417                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.091642                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000618                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015557                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.195830                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000492                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009544                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.253417                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.091642                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39335.413644                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39335.413644                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                7620138                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          6076880                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           380507                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4965064                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4053585                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            81.642150                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 731859                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             39538                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    26058653                       # DTB read hits
system.cpu0.dtb.read_misses                     40101                       # DTB read misses
system.cpu0.dtb.write_hits                    5895373                       # DTB write hits
system.cpu0.dtb.write_misses                     9447                       # DTB write misses
system.cpu0.dtb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                771                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5619                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1431                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   273                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      647                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                26098754                       # DTB read accesses
system.cpu0.dtb.write_accesses                5904820                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31954026                       # DTB hits
system.cpu0.dtb.misses                          49548                       # DTB misses
system.cpu0.dtb.accesses                     32003574                       # DTB accesses
system.cpu0.itb.inst_hits                     6112115                       # ITB inst hits
system.cpu0.itb.inst_misses                      7637                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                771                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2623                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1579                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6119752                       # ITB inst accesses
system.cpu0.itb.hits                          6112115                       # DTB hits
system.cpu0.itb.misses                           7637                       # DTB misses
system.cpu0.itb.accesses                      6119752                       # DTB accesses
system.cpu0.numCycles                       239063312                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          15490963                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      47835555                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7620138                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4785444                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10608217                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2561094                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     89115                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              49527666                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1654                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             1892                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        49952                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       101088                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          226                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6110008                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               396628                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3581                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          77642580                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.762278                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.119818                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67041875     86.35%     86.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  689016      0.89%     87.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  885560      1.14%     88.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1228014      1.58%     89.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1141359      1.47%     91.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  577108      0.74%     92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1324549      1.71%     93.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  398041      0.51%     94.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4357058      5.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            77642580                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031875                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.200096                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16540886                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             49255967                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9607571                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               552371                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1683667                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1024811                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                90579                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56316085                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               302289                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1683667                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17475063                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               18984775                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27019953                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9154130                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3322955                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              53494037                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                13484                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                621738                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2157353                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             548                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           55660367                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            243519467                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       243471355                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            48112                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             40417937                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                15242430                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            429833                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        381699                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6758508                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10355148                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6782314                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1058612                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1316675                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  49644359                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1043369                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 63195717                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            96260                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10515144                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     26542188                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        266673                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     77642580                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.813931                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.519230                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           54792876     70.57%     70.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7218069      9.30%     79.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3694351      4.76%     84.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3145323      4.05%     88.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6277418      8.09%     96.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1407401      1.81%     98.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             809465      1.04%     99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             231906      0.30%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              65771      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       77642580                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  29563      0.66%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     4      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4229523     94.72%     95.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               206294      4.62%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass           195578      0.31%      0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29951554     47.39%     47.70% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46938      0.07%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  6      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 1      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              4      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1212      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26776565     42.37%     90.15% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6223855      9.85%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              63195717                       # Type of FU issued
system.cpu0.iq.rate                          0.264347                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4465384                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.070660                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         208632682                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         61211746                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     44166006                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12339                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6563                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5520                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              67458994                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6529                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          322005                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2276398                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3543                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        16033                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       889328                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17163737                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       367898                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1683667                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               14223209                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               234272                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           50804503                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           105344                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10355148                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6782314                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            742198                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 56887                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3242                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         16033                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        187141                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       147345                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              334486                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             62025172                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26418520                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1170545                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       116775                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32585401                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6028949                       # Number of branches executed
system.cpu0.iew.exec_stores                   6166881                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.259451                       # Inst execution rate
system.cpu0.iew.wb_sent                      61495183                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     44171526                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24314220                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 44686636                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.184769                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.544105                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       10365934                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         776696                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           291216                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     75958913                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.525792                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.508136                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     61730922     81.27%     81.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6914068      9.10%     90.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2040925      2.69%     93.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1133695      1.49%     94.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1039727      1.37%     95.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       547660      0.72%     96.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       699909      0.92%     97.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       371161      0.49%     98.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1480846      1.95%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     75958913                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            31284581                       # Number of instructions committed
system.cpu0.commit.committedOps              39938560                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13971736                       # Number of memory references committed
system.cpu0.commit.loads                      8078750                       # Number of loads committed
system.cpu0.commit.membars                     212403                       # Number of memory barriers committed
system.cpu0.commit.branches                   5205711                       # Number of branches committed
system.cpu0.commit.fp_insts                      5497                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 35286774                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              514203                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1480846                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   123805555                       # The number of ROB reads
system.cpu0.rob.rob_writes                  102335061                       # The number of ROB writes
system.cpu0.timesIdled                         884089                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      161420732                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2289699870                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   31205252                       # Number of Instructions Simulated
system.cpu0.committedOps                     39859231                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             31205252                       # Number of Instructions Simulated
system.cpu0.cpi                              7.660996                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        7.660996                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.130531                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.130531                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               280760557                       # number of integer regfile reads
system.cpu0.int_regfile_writes               45445732                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    22770                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   19806                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               15502985                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                430013                       # number of misc regfile writes
system.cpu0.icache.replacements                984427                       # number of replacements
system.cpu0.icache.tagsinuse               510.429233                       # Cycle average of tags in use
system.cpu0.icache.total_refs                11039860                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                984939                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 11.208674                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6522889000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   356.685952                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst   153.743281                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.696652                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.300280                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996932                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      5569328                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5470532                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       11039860                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5569328                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5470532                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        11039860                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5569328                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5470532                       # number of overall hits
system.cpu0.icache.overall_hits::total       11039860                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       540556                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       524651                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1065207                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       540556                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       524651                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1065207                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       540556                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       524651                       # number of overall misses
system.cpu0.icache.overall_misses::total      1065207                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7319258495                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6971682996                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14290941491                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7319258495                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6971682996                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14290941491                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7319258495                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6971682996                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14290941491                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6109884                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5995183                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     12105067                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6109884                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5995183                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     12105067                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6109884                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5995183                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     12105067                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.088472                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.087512                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.087997                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.088472                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.087512                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.087997                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.088472                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.087512                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.087997                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13416.116765                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13416.116765                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4720                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              314                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.031847                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        40959                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39286                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        80245                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        40959                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        39286                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        80245                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        40959                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        39286                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        80245                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       499597                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       485365                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       984962                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       499597                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       485365                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       984962                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       499597                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       485365                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       984962                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5974261995                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5687350997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11661612992                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5974261995                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5687350997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11661612992                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5974261995                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5687350997                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11661612992                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7526000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7526000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7526000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7526000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.081769                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.080959                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.081368                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.081769                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.080959                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.081368                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.081769                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.080959                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.081368                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11958.162269                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.678442                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11839.657765                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11958.162269                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.678442                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11839.657765                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11958.162269                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.678442                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11839.657765                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                643954                       # number of replacements
system.cpu0.dcache.tagsinuse               511.992718                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                21537903                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                644466                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.419766                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43205000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   318.437002                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data   193.555716                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.621947                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.378039                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999986                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7114821                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6667161                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13781982                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3771949                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3489739                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7261688                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       125842                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117705                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       243547                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       127851                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       119764                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247615                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10886770                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10156900                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21043670                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10886770                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10156900                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21043670                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       435511                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       315516                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       751027                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1388695                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1572418                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2961113                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6824                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6787                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13611                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1824206                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1887934                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3712140                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1824206                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1887934                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3712140                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6465462500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   4867480500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11332943000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  52611155364                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  61827357784                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114438513148                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92173500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     95497500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    187671000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        52000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        78000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       130000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  59076617864                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  66694838284                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125771456148                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  59076617864                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  66694838284                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125771456148                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7550332                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      6982677                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14533009                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5160644                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5062157                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10222801                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       132666                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       124492                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       257158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       127855                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       119770                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247625                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12710976                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     12044834                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24755810                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12710976                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     12044834                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24755810                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.057681                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.045186                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051677                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.269093                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.310622                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.289658                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.051437                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054518                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052929                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000031                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000050                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000040                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.143514                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.156742                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149950                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.143514                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.156742                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149950                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14845.692761                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15427.048074                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.927526                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37885.320653                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39319.924972                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38647.128005                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.253810                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14070.649772                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13788.186026                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32384.839138                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35326.890815                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33881.118748                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32384.839138                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35326.890815                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33881.118748                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        35462                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        15651                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3547                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            261                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.997745                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    59.965517                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       608473                       # number of writebacks
system.cpu0.dcache.writebacks::total           608473                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       221772                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       142997                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       364769                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1269356                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1442834                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2712190                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          679                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          700                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1379                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1491128                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1585831                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3076959                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1491128                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1585831                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3076959                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       213739                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       172519                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       386258                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       119339                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       129584                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       248923                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6145                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         6087                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12232                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       333078                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       302103                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       635181                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       333078                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       302103                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       635181                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2903093500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2321765000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5224858500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3977310493                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   4483624933                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8460935426                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     71679000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74936000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    146615000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        44000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        66000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       110000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6880403993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6805389933                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13685793926                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6880403993                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6805389933                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13685793926                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91929858500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90426612500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356471000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  14888104285                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  18626460302                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  33514564587                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028309                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024707                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026578                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023125                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025599                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024350                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046319                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.048895                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047566                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000031                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000050                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026204                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025082                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025658                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026204                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025082                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025658                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                7047379                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5653088                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           345044                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4644809                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3819502                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            82.231627                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 672042                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             34964                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25308350                       # DTB read hits
system.cpu1.dtb.read_misses                     36279                       # DTB read misses
system.cpu1.dtb.write_hits                    5820677                       # DTB write hits
system.cpu1.dtb.write_misses                     9386                       # DTB write misses
system.cpu1.dtb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                668                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    5518                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1305                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   250                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      636                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25344629                       # DTB read accesses
system.cpu1.dtb.write_accesses                5830063                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         31129027                       # DTB hits
system.cpu1.dtb.misses                          45665                       # DTB misses
system.cpu1.dtb.accesses                     31174692                       # DTB accesses
system.cpu1.itb.inst_hits                     5997294                       # ITB inst hits
system.cpu1.itb.inst_misses                      6928                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                668                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2607                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1462                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 6004222                       # ITB inst accesses
system.cpu1.itb.hits                          5997294                       # DTB hits
system.cpu1.itb.misses                           6928                       # DTB misses
system.cpu1.itb.accesses                      6004222                       # DTB accesses
system.cpu1.numCycles                       234192897                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          15145693                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      46615728                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    7047379                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4491544                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     10277592                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2615595                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     81100                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              47506260                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                 991                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             2050                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        43629                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        94802                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          132                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5995185                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               443145                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3161                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          74942742                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.773391                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.139188                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                64672921     86.30%     86.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  620255      0.83%     87.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  831184      1.11%     88.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1205105      1.61%     89.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1036791      1.38%     91.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  535666      0.71%     91.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1369144      1.83%     93.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  351637      0.47%     94.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4320039      5.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            74942742                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.030092                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.199048                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                16159158                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             47296340                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  9320957                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               457304                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1706877                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              946060                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                86144                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              54858013                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               286862                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1706877                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17095317                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               18544880                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      25731919                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8763106                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3098607                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              51692102                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 7152                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                482288                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2118635                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents              58                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           53768769                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            237295359                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       237252975                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            42384                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             37974901                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                15793867                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            403461                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        357400                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6244351                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9843526                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6693253                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           891235                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1110531                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  47673025                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             943085                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 60813772                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            81704                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10584682                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     28040387                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        237278                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     74942742                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.811470                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.521589                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           53203952     70.99%     70.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6663470      8.89%     79.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3519082      4.70%     84.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2892768      3.86%     88.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6218608      8.30%     96.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1439258      1.92%     98.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             735883      0.98%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             209954      0.28%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              59767      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       74942742                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  24319      0.56%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4142702     94.84%     95.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               201068      4.60%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           168088      0.28%      0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             28444166     46.77%     47.05% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46611      0.08%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  9      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           900      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.13% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            26040619     42.82%     89.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6113365     10.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              60813772                       # Type of FU issued
system.cpu1.iq.rate                          0.259674                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4368089                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.071827                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         201054983                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         59209073                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     41787342                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              10574                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              5911                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         4752                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              65008196                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   5577                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          302847                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2267035                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3168                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        14674                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       853664                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     16940133                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       457083                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1706877                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               13961840                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               229523                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           48721689                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            98782                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9843526                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6693253                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            669936                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 49642                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3791                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         14674                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        166878                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       133542                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              300420                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             59454145                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25635874                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1359627                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       105579                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31697240                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5530994                       # Number of branches executed
system.cpu1.iew.exec_stores                   6061366                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.253868                       # Inst execution rate
system.cpu1.iew.wb_sent                      58875000                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     41792094                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 22753184                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 41716740                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.178452                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.545421                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       10509796                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         705807                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           260176                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     73235865                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.516331                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.496791                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     59723279     81.55%     81.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6657456      9.09%     90.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1906988      2.60%     93.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1010218      1.38%     94.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       959564      1.31%     95.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       524950      0.72%     96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       702340      0.96%     97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       373722      0.51%     98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1377348      1.88%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     73235865                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            29175677                       # Number of instructions committed
system.cpu1.commit.committedOps              37813970                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13416080                       # Number of memory references committed
system.cpu1.commit.loads                      7576491                       # Number of loads committed
system.cpu1.commit.membars                     191234                       # Number of memory barriers committed
system.cpu1.commit.branches                   4755917                       # Number of branches committed
system.cpu1.commit.fp_insts                      4715                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 33570741                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              477112                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1377348                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   119309924                       # The number of ROB reads
system.cpu1.rob.rob_writes                   98406667                       # The number of ROB writes
system.cpu1.timesIdled                         873323                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      159250155                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2285809379                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   29104625                       # Number of Instructions Simulated
system.cpu1.committedOps                     37742918                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             29104625                       # Number of Instructions Simulated
system.cpu1.cpi                              8.046587                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.046587                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.124276                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.124276                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               269354983                       # number of integer regfile reads
system.cpu1.int_regfile_writes               42881539                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    22070                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   19722                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               14807942                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                402452                       # number of misc regfile writes
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192818443837                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83054                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------