path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.804583                       # Number of seconds simulated
sim_ticks                                2804582834000                       # Number of ticks simulated
final_tick                               2804582834000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 172391                       # Simulator instruction rate (inst/s)
host_op_rate                                   209235                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4135673798                       # Simulator tick rate (ticks/s)
host_mem_usage                                 633896                       # Number of bytes of host memory used
host_seconds                                   678.14                       # Real time elapsed on the host
sim_insts                                   116905819                       # Number of instructions simulated
sim_ops                                     141891765                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           685504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5035168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           692224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4774856                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11197032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       685504                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       692224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1377728                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8413760                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8431284                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10711                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             79193                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           67                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             74609                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175474                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131465                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               135846                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              244423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1795336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              246819                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1702519                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3992406                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         244423                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         246819                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             491242                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3000004                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6245                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3006252                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3000004                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1415                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             244423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1801581                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1529                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             246819                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1702522                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6998658                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175475                       # Number of read requests accepted
system.physmem.writeReqs                       135846                       # Number of write requests accepted
system.physmem.readBursts                      175475                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     135846                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11220480                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9920                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8444352                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11197096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8431284                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      155                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11302                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11252                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11256                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10710                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11532                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11381                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12180                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12061                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10232                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10264                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10575                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9266                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10585                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11349                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10873                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10502                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8422                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8567                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8697                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8116                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8443                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8487                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9141                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9034                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7740                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7663                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7868                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6935                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8081                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8671                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8304                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7774                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    2804582655500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174919                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131465                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103782                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61323                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1751                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64935                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      302.837730                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     178.379870                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.140175                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24467     37.68%     37.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15703     24.18%     61.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6760     10.41%     72.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3722      5.73%     78.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2848      4.39%     82.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1541      2.37%     84.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1091      1.68%     86.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1047      1.61%     88.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7756     11.94%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64935                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6659                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.328127                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      478.808129                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6657     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6659                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6659                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.814236                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.240992                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.368669                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                11      0.17%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 8      0.12%      0.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                5      0.08%      0.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               7      0.11%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5729     86.03%     86.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             143      2.15%     88.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              83      1.25%     89.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              58      0.87%     90.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             282      4.23%     95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              54      0.81%     95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              22      0.33%     96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.15%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              13      0.20%     96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               9      0.14%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.12%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.08%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             158      2.37%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               2      0.03%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               9      0.14%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.05%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             6      0.09%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.20%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6659                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2658321750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5945571750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    876600000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15162.68                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33912.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.00                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.99                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144869                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97458                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.86                       # Row buffer hit rate for writes
system.physmem.avgGap                      9008652.34                       # Average gap between requests
system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  258385680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  140984250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 715049400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                446517360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           183181277760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            78012609390                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1614313697250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1877068521090                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.287723                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2685462700000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     93650960000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     25469163500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  232522920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  126872625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 652438800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                408473280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           183181277760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            77055662610                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1615153124250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1876810372245                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.195678                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2686857596250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     93650960000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     24067808750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26563319                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13759388                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           495774                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            16214186                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8026564                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            49.503342                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6609603                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28316                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4513473                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           4401835                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          111638                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        31883                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    59132                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               59132                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17796                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14691                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        26645                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        32487                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   741.511989                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  4828.940187                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        32073     98.73%     98.73% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          302      0.93%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           58      0.18%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           24      0.07%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        32487                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12954                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13356.453605                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11053.395474                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  8313.507092                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         9693     74.83%     74.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         2999     23.15%     97.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          232      1.79%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535           12      0.09%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919            3      0.02%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303           11      0.08%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12954                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  80893447336                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.689246                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.490660                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  80809388336     99.90%     99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     57018000      0.07%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     12830500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      5059000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2818000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1843000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1116000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1980000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       463500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       218500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21       179500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        36500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       167500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        41000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        27000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31       261000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  80893447336                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3543     69.38%     69.38% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1564     30.62%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5107                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        59132                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        59132                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5107                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5107                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        64239                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13759364                       # DTB read hits
system.cpu0.dtb.read_misses                     49716                       # DTB read misses
system.cpu0.dtb.write_hits                   10256387                       # DTB write hits
system.cpu0.dtb.write_misses                     9416                       # DTB write misses
system.cpu0.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3461                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      822                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1317                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      673                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                13809080                       # DTB read accesses
system.cpu0.dtb.write_accesses               10265803                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24015751                       # DTB hits
system.cpu0.dtb.misses                          59132                       # DTB misses
system.cpu0.dtb.accesses                     24074883                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     7852                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7852                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2338                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4601                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          913                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         6939                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1482.922611                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  5881.501681                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6495     93.60%     93.60% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          232      3.34%     96.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          124      1.79%     98.73% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           39      0.56%     99.29% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           13      0.19%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           15      0.22%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343           10      0.14%     99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            3      0.04%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         6939                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3247                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12392.208192                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 10258.914411                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7404.792558                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191         1195     36.80%     36.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1373     42.29%     79.09% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          618     19.03%     98.12% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           36      1.11%     99.23% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           12      0.37%     99.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            8      0.25%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3247                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  29354741784                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.621127                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.485486                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    11126118428     37.90%     37.90% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    18225065856     62.09%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2842500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         576000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         139000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  29354741784                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1743     74.68%     74.68% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          591     25.32%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2334                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7852                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7852                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2334                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2334                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10186                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    19905461                       # ITB inst hits
system.cpu0.itb.inst_misses                      7852                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2294                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1258                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                19913313                       # ITB inst accesses
system.cpu0.itb.hits                         19905461                       # DTB hits
system.cpu0.itb.misses                           7852                       # DTB misses
system.cpu0.itb.accesses                     19913313                       # DTB accesses
system.cpu0.numPwrStateTransitions               3146                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1573                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    939647394.777495                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   18797497095.969948                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1537     97.71%     97.71% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10           33      2.10%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.06%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            2      0.13%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499976908600                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1573                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   1326517482015                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       106457732                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39778104                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     102329331                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26563319                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19038002                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     62116027                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3105600                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    111146                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                3723                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              374                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       142117                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       123224                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          483                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 19903626                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               349456                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   4039                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         103827961                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.185750                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.289369                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                75543673     72.76%     72.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3812816      3.67%     76.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2351525      2.26%     78.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 7978907      7.68%     86.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1585659      1.53%     87.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  993143      0.96%     88.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6063618      5.84%     94.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1017561      0.98%     95.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4481059      4.32%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           103827961                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.249520                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.961220                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27448350                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58255743                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15281337                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1431455                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1410775                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1819074                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               143809                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              84464795                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               475260                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1410775                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                28253865                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6710507                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      43964237                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 15899574                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7588686                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              80835076                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 4210                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1036846                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                275223                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               5569610                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           83235701                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            372775200                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        90140763                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             7010                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             70379825                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12855876                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1526723                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1432794                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8313035                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14557991                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11307773                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1955979                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2652434                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  77887971                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1057787                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 74749052                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            90659                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10605329                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23152649                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        112514                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    103827961                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.719932                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.414021                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           73906111     71.18%     71.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10009384      9.64%     80.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7640879      7.36%     88.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6355260      6.12%     94.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2281294      2.20%     96.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1454406      1.40%     97.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1486828      1.43%     99.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             476436      0.46%     99.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             217363      0.21%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      103827961                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  96059      8.82%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                522555     47.96%     56.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               470896     43.22%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2193      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             49733964     66.53%     66.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57150      0.08%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4360      0.01%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14140204     18.92%     85.54% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10811178     14.46%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              74749052                       # Type of FU issued
system.cpu0.iq.rate                          0.702148                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1089511                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014576                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         254491359                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         89595521                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     72529451                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              14876                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              8869                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6537                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              75828364                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   8006                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          352891                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2046517                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2081                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54500                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1025754                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       203183                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        83677                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1410775                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5864401                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               637976                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           79069756                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           107726                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14557991                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11307773                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            551458                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44492                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               582169                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54500                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        204607                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       218688                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              423295                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             74201167                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             13921134                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           488864                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       123998                       # number of nop insts executed
system.cpu0.iew.exec_refs                    24636404                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14031471                       # Number of branches executed
system.cpu0.iew.exec_stores                  10715270                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.697001                       # Inst execution rate
system.cpu0.iew.wb_sent                      73687563                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     72535988                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 37714943                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 65670191                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.681360                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.574308                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10562082                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         945273                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           353712                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    101401288                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.674752                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.564672                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     74703091     73.67%     73.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12065534     11.90%     85.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6043146      5.96%     91.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2565114      2.53%     94.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1263406      1.25%     95.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       840623      0.83%     96.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1825870      1.80%     97.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       394429      0.39%     98.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1700075      1.68%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    101401288                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            56174796                       # Number of instructions committed
system.cpu0.commit.committedOps              68420730                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      22793493                       # Number of memory references committed
system.cpu0.commit.loads                     12511474                       # Number of loads committed
system.cpu0.commit.membars                     380410                       # Number of memory barriers committed
system.cpu0.commit.branches                  13308961                       # Number of branches committed
system.cpu0.commit.fp_insts                      6093                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 59905864                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2612225                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        45567261     66.60%     66.60% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55619      0.08%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4357      0.01%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12511474     18.29%     84.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10282019     15.03%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         68420730                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1700075                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   166296828                       # The number of ROB reads
system.cpu0.rob.rob_writes                  160391499                       # The number of ROB writes
system.cpu0.timesIdled                         400345                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2629771                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2956130676                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   56094495                       # Number of Instructions Simulated
system.cpu0.committedOps                     68340429                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.897829                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.897829                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.526918                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.526918                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                80764362                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46165163                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    17106                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13230                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                262463335                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27226302                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              188101438                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                725062                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           852281                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.984445                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42339308                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           852793                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.647814                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         92671500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.071418                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.913027                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359514                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.640455                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189174355                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189174355                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     12233622                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12935174                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25168796                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7652789                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8245651                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15898440                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177697                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       185293                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       362990                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209982                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236483                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446465                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216319                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243020                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459339                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     19886411                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21180825                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41067236                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20064108                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21366118                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41430226                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       399335                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       433156                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       832491                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1953724                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1746335                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3700059                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        79458                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       104494                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183952                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13729                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14031                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27760                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           50                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           43                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           93                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2353059                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2179491                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4532550                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2432517                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2283985                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4716502                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5993164000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6602742500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12595906500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  87678812214                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  78129188370                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 165808000584                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    179748500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    207520500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    387269000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      1029000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       788500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1817500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  93671976214                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  84731930870                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 178403907084                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  93671976214                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  84731930870                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 178403907084                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12632957                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13368330                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26001287                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9606513                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9991986                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19598499                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       257155                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       289787                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       546942                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223711                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250514                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474225                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216369                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243063                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459432                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22239470                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23360316                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45599786                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22496625                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23650103                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46146728                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031611                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032402                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032017                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.203375                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174774                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188793                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.308989                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.360589                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336328                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061369                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056009                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058538                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000231                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000177                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000202                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105806                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093299                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099398                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108128                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096574                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102207                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15007.860568                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15243.336119                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15130.381590                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44877.788374                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44738.946634                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44812.258557                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13092.614174                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14790.143254                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13950.612392                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        20580                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18337.209302                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19543.010753                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.596475                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 38876.935427                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39360.604314                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38508.251418                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37098.286928                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37825.470462                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1131320                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       188861                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            53104                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2863                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.303857                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    65.966119                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       702476                       # number of writebacks
system.cpu0.dcache.writebacks::total           702476                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       189142                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       219525                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       408667                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1797272                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1603201                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3400473                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9446                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9040                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18486                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1986414                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1822726                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3809140                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1986414                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1822726                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3809140                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210193                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       213631                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       423824                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156452                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143134                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299586                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55184                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        67813                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122997                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4283                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4991                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9274                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           50                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           43                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           93                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       366645                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       356765                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       723410                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       421829                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       424578                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       846407                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16364                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14763                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15955                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11629                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32319                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2996485500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3091984000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6088469500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7303847372                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6679350930                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13983198302                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    775558500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    966595500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1742154000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     55534500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     83841500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    139376000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       979000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       745500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1724500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10300332872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9771334930                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  20071667802                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11075891372                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10737930430                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  21813821802                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3308436000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2995791000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6304227000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3308436000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2995791000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6304227000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016638                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015980                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016300                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016286                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014325                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015286                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.214594                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.234010                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224881                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019145                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019923                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019556                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000231                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000177                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000202                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016486                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015272                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015864                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018751                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017952                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018342                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14255.876742                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14473.479972                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14365.560940                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46684.269757                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46665.019702                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46675.072607                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14054.046463                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14253.837760                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14164.199127                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12966.261966                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16798.537367                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.682338                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        19580                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17337.209302                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18543.010753                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28093.476993                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27388.715065                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.908685                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26256.827700                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.830966                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25772.260629                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202177.707162                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.624873                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202532.431651                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102368.142579                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.329191                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107377.271721                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1934770                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.556955                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38706180                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1935282                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.000279                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9780443500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   231.259013                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   280.297942                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.451678                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.547457                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999135                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          224                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42724671                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42724671                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     18869611                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19836569                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38706180                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     18869611                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19836569                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38706180                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     18869611                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19836569                       # number of overall hits
system.cpu0.icache.overall_hits::total       38706180                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1033343                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1049727                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2083070                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1033343                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1049727                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2083070                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1033343                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1049727                       # number of overall misses
system.cpu0.icache.overall_misses::total      2083070                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14011205485                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14271764988                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28282970473                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14011205485                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14271764988                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28282970473                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14011205485                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14271764988                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28282970473                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     19902954                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20886296                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40789250                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     19902954                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20886296                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40789250                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     19902954                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20886296                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40789250                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051919                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050259                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051069                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051919                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050259                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051069                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051919                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050259                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051069                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.104271                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.692011                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.542028                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.104271                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.692011                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13577.542028                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.104271                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.692011                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13577.542028                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        12666                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              637                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.883830                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1934770                       # number of writebacks
system.cpu0.icache.writebacks::total          1934770                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71468                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76180                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       147648                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71468                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76180                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       147648                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71468                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76180                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       147648                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       961875                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       973547                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1935422                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       961875                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       973547                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1935422                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       961875                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       973547                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1935422                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12392823488                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12603228992                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  24996052480                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12392823488                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12603228992                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  24996052480                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12392823488                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12603228992                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  24996052480                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048328                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046612                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047449                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048328                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046612                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047449                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048328                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046612                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047449                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.027018                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12945.681094                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.039965                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.027018                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12945.681094                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.039965                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.027018                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12945.681094                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.039965                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171                       # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups               27800734                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14468017                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           520264                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17357855                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                8537221                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            49.183617                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6851276                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             30109                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4615749                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           4505317                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          110432                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        32773                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    58704                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58704                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18787                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14342                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25575                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33129                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   607.488907                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3928.944060                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32763     98.90%     98.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          284      0.86%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           53      0.16%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           14      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919            9      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33129                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        12929                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13107.123521                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.290186                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7818.028410                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         3814     29.50%     29.50% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         6003     46.43%     75.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2605     20.15%     96.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          277      2.14%     98.22% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959          121      0.94%     99.16% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           97      0.75%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            6      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        12929                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  90162765428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.682767                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.486580                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  90084509428     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     54607500      0.06%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     11537000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4308000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2626500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1272000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       860000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      1827500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       362000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       169500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21       127500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23       189000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       278500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        31000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29         4000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31        56000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  90162765428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3736     69.71%     69.71% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1623     30.29%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5359                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58704                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58704                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        64063                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14569453                       # DTB read hits
system.cpu1.dtb.read_misses                     50573                       # DTB read misses
system.cpu1.dtb.write_hits                   10639861                       # DTB write hits
system.cpu1.dtb.write_misses                     8131                       # DTB write misses
system.cpu1.dtb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     472                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3396                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      805                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1145                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      620                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14620026                       # DTB read accesses
system.cpu1.dtb.write_accesses               10647992                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25209314                       # DTB hits
system.cpu1.dtb.misses                          58704                       # DTB misses
system.cpu1.dtb.accesses                     25268018                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     7547                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7547                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2262                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4445                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          840                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         6707                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1590.577009                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  7723.778790                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-16383         6530     97.36%     97.36% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-32767          110      1.64%     99.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-49151           34      0.51%     99.51% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-65535           14      0.21%     99.72% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-81919            4      0.06%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-98303            4      0.06%     99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-114687            4      0.06%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::114688-131071            3      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-147455            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::147456-163839            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-180223            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         6707                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         3150                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12187.460317                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9947.804489                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8166.759001                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         2468     78.35%     78.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          654     20.76%     99.11% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-49151           23      0.73%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-65535            4      0.13%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::180224-196607            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         3150                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  25738120488                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.844814                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.363091                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     3999711376     15.54%     15.54% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    21735062612     84.45%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2190000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         624000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         246500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         151000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6          78500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::7          56500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  25738120488                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1735     75.11%     75.11% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          575     24.89%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2310                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7547                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7547                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2310                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2310                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         9857                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20888873                       # ITB inst hits
system.cpu1.itb.inst_misses                      7547                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     472                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2235                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1381                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20896420                       # ITB inst accesses
system.cpu1.itb.hits                         20888873                       # DTB hits
system.cpu1.itb.misses                           7547                       # DTB misses
system.cpu1.itb.accesses                     20896420                       # DTB accesses
system.cpu1.numPwrStateTransitions               2930                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         1465                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    831651178.963822                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   15817593716.503048                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1430     97.61%     97.61% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10           32      2.18%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.07%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.07%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 499953823748                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           1465                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   1586213856818                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218368977182                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       109807766                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40946708                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108526504                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27800734                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19893814                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     64236038                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3213549                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    105759                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7245                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              373                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       135453                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       122613                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          242                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20886297                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               363278                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3848                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         107161169                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.215637                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.316725                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                77416464     72.24%     72.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3965095      3.70%     75.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2490829      2.32%     78.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8243361      7.69%     85.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1613956      1.51%     87.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1187147      1.11%     88.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6283757      5.86%     94.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1186298      1.11%     95.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4774262      4.46%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           107161169                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.253176                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.988332                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27964353                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             60068615                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15897753                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1769475                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1460665                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             2003148                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               148026                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              90335872                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               490325                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1460665                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28918939                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                5241732                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      47181148                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16705614                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              7652719                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              86492691                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2006                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1748729                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                211009                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               4894541                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           89713841                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            398185196                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        96380963                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6166                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             76287775                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13426050                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1604503                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1503333                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10223805                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15401006                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11773081                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2213053                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2955194                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  83360447                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1152123                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 80030097                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91651                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10961230                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24699895                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        103564                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    107161169                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.746820                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.429737                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           74988145     69.98%     69.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10859318     10.13%     80.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8183119      7.64%     87.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6800302      6.35%     94.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2507101      2.34%     96.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1554442      1.45%     97.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1528270      1.43%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             490375      0.46%     99.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             250097      0.23%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      107161169                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 115126      9.98%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     7      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                527227     45.72%     55.70% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               510910     44.30%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              144      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             53746905     67.16%     67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59075      0.07%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              3      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4215      0.01%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14959094     18.69%     85.93% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11260652     14.07%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              80030097                       # Type of FU issued
system.cpu1.iq.rate                          0.728820                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1153270                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014410                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268452912                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         95516318                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     77725340                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              13372                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7575                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5790                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              81175982                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7241                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          353102                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2112683                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         1972                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51148                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1017197                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       193348                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       111717                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1460665                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4238159                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               750598                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           84630100                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           109084                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15401006                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11773081                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            582386                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44757                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               693078                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51148                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        222492                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       227539                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              450031                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             79465930                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14732483                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           505630                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       117530                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25895547                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14804111                       # Number of branches executed
system.cpu1.iew.exec_stores                  11163064                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.723682                       # Inst execution rate
system.cpu1.iew.wb_sent                      78901102                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     77731130                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 41032213                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 71725825                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.707884                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.572070                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       10989958                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1048559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           374118                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    104645735                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.703573                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.592319                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     76040779     72.66%     72.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12759216     12.19%     84.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6569138      6.28%     91.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2748147      2.63%     93.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1448865      1.38%     95.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       932135      0.89%     96.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1856823      1.77%     97.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       438122      0.42%     98.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1852510      1.77%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    104645735                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            60885928                       # Number of instructions committed
system.cpu1.commit.committedOps              73625940                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      24044207                       # Number of memory references committed
system.cpu1.commit.loads                     13288323                       # Number of loads committed
system.cpu1.commit.membars                     433821                       # Number of memory barriers committed
system.cpu1.commit.branches                  14065730                       # Number of branches committed
system.cpu1.commit.fp_insts                      5335                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 64521424                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2723504                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        49520111     67.26%     67.26% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57410      0.08%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4212      0.01%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13288323     18.05%     85.39% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10755884     14.61%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         73625940                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1852510                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   174677688                       # The number of ROB reads
system.cpu1.rob.rob_writes                  171746746                       # The number of ROB writes
system.cpu1.timesIdled                         397244                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2646597                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2436737930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   60811324                       # Number of Instructions Simulated
system.cpu1.committedOps                     73551336                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.805712                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.805712                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.553798                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.553798                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                86399425                       # number of integer regfile reads
system.cpu1.int_regfile_writes               49556939                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16634                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13036                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                280643076                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29716175                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              196047925                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                794523                       # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49488500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               336500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               631000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               20000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6430000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38405500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187814627                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36409                       # number of replacements
system.iocache.tags.tagsinuse                0.981814                       # Cycle average of tags in use
system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234298498000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.981814                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.061363                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.061363                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
system.iocache.tags.data_accesses              328227                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
system.iocache.demand_hits::total                  29                       # number of demand (read+write) hits
system.iocache.overall_hits::realview.ide           29                       # number of overall hits
system.iocache.overall_hits::total                 29                       # number of overall hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
system.iocache.overall_misses::total            36444                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31228377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31228377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4281194250                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4281194250                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4312422627                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4312422627                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4312422627                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4312422627                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36473                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36473                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36473                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36473                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide     0.999205                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 125415.168675                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125415.168675                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118281.371736                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118281.371736                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118330.112693                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118330.112693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118330.112693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118330.112693                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            93                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs           93                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36160                       # number of writebacks
system.iocache.writebacks::total                36160                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36444                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18778377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18778377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2469323520                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2469323520                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2488101897                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2488101897                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2488101897                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2488101897                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.999205                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.999205                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75415.168675                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75415.168675                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68222.779942                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68222.779942                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68271.921222                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68271.921222                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68271.921222                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   104354                       # number of replacements
system.l2c.tags.tagsinuse                65128.327411                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5134678                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169609                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.273618                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   49028.421881                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.557435                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000253                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4778.981543                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2180.199494                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    47.031154                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5874.260795                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3173.874857                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.748114                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000695                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.072921                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.033267                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000718                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.089634                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.048429                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993779                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65177                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           78                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3224                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8984                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52582                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001190                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994522                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45398834                       # Number of tag accesses
system.l2c.tags.data_accesses                45398834                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker        35730                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6852                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36375                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6496                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85453                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       702476                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          702476                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1895131                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1895131                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              78                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              55                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 133                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            35                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                69                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            82259                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            74230                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156489                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        951585                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        962532                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1914117                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       262545                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       278213                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           540758                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         35730                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6852                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              951585                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              344804                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36375                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6496                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              962532                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              352443                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2696817                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        35730                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6852                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             951585                       # number of overall hits
system.l2c.overall_hits::cpu0.data             344804                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36375                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6496                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             962532                       # number of overall hits
system.l2c.overall_hits::cpu1.data             352443                       # number of overall hits
system.l2c.overall_hits::total                2696817                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           62                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           67                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  130                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1433                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1300                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2733                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           16                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            8                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              24                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          72695                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          67565                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140260                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        10064                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10823                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20887                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         7102                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         8206                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15308                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           62                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             10064                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             79797                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           67                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10823                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             75771                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176585                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           62                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            10064                       # number of overall misses
system.l2c.overall_misses::cpu0.data            79797                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           67                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10823                       # number of overall misses
system.l2c.overall_misses::cpu1.data            75771                       # number of overall misses
system.l2c.overall_misses::total               176585                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5759000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5729000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       11571500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       494500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       471000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       965500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       285000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       200000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       485000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6150345000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5634905000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11785250000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst    832598498                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    909265000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1741863498                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    619097000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    739733000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1358830000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5759000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    832598498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6769442000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5729000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    909265000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6374638000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     14897514998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5759000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    832598498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6769442000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5729000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    909265000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6374638000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    14897514998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        35792                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6853                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36442                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6496                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              85583                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       702476                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       702476                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1895131                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1895131                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1511                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1355                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2866                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           50                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           43                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            93                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       154954                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       141795                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296749                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       961649                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       973355                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1935004                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       269647                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       286419                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       556066                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        35792                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6853                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          961649                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          424601                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36442                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6496                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          973355                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          428214                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2873402                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        35792                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6853                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         961649                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         424601                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36442                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6496                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         973355                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         428214                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2873402                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001732                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001839                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001519                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.948379                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.959410                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.953594                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.320000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.186047                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.258065                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.469139                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.476498                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472655                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010465                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011119                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010794                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.026338                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.028650                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027529                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001732                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010465                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.187934                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001839                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.176947                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061455                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001732                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010465                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.187934                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001839                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.176947                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061455                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 89011.538462                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   345.080251                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   362.307692                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   353.274790                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17812.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        25000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 20208.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84604.787124                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83399.763191                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84024.311992                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82730.375397                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84012.288645                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 83394.623354                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87172.205013                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90145.381428                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 88766.004703                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82730.375397                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 84833.289472                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84012.288645                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84130.313708                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 84364.555302                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82730.375397                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 84833.289472                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84012.288645                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84130.313708                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 84364.555302                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               95305                       # number of writebacks
system.l2c.writebacks::total                    95305                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           74                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           66                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          140                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             66                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                152                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            74                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            66                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               152                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           62                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           67                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             130                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1433                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1300                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2733                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           16                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           24                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        72695                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        67565                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140260                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10058                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10817                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20875                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         7028                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         8140                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15168                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        10058                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        79723                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           67                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10817                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        75705                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176433                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           62                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        10058                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        79723                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           67                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10817                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        75705                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176433                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16364                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14763                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31794                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15955                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11629                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32319                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59378                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     10271500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27285000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     24739000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     52024000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       360000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       208500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       568500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5423395000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4959255000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10382650000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    731721998                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    800800501                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1532522499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    543441001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    653257500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1196698501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    731721998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5966836001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    800800501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5612512500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  13122142500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    731721998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5966836001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    800800501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5612512500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  13122142500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3103826000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2811200500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5958129998                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3103826000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2811200500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5958129998                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001732                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001839                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001519                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.948379                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.959410                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.953594                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.320000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.186047                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.258065                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.469139                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.476498                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472655                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010459                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011113                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010788                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.026064                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.028420                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027277                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001732                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010459                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.187760                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001839                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011113                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.176792                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061402                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001732                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010459                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.187760                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001839                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011113                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.176792                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061402                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 79011.538462                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19040.474529                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19030                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19035.492133                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        22500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 26062.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23687.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74604.787124                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73399.763191                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 74024.311992                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72750.248360                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74031.663215                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73414.251449                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77325.128201                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80252.764128                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78896.261933                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72750.248360                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74844.599438                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74031.663215                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74136.615811                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 74374.649300                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72750.248360                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74844.599438                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74031.663215                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74136.615811                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 74374.649300                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189674.040577                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190422.034817                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.936655                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96037.191745                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106517.145347                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.382667                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        356405                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       150205                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               31794                       # Transaction distribution
system.membus.trans_dist::ReadResp              68215                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131465                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9298                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4631                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             24                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138363                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138363                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36422                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468976                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       576548                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 649416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17313116                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17477149                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19792349                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              523                       # Total snoops (count)
system.membus.snoop_fanout::samples            275014                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019224                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.137313                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  269727     98.08%     98.08% # Request fanout histogram
system.membus.snoop_fanout::1                    5287      1.92%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              275014                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95656500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1704498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           922039711                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1008874750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1321623                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      5615551                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2827345                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        47668                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            189                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804582834000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq             149135                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2640787                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       797781                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1934770                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          158854                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2867                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            93                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2959                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296749                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296749                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1935422                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       556302                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4761                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5806529                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2681416                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        36041                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166883                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8690869                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247708160                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99732253                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        53396                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       288936                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              347782745                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          141693                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3081386                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027688                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.164077                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2996069     97.23%     97.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  85317      2.77%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3081386                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5532635383                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           308377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2905951347                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1326155926                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          22725930                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          95104578                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------