path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.804580                       # Number of seconds simulated
sim_ticks                                2804580230500                       # Number of ticks simulated
final_tick                               2804580230500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 127171                       # Simulator instruction rate (inst/s)
host_op_rate                                   154351                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3050845926                       # Simulator tick rate (ticks/s)
host_mem_usage                                 593120                       # Number of bytes of host memory used
host_seconds                                   919.28                       # Real time elapsed on the host
sim_insts                                   116905819                       # Number of instructions simulated
sim_ops                                     141891765                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           685504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5032416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           692288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4777544                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11197032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       685504                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       692288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1377792                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8414016                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8431540                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10711                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             79150                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           67                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10817                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             74651                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175474                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131469                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               135850                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              244423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1794356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              246842                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1703479                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3992409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         244423                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         246842                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             491265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3000098                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6245                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3006347                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3000098                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1415                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             244423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1800602                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1529                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             246842                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1703482                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6998756                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175475                       # Number of read requests accepted
system.physmem.writeReqs                       135850                       # Number of write requests accepted
system.physmem.readBursts                      175475                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     135850                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11220480                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9920                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8444544                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11197096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8431540                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      155                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11302                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11253                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11257                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10711                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11530                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11380                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12179                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12059                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10232                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10264                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10576                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9268                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10585                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11349                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10873                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10502                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8422                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8567                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8697                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8117                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8443                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8487                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9140                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9032                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7740                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7663                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7869                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6937                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8081                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8671                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8306                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7774                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    2804580052000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174919                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131469                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103792                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8442                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1749                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4635                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8260                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      302.859343                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     178.384089                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.204668                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24461     37.67%     37.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15710     24.19%     61.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6774     10.43%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3704      5.70%     78.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2837      4.37%     82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1544      2.38%     84.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1096      1.69%     86.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1046      1.61%     88.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7759     11.95%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64931                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6660                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.324024                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      478.772149                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6658     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6660                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6660                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.811712                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.241865                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.351487                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                11      0.17%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 8      0.12%      0.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                5      0.08%      0.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               7      0.11%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5729     86.02%     86.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             144      2.16%     88.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              82      1.23%     89.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              58      0.87%     90.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             282      4.23%     94.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              56      0.84%     95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              22      0.33%     96.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.15%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              13      0.20%     96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               9      0.14%     96.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.12%     96.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.08%     96.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             158      2.37%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.02%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               9      0.14%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.05%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             6      0.09%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.20%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6660                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2657846750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5945096750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    876600000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15159.97                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33909.97                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.00                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.99                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144865                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97469                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.86                       # Row buffer hit rate for writes
system.physmem.avgGap                      9008528.23                       # Average gap between requests
system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  258347880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  140963625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 715026000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                446504400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           183181277760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            78001831260                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1614323151750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1877067102675                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.287218                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2685476419500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     93650960000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     25452840500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  232530480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  126876750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 652462200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                408505680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           183181277760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            77069277630                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1615141181250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1876812111750                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.196298                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2686837815500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     93650960000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     24087589500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26564246                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13760083                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           495819                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            16217384                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8027247                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            49.497792                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6609804                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28343                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4513554                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           4401782                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          111772                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        31942                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    58733                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               58733                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17793                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14688                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        26252                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        32481                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   736.907731                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  4817.272185                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        32071     98.74%     98.74% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          298      0.92%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           58      0.18%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           24      0.07%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        32481                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12836                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13407.876285                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11117.462243                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  8301.375847                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         9572     74.57%     74.57% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3010     23.45%     98.02% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          224      1.75%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535           12      0.09%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919            3      0.02%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303           11      0.09%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12836                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  80896428336                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.690430                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.489717                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  80813150336     99.90%     99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     56853500      0.07%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     12740500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4914000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2520000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1766000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1127000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1985000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       442000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       216500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21       182000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        37500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       158000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        42500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        16500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31       277000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  80896428336                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3537     69.35%     69.35% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1563     30.65%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5100                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58733                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58733                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5100                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5100                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        63833                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13760624                       # DTB read hits
system.cpu0.dtb.read_misses                     49633                       # DTB read misses
system.cpu0.dtb.write_hits                   10257954                       # DTB write hits
system.cpu0.dtb.write_misses                     9100                       # DTB write misses
system.cpu0.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3389                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      823                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1310                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      671                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                13810257                       # DTB read accesses
system.cpu0.dtb.write_accesses               10267054                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24018578                       # DTB hits
system.cpu0.dtb.misses                          58733                       # DTB misses
system.cpu0.dtb.accesses                     24077311                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     7862                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7862                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2332                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4618                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          912                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         6950                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1524.460432                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  6004.169915                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6494     93.44%     93.44% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          241      3.47%     96.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          125      1.80%     98.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           34      0.49%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           18      0.26%     99.45% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           15      0.22%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343           11      0.16%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            4      0.06%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         6950                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3241                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12408.053070                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 10260.895484                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7472.988391                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191         1196     36.90%     36.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1364     42.09%     78.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          617     19.04%     98.03% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           36      1.11%     99.14% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           13      0.40%     99.54% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            9      0.28%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            4      0.12%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3241                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  29351792784                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.620704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.485614                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    11137583928     37.95%     37.95% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    18210652356     62.04%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2700500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         701500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         154500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  29351792784                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1739     74.67%     74.67% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          590     25.33%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2329                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7862                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7862                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2329                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2329                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10191                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    19906259                       # ITB inst hits
system.cpu0.itb.inst_misses                      7862                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     445                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2225                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1249                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                19914121                       # ITB inst accesses
system.cpu0.itb.hits                         19906259                       # DTB hits
system.cpu0.itb.misses                           7862                       # DTB misses
system.cpu0.itb.accesses                     19914121                       # DTB accesses
system.cpu0.numPwrStateTransitions               3146                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1573                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    939647394.777495                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   18797497095.969948                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1537     97.71%     97.71% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10           33      2.10%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.06%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            2      0.13%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499976908600                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1573                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   1326514878515                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       106457810                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39783272                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     102334432                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26564246                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19038833                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     62110443                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3105656                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    111244                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                3727                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              375                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       142235                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       122947                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          487                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 19904431                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               349445                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   4054                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         103827521                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.185827                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.289430                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                75541763     72.76%     72.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3812950      3.67%     76.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2351578      2.26%     78.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 7979154      7.69%     86.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1585790      1.53%     87.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  993286      0.96%     88.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6064061      5.84%     94.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1017530      0.98%     95.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4481409      4.32%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           103827521                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.249528                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.961267                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27452745                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58249830                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15282230                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1431597                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1410818                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1819259                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               143809                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              84470520                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               475057                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1410818                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                28258375                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6709685                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      43965251                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 15900516                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7582559                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              80840782                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 4307                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1036576                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                275166                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               5563712                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           83242060                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            372803118                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        90148302                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             7047                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             70383329                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12858731                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1526779                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1432825                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8314563                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14558964                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11309450                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1956443                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2653694                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  77893392                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1057864                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 74754554                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            90317                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10606810                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23150954                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        112541                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    103827521                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.719988                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.414103                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           73904134     71.18%     71.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10009837      9.64%     80.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7641807      7.36%     88.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6354760      6.12%     94.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2280701      2.20%     96.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1455227      1.40%     97.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1486959      1.43%     99.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             476638      0.46%     99.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             217458      0.21%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      103827521                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  96078      8.82%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                523068     47.99%     56.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               470781     43.19%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2193      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             49737115     66.53%     66.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57140      0.08%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4360      0.01%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14141290     18.92%     85.54% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10812453     14.46%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              74754554                       # Type of FU issued
system.cpu0.iq.rate                          0.702199                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1089928                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014580                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         254501968                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         89602389                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     72535350                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              14906                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              8959                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6549                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              75834268                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   8021                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          353131                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2046839                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2065                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54488                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1026130                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       203254                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        83583                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1410818                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5863644                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               637671                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           79075081                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           107625                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14558964                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11309450                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            551514                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44441                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               581945                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54488                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        204716                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       218656                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              423372                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             74207157                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             13922405                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           488771                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       123825                       # number of nop insts executed
system.cpu0.iew.exec_refs                    24639289                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14032526                       # Number of branches executed
system.cpu0.iew.exec_stores                  10716884                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.697057                       # Inst execution rate
system.cpu0.iew.wb_sent                      73693634                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     72541899                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 37717472                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 65674853                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.681415                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.574306                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10563486                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         945323                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           353772                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    101400754                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.674795                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.564695                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     74701679     73.67%     73.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12064783     11.90%     85.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6043507      5.96%     91.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2566010      2.53%     94.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1263544      1.25%     95.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       840996      0.83%     96.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1825672      1.80%     97.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       394773      0.39%     98.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1699790      1.68%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    101400754                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            56177531                       # Number of instructions committed
system.cpu0.commit.committedOps              68424746                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      22795445                       # Number of memory references committed
system.cpu0.commit.loads                     12512125                       # Number of loads committed
system.cpu0.commit.membars                     380426                       # Number of memory barriers committed
system.cpu0.commit.branches                  13309453                       # Number of branches committed
system.cpu0.commit.fp_insts                      6093                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 59909497                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2612274                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        45569326     66.60%     66.60% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55618      0.08%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4357      0.01%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12512125     18.29%     84.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10283320     15.03%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         68424746                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1699790                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   166301969                       # The number of ROB reads
system.cpu0.rob.rob_writes                  160402388                       # The number of ROB writes
system.cpu0.timesIdled                         400481                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2630289                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2956130676                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   56097231                       # Number of Instructions Simulated
system.cpu0.committedOps                     68344446                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.897737                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.897737                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.526943                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.526943                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                80771254                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46168447                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    17119                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13230                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                262483574                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27229221                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              188104262                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                725122                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           852281                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.984445                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42339944                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           852793                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.648559                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         92671500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.072113                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.912332                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359516                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.640454                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189174351                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189174351                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     12234598                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12933985                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25168583                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7653509                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8245795                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15899304                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177729                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       185261                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       362990                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210001                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236455                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446456                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216327                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243012                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459339                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     19888107                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21179780                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41067887                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20065836                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21365041                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41430877                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       399294                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       433443                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       832737                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1954214                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1744981                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3699195                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        79447                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       104479                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183926                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13728                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14033                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27761                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           50                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           43                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           93                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2353508                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2178424                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4531932                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2432955                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2282903                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4715858                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5995822000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6613305000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12609127000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  87564281292                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  78191889675                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 165756170967                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    179746000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    207586500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    387332500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      1029000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       788500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1817500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  93560103292                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  84805194675                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 178365297967                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  93560103292                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  84805194675                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 178365297967                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12633892                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13367428                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26001320                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9607723                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9990776                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19598499                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       257176                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       289740                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       546916                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223729                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250488                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474217                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216377                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243055                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459432                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22241615                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23358204                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45599819                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22498791                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23647944                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46146735                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031605                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032425                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032027                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.203400                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174659                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188749                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.308921                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.360596                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336297                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061360                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056023                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058541                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000231                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000177                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000202                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105816                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093262                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099385                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108137                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096537                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102193                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15016.058343                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15257.611727                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15141.787863                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44807.928554                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44809.593729                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44808.714049                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13093.385781                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14792.738545                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13952.397248                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        20580                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18337.209302                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19543.010753                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39753.467289                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 38929.609055                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39357.452399                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38455.336532                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37147.962342                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37822.448845                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1130917                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       188980                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            52756                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2865                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.436747                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    65.961606                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       702484                       # number of writebacks
system.cpu0.dcache.writebacks::total           702484                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       189081                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       219808                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       408889                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1797716                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1601889                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3399605                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9443                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9044                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18487                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1986797                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1821697                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3808494                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1986797                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1821697                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3808494                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210213                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       213635                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       423848                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156498                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143092                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299590                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55178                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        67787                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122965                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4989                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9274                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           50                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           43                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           93                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       366711                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       356727                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       723438                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       421889                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       424514                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       846403                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16364                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14763                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15955                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11629                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32319                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2997028500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3092354500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6089383000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7297289872                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6685283941                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13982573813                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    775081500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    964984500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1740066000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     55558500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     83818500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    139377000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       979000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       745500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1724500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10294318372                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9777638441                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  20071956813                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11069399872                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10742622941                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  21812022813                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3308422500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2995783000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6304205500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3308422500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2995783000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6304205500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016639                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015982                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016301                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016289                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014322                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015286                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.214553                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.233958                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224833                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019153                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019917                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019556                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000231                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000177                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000202                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016488                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015272                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015865                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018752                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017951                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018342                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14257.103509                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14474.943244                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14366.902758                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46628.646194                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46720.179612                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46672.364942                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14046.929936                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14235.539263                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14150.904729                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12965.810968                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16800.661455                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.790166                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        19580                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17337.209302                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18543.010753                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28072.019579                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27409.303027                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.234302                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26237.706771                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25305.697671                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25770.256973                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202176.882180                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.082978                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.740932                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102367.724868                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.026069                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.905520                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1934891                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.556955                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38705762                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1935403                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            19.998813                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9780443500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   231.260597                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   280.296358                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.451681                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.547454                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999135                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42724437                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42724437                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     18870227                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19835535                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38705762                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     18870227                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19835535                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38705762                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     18870227                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19835535                       # number of overall hits
system.cpu0.icache.overall_hits::total       38705762                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1033532                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1049601                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2083133                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1033532                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1049601                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2083133                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1033532                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1049601                       # number of overall misses
system.cpu0.icache.overall_misses::total      2083133                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14014676985                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14269854487                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28284531472                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14014676985                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14269854487                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28284531472                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14014676985                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14269854487                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28284531472                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     19903759                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20885136                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40788895                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     19903759                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20885136                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40788895                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     19903759                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20885136                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40788895                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051926                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050256                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051071                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051926                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050256                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051071                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051926                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050256                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051071                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.983614                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.503898                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.880756                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.983614                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.503898                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13577.880756                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.983614                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.503898                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13577.880756                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        12686                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              639                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.852895                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1934891                       # number of writebacks
system.cpu0.icache.writebacks::total          1934891                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71394                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76196                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       147590                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71394                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76196                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       147590                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71394                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76196                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       147590                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       962138                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       973405                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1935543                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       962138                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       973405                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1935543                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       962138                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       973405                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1935543                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12396442988                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12601714991                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  24998157979                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12396442988                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12601714991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  24998157979                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12396442988                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12601714991                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  24998157979                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048340                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046608                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047453                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048340                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046608                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047453                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048340                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046608                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047453                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.267109                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12946.014240                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.320393                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.267109                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12946.014240                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.320393                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.267109                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12946.014240                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.320393                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171                       # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups               27798523                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14466350                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           520194                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17356776                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                8536168                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            49.180608                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6850987                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             30102                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4615656                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           4505334                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          110322                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        32790                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    58687                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58687                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18789                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14348                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25550                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33137                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   617.587591                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3984.391967                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32762     98.87%     98.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          289      0.87%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           55      0.17%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           15      0.05%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33137                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        12948                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13117.547112                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.155685                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7835.700834                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         3825     29.54%     29.54% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5982     46.20%     75.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2634     20.34%     96.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          274      2.12%     98.20% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959          123      0.95%     99.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           98      0.76%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            6      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        12948                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  90160170928                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.682736                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.486637                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  90081870928     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     54780000      0.06%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     11436000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4223000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2627000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1276500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       880500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      1864000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       368000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       150000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21       136000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23       188500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       289500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        30000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29         3500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31        47500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  90160170928                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3742     69.76%     69.76% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1622     30.24%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5364                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58687                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58687                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5364                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5364                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        64051                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14568202                       # DTB read hits
system.cpu1.dtb.read_misses                     50557                       # DTB read misses
system.cpu1.dtb.write_hits                   10638746                       # DTB write hits
system.cpu1.dtb.write_misses                     8130                       # DTB write misses
system.cpu1.dtb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     472                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3340                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      811                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1147                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      622                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14618759                       # DTB read accesses
system.cpu1.dtb.write_accesses               10646876                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25206948                       # DTB hits
system.cpu1.dtb.misses                          58687                       # DTB misses
system.cpu1.dtb.accesses                     25265635                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     7567                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7567                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2268                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4460                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          839                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         6728                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1599.137931                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  7818.499814                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-16383         6550     97.35%     97.35% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-32767          110      1.63%     98.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-49151           34      0.51%     99.49% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-65535           14      0.21%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-81919            4      0.06%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-98303            4      0.06%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-114687            5      0.07%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::114688-131071            3      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-147455            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::147456-163839            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-180223            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         6728                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         3154                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12204.343691                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9955.063689                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8183.561503                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         2464     78.12%     78.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          661     20.96%     99.08% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-49151           24      0.76%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-65535            4      0.13%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::180224-196607            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         3154                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  25735525988                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.805879                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.396479                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     5001469876     19.43%     19.43% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    20730637612     80.55%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2251500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         605500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         237500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         189000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6          78500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::7          56500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  25735525988                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1742     75.25%     75.25% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          573     24.75%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2315                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7567                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7567                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2315                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2315                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         9882                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20887699                       # ITB inst hits
system.cpu1.itb.inst_misses                      7567                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     472                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2181                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1369                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20895266                       # ITB inst accesses
system.cpu1.itb.hits                         20887699                       # DTB hits
system.cpu1.itb.misses                           7567                       # DTB misses
system.cpu1.itb.accesses                     20895266                       # DTB accesses
system.cpu1.numPwrStateTransitions               2930                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         1465                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    831651195.687372                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   15817593715.627289                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1430     97.61%     97.61% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10           32      2.18%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.07%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.07%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 499953823748                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           1465                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   1586211228818                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218369001682                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       109802096                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40943144                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108514996                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27798523                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19892489                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     64235640                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3213335                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    105850                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7199                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              370                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       133652                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       123170                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          245                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20885138                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               363282                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3860                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         107155901                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.215568                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.316644                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                77413551     72.24%     72.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3964796      3.70%     75.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2490827      2.32%     78.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8243216      7.69%     85.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1613766      1.51%     87.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1187087      1.11%     88.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6283183      5.86%     94.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1186163      1.11%     95.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4773312      4.45%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           107155901                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.253169                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.988278                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27961508                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             60068174                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15895892                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1769487                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1460540                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             2002899                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               148049                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              90324512                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               490358                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1460540                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28915970                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                5237096                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      47181010                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16703954                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              7656988                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              86483131                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 1983                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1745149                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                215112                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               4898057                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           89702997                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            398140635                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        96368391                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6135                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             76284271                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13418710                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1604439                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1503267                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10222597                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15399417                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11771402                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2211738                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2954385                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  83351812                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1152022                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 80024674                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91529                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10956511                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24682043                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        103513                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    107155901                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.746806                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.429727                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           74986719     69.98%     69.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10856192     10.13%     80.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8181836      7.64%     87.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6800942      6.35%     94.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2507542      2.34%     96.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1554150      1.45%     97.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1528598      1.43%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             489898      0.46%     99.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             250024      0.23%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      107155901                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 115019      9.97%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     7      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                527702     45.75%     55.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               510821     44.28%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              144      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             53744043     67.16%     67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59080      0.07%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              3      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4215      0.01%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14957838     18.69%     85.93% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11259342     14.07%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              80024674                       # Type of FU issued
system.cpu1.iq.rate                          0.728808                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1153549                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014415                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268436998                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         95502900                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     77720615                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              13329                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7517                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5775                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              81170860                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7219                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          353138                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2111745                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         1994                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51136                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1016819                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       193347                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       111137                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1460540                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4234573                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               751343                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           84621300                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           108802                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15399417                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11771402                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            582328                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44713                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               693944                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51136                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        222391                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       227484                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              449875                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             79460848                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14731272                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           505307                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       117466                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25893193                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14803387                       # Number of branches executed
system.cpu1.iew.exec_stores                  11161921                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.723673                       # Inst execution rate
system.cpu1.iew.wb_sent                      78896446                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     77726390                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 41030059                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 71721300                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.707877                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.572076                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       10985590                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1048509                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           374030                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    104641106                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.703566                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.592412                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     76039975     72.67%     72.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12757270     12.19%     84.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6567840      6.28%     91.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2747077      2.63%     93.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1449083      1.38%     95.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       932804      0.89%     96.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1855484      1.77%     97.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       438097      0.42%     98.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1853476      1.77%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    104641106                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            60883193                       # Number of instructions committed
system.cpu1.commit.committedOps              73621924                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      24042255                       # Number of memory references committed
system.cpu1.commit.loads                     13287672                       # Number of loads committed
system.cpu1.commit.membars                     433805                       # Number of memory barriers committed
system.cpu1.commit.branches                  14065238                       # Number of branches committed
system.cpu1.commit.fp_insts                      5335                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 64517791                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2723455                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        49518046     67.26%     67.26% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57411      0.08%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4212      0.01%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13287672     18.05%     85.39% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10754583     14.61%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         73621924                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1853476                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   174663739                       # The number of ROB reads
system.cpu1.rob.rob_writes                  171729340                       # The number of ROB writes
system.cpu1.timesIdled                         397158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2646195                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2436737979                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   60808588                       # Number of Instructions Simulated
system.cpu1.committedOps                     73547319                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.805700                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.805700                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.553802                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.553802                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                86393465                       # number of integer regfile reads
system.cpu1.int_regfile_writes               49554201                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16619                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13036                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                280625358                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29714417                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              196041210                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                794463                       # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49488500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               336500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               631000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               20000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6424000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38406000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187814627                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36409                       # number of replacements
system.iocache.tags.tagsinuse                0.981800                       # Cycle average of tags in use
system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234298498000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.981800                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.061363                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.061363                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
system.iocache.tags.data_accesses              328227                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
system.iocache.demand_hits::total                  29                       # number of demand (read+write) hits
system.iocache.overall_hits::realview.ide           29                       # number of overall hits
system.iocache.overall_hits::total                 29                       # number of overall hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
system.iocache.overall_misses::total            36444                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31228377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31228377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4281194250                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4281194250                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4312422627                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4312422627                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4312422627                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4312422627                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36473                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36473                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36473                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36473                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide     0.999205                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 125415.168675                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125415.168675                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118281.371736                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118281.371736                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118330.112693                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118330.112693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118330.112693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118330.112693                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            93                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs           93                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36160                       # number of writebacks
system.iocache.writebacks::total                36160                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36444                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18778377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18778377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2469323520                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2469323520                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2488101897                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2488101897                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2488101897                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2488101897                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.999205                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.999205                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75415.168675                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75415.168675                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68222.779942                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68222.779942                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68271.921222                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68271.921222                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68271.921222                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   104355                       # number of replacements
system.l2c.tags.tagsinuse                65128.328748                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5134809                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169609                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.274390                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   49028.426520                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.557440                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000253                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4778.977549                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2180.200854                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    47.031162                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5874.261984                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3173.872988                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.748114                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000695                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.072921                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.033267                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000718                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.089634                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.048429                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993779                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65176                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           78                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          371                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3222                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8987                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52579                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001190                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994507                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45400104                       # Number of tag accesses
system.l2c.tags.data_accesses                45400104                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker        35642                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6871                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36349                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6520                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85382                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       702484                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          702484                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1895251                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1895251                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              77                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              55                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 132                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            35                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                69                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            82353                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            74147                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156500                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        951848                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        962389                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1914237                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       262559                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       278192                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           540751                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         35642                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6871                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              951848                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              344912                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36349                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6520                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              962389                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              352339                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2696870                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        35642                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6871                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             951848                       # number of overall hits
system.l2c.overall_hits::cpu0.data             344912                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36349                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6520                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             962389                       # number of overall hits
system.l2c.overall_hits::cpu1.data             352339                       # number of overall hits
system.l2c.overall_hits::total                2696870                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           62                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           67                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  130                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1432                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1298                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2730                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           16                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            8                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              24                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          72649                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          67608                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140257                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        10064                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10824                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20888                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         7104                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         8203                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15307                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           62                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             10064                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             79753                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           67                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10824                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             75811                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176582                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           62                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            10064                       # number of overall misses
system.l2c.overall_misses::cpu0.data            79753                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           67                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10824                       # number of overall misses
system.l2c.overall_misses::cpu1.data            75811                       # number of overall misses
system.l2c.overall_misses::total               176582                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5759000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5729000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       11571500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       492500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       441500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       934000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       285000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       200000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       485000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6142757000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5641675000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11784432000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst    833020998                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    909515500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1742536498                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    619108000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    739349500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1358457500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5759000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    833020998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6761865000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5729000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    909515500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6381024500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     14896997498                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5759000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    833020998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6761865000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5729000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    909515500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6381024500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    14896997498                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        35704                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6872                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36416                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6520                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              85512                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       702484                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       702484                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1895251                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1895251                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1509                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1353                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2862                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           50                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           43                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            93                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       155002                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       141755                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296757                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       961912                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       973213                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1935125                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       269663                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       286395                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       556058                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        35704                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6872                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          961912                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          424665                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36416                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6520                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          973213                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          428150                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2873452                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        35704                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6872                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         961912                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         424665                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36416                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6520                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         973213                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         428150                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2873452                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001737                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001840                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001520                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.948973                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.959350                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.953878                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.320000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.186047                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.258065                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.468697                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.476936                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472632                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010462                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011122                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010794                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.026344                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.028642                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027528                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001737                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010462                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.187802                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001840                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011122                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.177066                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061453                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001737                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000146                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010462                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.187802                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001840                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011122                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.177066                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061453                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 89011.538462                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   343.924581                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   340.138675                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   342.124542                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17812.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        25000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 20208.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84553.909896                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83446.855402                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84020.277063                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82772.356717                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84027.669993                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 83422.850345                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87149.211712                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90131.598196                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 88747.468478                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82772.356717                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 84785.086454                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84027.669993                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84170.166599                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 84363.057945                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92887.096774                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82772.356717                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 84785.086454                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85507.462687                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84027.669993                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84170.166599                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 84363.057945                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               95309                       # number of writebacks
system.l2c.writebacks::total                    95309                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           74                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           66                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          140                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             66                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                152                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            74                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            66                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               152                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           62                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           67                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             130                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1432                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1298                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2730                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           16                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           24                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        72649                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        67608                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140257                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10058                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10818                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20876                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         7030                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         8137                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15167                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        10058                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        79679                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           67                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10818                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        75745                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176430                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           62                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        10058                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        79679                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           67                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10818                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        75745                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176430                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16364                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14763                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31794                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15955                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11629                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32319                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26392                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59378                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     10271500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27244500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     24670000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     51914500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       360000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       208500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       568500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5416267000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4965595000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10381862000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    732144498                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    801041001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1533185499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    543432001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    652904000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1196336001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    732144498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5959699001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    801041001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5618499000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  13121655000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5139000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    732144498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5959699001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      5059000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    801041001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5618499000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  13121655000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3103812500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2811194500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5958110498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3103812500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2811194500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5958110498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001737                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001840                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001520                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.948973                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.959350                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.953878                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.320000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.186047                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.258065                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.468697                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.476936                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472632                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010456                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011116                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010788                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.026070                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.028412                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027276                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001737                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010456                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.187628                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001840                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011116                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.176912                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061400                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001737                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000146                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010456                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.187628                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001840                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011116                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.176912                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061400                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 79011.538462                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19025.488827                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19006.163328                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19016.300366                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        22500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 26062.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23687.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74553.909896                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73446.855402                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 74020.277063                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72792.254723                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74047.051303                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73442.493725                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77301.849360                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80238.908689                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78877.563196                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72792.254723                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74796.357899                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74047.051303                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74176.500099                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 74373.150825                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72792.254723                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74796.357899                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74047.051303                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74176.500099                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 74373.150825                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189673.215595                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190421.628395                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.323331                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96036.774034                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106516.918005                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.054263                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        356400                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       150200                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               31794                       # Transaction distribution
system.membus.trans_dist::ReadResp              68215                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131469                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9295                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4625                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             24                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138363                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138363                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36422                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468971                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       576543                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 649411                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17313372                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17477405                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19792605                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              523                       # Total snoops (count)
system.membus.snoop_fanout::samples            275008                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019225                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.137315                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  269721     98.08%     98.08% # Request fanout histogram
system.membus.snoop_fanout::1                    5287      1.92%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              275008                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95651000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1701498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           922033211                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1008880500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1321623                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      5615830                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2827503                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        47677                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            189                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804580230500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq             149204                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2640969                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       797793                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1934891                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          158843                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2863                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            93                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2955                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296757                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296757                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1935543                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       556294                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4761                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5806892                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2681408                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        36148                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166774                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8691222                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247723648                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99732765                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        53568                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       288480                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              347798461                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          141834                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3081573                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027702                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.164119                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2996206     97.23%     97.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  85367      2.77%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3081573                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5532917883                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           308377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2906129853                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1326155422                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          22791427                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          95110077                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------