path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.540587                       # Number of seconds simulated
sim_ticks                                2540587123500                       # Number of ticks simulated
final_tick                               2540587123500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  28859                       # Simulator instruction rate (inst/s)
host_op_rate                                    37121                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1209803028                       # Simulator tick rate (ticks/s)
host_mem_usage                                 406188                       # Number of bytes of host memory used
host_seconds                                  2100.00                       # Real time elapsed on the host
sim_insts                                    60603607                       # Number of instructions simulated
sim_ops                                      77954043                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           521152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4740560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           279808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4349656                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131004456                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       521152                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       279808                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          800960                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3783104                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1619508                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1396592                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6799204                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              8143                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             74105                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4372                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             67969                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293448                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59111                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           404877                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           349148                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813136                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47670291                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           806                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              205131                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1865931                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              110135                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1712067                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51564638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         205131                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         110135                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315266                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1489067                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             637454                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             549712                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2676233                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1489067                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47670291                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          806                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             205131                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2503385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             110135                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2261780                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54240872                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293448                       # Total number of read requests seen
system.physmem.writeReqs                       813136                       # Total number of write requests seen
system.physmem.cpureqs                         218391                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    978780672                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52040704                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              131004456                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6799204                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       10                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4690                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                955907                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                956222                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                955717                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                955757                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                955661                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                955544                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                955404                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                955585                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                956056                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                955920                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               955992                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               955944                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               956032                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               955927                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               956056                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               955714                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50106                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50364                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 49972                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 50036                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50909                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50827                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50676                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50834                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51139                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51219                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51120                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51083                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51352                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51170                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51298                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51031                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                      677160                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2540585876000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      42                       # Categorize read packet sizes
system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154590                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                1431185                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  59111                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 4690                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                   1056941                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    992282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    949580                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    983982                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2774748                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2777750                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   5475537                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     36612                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     30094                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     29956                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    29864                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    57737                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    31653                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    59391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     5382                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1868                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    31866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    31776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    31654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    31445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    31156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    30947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    30761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    30573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    30334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                   295225090687                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              372543516687                       # Sum of mem lat for all requests
system.physmem.totBusLat                  61173752000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16144674000                       # Total cycles spent in bank access
system.physmem.avgQLat                       19304.04                       # Average queueing delay per request
system.physmem.avgBankLat                     1055.66                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  24359.70                       # Average memory access latency
system.physmem.avgRdBW                         385.26                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.48                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.56                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.54                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.15                       # Average read queue length over time
system.physmem.avgWrQLen                         1.12                       # Average write queue length over time
system.physmem.readRowHits                   15250784                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    786076                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.72                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  96.67                       # Row buffer hit rate for writes
system.physmem.avgGap                       157735.86                       # Average gap between requests
system.l2c.replacements                         64360                       # number of replacements
system.l2c.tagsinuse                     51403.610979                       # Cycle average of tags in use
system.l2c.total_refs                         1940230                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        129752                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         14.953373                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2504468947000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36917.340991                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker      20.674010                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000348                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5181.760660                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          3292.636698                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       8.768373                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3037.851423                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2944.578476                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.563314                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000315                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.079067                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.050242                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000134                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.046354                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.044931                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.784357                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        52210                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7522                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             501648                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             201746                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        46118                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6836                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             471830                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             185683                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1473593                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          608099                       # number of Writeback hits
system.l2c.Writeback_hits::total               608099                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  40                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            57007                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            55991                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112998                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         52210                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7522                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              501648                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              258753                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         46118                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6836                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              471830                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              241674                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1586591                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        52210                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7522                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             501648                       # number of overall hits
system.l2c.overall_hits::cpu0.data             258753                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        46118                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6836                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             471830                       # number of overall hits
system.l2c.overall_hits::cpu1.data             241674                       # number of overall hits
system.l2c.overall_hits::total                1586591                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           32                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             8033                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6226                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4376                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4487                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23165                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1562                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1342                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          68853                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          64314                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133167                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8033                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             75079                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             68801                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156332                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8033                       # number of overall misses
system.l2c.overall_misses::cpu0.data            75079                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            9                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4376                       # number of overall misses
system.l2c.overall_misses::cpu1.data            68801                       # number of overall misses
system.l2c.overall_misses::total               156332                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2269000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    420354500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    331291999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       618500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    233702500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    250819000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1239173499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       181000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       252500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       433500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3783281998                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2967459500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6750741498                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2269000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    420354500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4114573997                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       618500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    233702500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3218278500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      7989914997                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2269000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    420354500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4114573997                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       618500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    233702500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3218278500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     7989914997                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        52242                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7524                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         509681                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         207972                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        46127                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6836                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         476206                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         190170                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1496758                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       608099                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           608099                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1582                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1362                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2944                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            13                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       125860                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       120305                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246165                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        52242                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7524                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          509681                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          333832                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        46127                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6836                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          476206                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          310475                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1742923                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        52242                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7524                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         509681                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         333832                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        46127                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6836                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         476206                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         310475                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1742923                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000613                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000266                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015761                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.029937                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000195                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009189                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.023595                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015477                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987358                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.985316                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.986413                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.142857                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.076923                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.547060                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.534591                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.540966                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000613                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000266                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015761                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.224901                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000195                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009189                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.221599                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.089695                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000613                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000266                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015761                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.224901                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000195                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009189                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.221599                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.089695                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70906.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52328.457612                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 53211.050273                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68722.222222                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53405.507313                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 55899.041676                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53493.351997                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   115.877081                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   188.152012                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   149.276860                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54947.235386                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46140.179432                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50693.801753                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70906.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52328.457612                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 54803.260526                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68722.222222                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53405.507313                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 46776.623886                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51108.634170                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70906.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52328.457612                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 54803.260526                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68722.222222                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53405.507313                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 46776.623886                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51108.634170                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59111                       # number of writebacks
system.l2c.writebacks::total                    59111                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         8025                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6187                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            9                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4372                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4463                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23090                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1562                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1342                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2904                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        68853                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        64314                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133167                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8025                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        75040                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4372                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        68777                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156257                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8025                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        75040                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            9                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4372                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        68777                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156257                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    318411185                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    250751004                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    178311078                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    193087266                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    943023112                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15680528                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13422342                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29102870                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2929616476                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2170341063                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5099957539                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    318411185                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   3180367480                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    178311078                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2363428329                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6042980651                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    318411185                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   3180367480                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    178311078                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2363428329                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6042980651                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      4312653                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83955529530                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83016717004                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166976559187                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8488186790                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   5709859144                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  14198045934                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76004                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76004                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      4312653                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92443716320                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  88726576148                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 181174605121                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.029749                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.023468                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015427                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987358                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.985316                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.986413                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.142857                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.076923                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.547060                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.534591                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.540966                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.224784                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.221522                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.089652                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.224784                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.221522                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.089652                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40528.689834                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43264.007618                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40841.191511                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.750320                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.745156                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.649449                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42548.857363                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.012734                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38297.457621                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42382.295842                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34363.643791                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 38673.343601                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42382.295842                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34363.643791                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 38673.343601                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    26104138                       # DTB read hits
system.cpu0.dtb.read_misses                     45655                       # DTB read misses
system.cpu0.dtb.write_hits                    6173225                       # DTB write hits
system.cpu0.dtb.write_misses                    11582                       # DTB write misses
system.cpu0.dtb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                737                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    8687                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1569                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   298                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      666                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                26149793                       # DTB read accesses
system.cpu0.dtb.write_accesses                6184807                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32277363                       # DTB hits
system.cpu0.dtb.misses                          57237                       # DTB misses
system.cpu0.dtb.accesses                     32334600                       # DTB accesses
system.cpu0.itb.inst_hits                     6054056                       # ITB inst hits
system.cpu0.itb.inst_misses                      7505                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                737                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2789                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1640                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6061561                       # ITB inst accesses
system.cpu0.itb.hits                          6054056                       # DTB hits
system.cpu0.itb.misses                           7505                       # DTB misses
system.cpu0.itb.accesses                      6061561                       # DTB accesses
system.cpu0.numCycles                       240389950                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 7650447                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           6071769                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            390619                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              4963412                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 4056247                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  744385                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              39840                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          15652124                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      47554546                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7650447                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4800632                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10611377                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2494725                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     89565                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              50696365                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1823                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             1967                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        55574                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       106827                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          232                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6051824                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               344537                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3471                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          78943853                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.750152                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.105781                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                68340077     86.57%     86.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  702129      0.89%     87.46% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  881040      1.12%     88.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1224383      1.55%     90.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1120463      1.42%     91.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  584523      0.74%     92.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1319074      1.67%     93.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  413717      0.52%     94.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4358447      5.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            78943853                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031825                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.197823                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16656979                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             50446432                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9625401                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               575149                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1637749                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1050019                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                92865                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56438894                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               312308                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1637749                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17559275                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               19379590                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27710296                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9215944                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3438937                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              54038405                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                14132                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                614041                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2240889                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents           19821                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           55994087                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            246350981                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       246302367                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            48614                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             41407239                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14586848                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            463494                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        411765                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6993142                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10396030                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            7010506                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1100529                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1298753                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  50240617                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1080191                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 63997387                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            98424                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10068381                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     24718063                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        263130                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     78943853                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.810670                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.516651                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           55721215     70.58%     70.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7438559      9.42%     80.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3764189      4.77%     84.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3138828      3.98%     88.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6266578      7.94%     96.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1507037      1.91%     98.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             806867      1.02%     99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             233373      0.30%     99.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              67207      0.09%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       78943853                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  28850      0.65%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     4      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4202057     94.56%     95.21% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               212765      4.79%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass           196420      0.31%      0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             30502224     47.66%     47.97% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               49600      0.08%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 1      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1274      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.05% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26758229     41.81%     89.86% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6489612     10.14%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              63997387                       # Type of FU issued
system.cpu0.iq.rate                          0.266223                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4443676                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.069435                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         211525282                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         61397992                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     45248586                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12498                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6745                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5570                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              68238014                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6629                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          331719                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2183838                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         4014                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        16143                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       861796                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17073193                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       345280                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1637749                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               14492701                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               245337                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           51437500                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           107423                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10396030                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             7010506                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            766368                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 62240                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3660                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         16143                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        190401                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       151763                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              342164                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             62995358                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26449087                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1002029                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       116692                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32879818                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6078109                       # Number of branches executed
system.cpu0.iew.exec_stores                   6430731                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.262055                       # Inst execution rate
system.cpu0.iew.wb_sent                      62497341                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     45254156                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24800882                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 45441474                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.188253                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.545776                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        9944794                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         817061                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           299135                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     77306104                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.530438                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.512152                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     62653127     81.05%     81.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7139643      9.24%     90.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2117433      2.74%     93.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1152491      1.49%     94.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1052620      1.36%     95.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       581358      0.75%     96.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       718590      0.93%     97.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       381418      0.49%     98.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1509424      1.95%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     77306104                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            32015395                       # Number of instructions committed
system.cpu0.commit.committedOps              41006110                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14360902                       # Number of memory references committed
system.cpu0.commit.loads                      8212192                       # Number of loads committed
system.cpu0.commit.membars                     221881                       # Number of memory barriers committed
system.cpu0.commit.branches                   5266033                       # Number of branches committed
system.cpu0.commit.fp_insts                      5497                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 36294613                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              520344                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1509424                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   125738503                       # The number of ROB reads
system.cpu0.rob.rob_writes                  103590706                       # The number of ROB writes
system.cpu0.timesIdled                         892654                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      161446097                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2255175331                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   31936467                       # Number of Instructions Simulated
system.cpu0.committedOps                     40927182                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             31936467                       # Number of Instructions Simulated
system.cpu0.cpi                              7.527130                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        7.527130                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.132853                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.132853                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               285784738                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46365180                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    22828                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   19904                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               16064067                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                471303                       # number of misc regfile writes
system.cpu0.icache.replacements                986601                       # number of replacements
system.cpu0.icache.tagsinuse               511.585602                       # Cycle average of tags in use
system.cpu0.icache.total_refs                10225858                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                987113                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 10.359359                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6782112000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   321.917069                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst   189.668533                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.628744                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.370446                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999191                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      5498991                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      4726867                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       10225858                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5498991                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      4726867                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        10225858                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5498991                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      4726867                       # number of overall hits
system.cpu0.icache.overall_hits::total       10225858                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       552708                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       515964                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1068672                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       552708                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       515964                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1068672                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       552708                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       515964                       # number of overall misses
system.cpu0.icache.overall_misses::total      1068672                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7467633494                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6811010992                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14278644486                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7467633494                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6811010992                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14278644486                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7467633494                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6811010992                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14278644486                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6051699                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5242831                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     11294530                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6051699                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5242831                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     11294530                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6051699                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5242831                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     11294530                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091331                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.098413                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.094619                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091331                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.098413                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.094619                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091331                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.098413                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.094619                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13510.992231                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13200.554674                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13361.110318                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13510.992231                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13200.554674                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13361.110318                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13510.992231                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13200.554674                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13361.110318                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4485                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          398                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              340                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.191176                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          398                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42344                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39180                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        81524                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        42344                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        39180                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        81524                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        42344                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        39180                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        81524                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       510364                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       476784                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       987148                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       510364                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       476784                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       987148                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       510364                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       476784                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       987148                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6084165494                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5553411993                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11637577487                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6084165494                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5553411993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11637577487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6084165494                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5553411993                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11637577487                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      6767000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      6767000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      6767000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      6767000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087401                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.087401                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.087401                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.090883                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.090883                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.090883                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                643795                       # number of replacements
system.cpu0.dcache.tagsinuse               511.994133                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                21730635                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                644307                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.727144                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              36157000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   255.754263                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data   256.239870                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.499520                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.500468                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999989                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7320998                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6545083                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13866081                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3839440                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3452761                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7292201                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       142548                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       140954                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       283502                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       144156                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       141612                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       285768                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11160438                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      9997844                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21158282                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11160438                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      9997844                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21158282                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       376773                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       369451                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       746224                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1505844                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1453809                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2959653                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7530                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6140                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13670                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1882617                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1823260                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3705877                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1882617                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1823260                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3705877                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5747755000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5402696500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11150451500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  63541262289                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  51082353349                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114623615638                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    104538500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81673500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    186212000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        78000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       103000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       181000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  69289017289                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  56485049849                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125774067138                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  69289017289                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  56485049849                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125774067138                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7697771                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      6914534                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14612305                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5345284                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      4906570                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10251854                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       150078                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       147094                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       297172                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144162                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       141619                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       285781                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13043055                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     11821104                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24864159                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13043055                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     11821104                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24864159                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048946                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.053431                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051068                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.281714                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.296298                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.288694                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.050174                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.041742                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046000                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000042                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000049                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.144339                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.154238                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149045                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.144339                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.154238                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149045                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15255.219987                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14623.580664                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14942.499169                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42196.444179                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35136.908183                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38728.734631                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13882.934927                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13301.872964                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13621.945867                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14714.285714                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13923.076923                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36804.627436                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30980.249580                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33939.083013                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36804.627436                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30980.249580                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33939.083013                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        35448                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        12573                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3421                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            258                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.361882                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    48.732558                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       608099                       # number of writebacks
system.cpu0.dcache.writebacks::total           608099                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       175511                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       184666                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       360177                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1378456                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1332180                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2710636                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          766                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          717                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1483                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1553967                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1516846                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3070813                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1553967                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1516846                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3070813                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       201262                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       184785                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       386047                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       127388                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       121629                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       249017                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6764                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5423                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12187                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       328650                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       306414                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       635064                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       328650                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       306414                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       635064                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2736355500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2446708500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5183064000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4640301429                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3791272989                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8431574418                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     82236000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62703500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    144939500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        66000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        89000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       155000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7376656929                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6237981489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13614638418                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7376656929                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6237981489                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13614638418                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91682874000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90682822000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182365696000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13814824895                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  10281264593                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  24096089488                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105497698895                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100964086593                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206461785488                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.026145                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026724                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026419                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023832                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024789                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024290                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.045070                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.036868                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.041010                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000042                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000049                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025921                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025541                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025921                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025541                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13595.986823                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13240.839354                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13425.992172                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36426.519209                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31170.797992                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33859.432962                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12157.894737                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11562.511525                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11892.959711                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923.076923                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22445.327640                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20358.017222                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21438.214759                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22445.327640                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20358.017222                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21438.214759                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25160982                       # DTB read hits
system.cpu1.dtb.read_misses                     40128                       # DTB read misses
system.cpu1.dtb.write_hits                    5622181                       # DTB write hits
system.cpu1.dtb.write_misses                     9250                       # DTB write misses
system.cpu1.dtb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                702                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    7925                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1386                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   276                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      627                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25201110                       # DTB read accesses
system.cpu1.dtb.write_accesses                5631431                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         30783163                       # DTB hits
system.cpu1.dtb.misses                          49378                       # DTB misses
system.cpu1.dtb.accesses                     30832541                       # DTB accesses
system.cpu1.itb.inst_hits                     5244962                       # ITB inst hits
system.cpu1.itb.inst_misses                      6670                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                702                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2650                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1456                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 5251632                       # ITB inst accesses
system.cpu1.itb.hits                          5244962                       # DTB hits
system.cpu1.itb.misses                           6670                       # DTB misses
system.cpu1.itb.accesses                      5251632                       # DTB accesses
system.cpu1.numCycles                       232013377                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 6790425                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           5410391                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            343130                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              4365867                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 3552399                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  675836                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              35150                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          14219364                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      41265528                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    6790425                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4228235                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      9330468                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2101425                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     82678                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              47674573                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                1053                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             1954                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        48379                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        99398                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          108                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5242833                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               267586                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2984                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          72923984                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.712246                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.058401                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                63601422     87.22%     87.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  651379      0.89%     88.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  811870      1.11%     89.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1013874      1.39%     90.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  943793      1.29%     91.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  538574      0.74%     92.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1195574      1.64%     94.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  358365      0.49%     94.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 3809133      5.22%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            72923984                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.029267                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.177858                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                15065111                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             47459427                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  8508787                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               504767                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1383740                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              935366                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                84721                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              49702311                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               283407                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1383740                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                15832821                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               18424865                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      25966015                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8176580                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3137893                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              47902393                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 7520                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                511770                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2112759                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           14566                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           49459920                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            218567938                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       218526163                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            41775                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             37332689                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                12127230                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            420234                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        377586                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6217035                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9300150                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6339076                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           983520                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1172387                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  44745095                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             970903                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 59171295                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            83947                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        8398889                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     19786111                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        243126                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     72923984                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.811411                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.516236                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           51567769     70.71%     70.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6722785      9.22%     79.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3414540      4.68%     84.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2860255      3.92%     88.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6054704      8.30%     96.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1326273      1.82%     98.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             714361      0.98%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             204058      0.28%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              59239      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       72923984                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  24658      0.56%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     2      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4170684     95.00%     95.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               195004      4.44%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           167246      0.28%      0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             27298169     46.13%     46.42% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               44245      0.07%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  6      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              3      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           839      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     46.49% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            25732684     43.49%     89.98% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            5928100     10.02%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              59171295                       # Type of FU issued
system.cpu1.iq.rate                          0.255034                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4390348                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.074197                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         195779484                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         54123667                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     40860194                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              10578                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              5727                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         4726                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              63388772                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   5625                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          295886                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      1794199                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2827                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        15001                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       687985                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     17035415                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       238532                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1383740                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               13800740                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               226965                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           45822265                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            96960                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9300150                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6339076                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            695770                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 48787                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3997                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         15001                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        167673                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       132287                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              299960                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             58435443                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25502557                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           735852                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       106267                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31379358                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5453104                       # Number of branches executed
system.cpu1.iew.exec_stores                   5876801                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.251862                       # Inst execution rate
system.cpu1.iew.wb_sent                      58051293                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     40864920                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 22407090                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 41228321                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.176132                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.543488                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        8312194                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         727777                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           259619                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     71540244                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.518566                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.491714                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     58151016     81.28%     81.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6627858      9.26%     90.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1880092      2.63%     93.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1040741      1.45%     94.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       983750      1.38%     96.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       494100      0.69%     96.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       697389      0.97%     97.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       324169      0.45%     98.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1341129      1.87%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     71540244                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            28738593                       # Number of instructions committed
system.cpu1.commit.committedOps              37098314                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13157042                       # Number of memory references committed
system.cpu1.commit.loads                      7505951                       # Number of loads committed
system.cpu1.commit.membars                     191336                       # Number of memory barriers committed
system.cpu1.commit.branches                   4758017                       # Number of branches committed
system.cpu1.commit.fp_insts                      4715                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 32847444                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              475803                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1341129                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   114702650                       # The number of ROB reads
system.cpu1.rob.rob_writes                   92242025                       # The number of ROB writes
system.cpu1.timesIdled                         868716                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      159089393                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2323530978                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   28667140                       # Number of Instructions Simulated
system.cpu1.committedOps                     37026861                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             28667140                       # Number of Instructions Simulated
system.cpu1.cpi                              8.093356                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.093356                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.123558                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.123558                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               264545362                       # number of integer regfile reads
system.cpu1.int_regfile_writes               41743183                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    22037                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   19620                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               14602821                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                442325                       # number of misc regfile writes
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125347676632                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1125347676632                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125347676632                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1125347676632                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   88038                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------