path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.543301                       # Number of seconds simulated
sim_ticks                                2543301032500                       # Number of ticks simulated
final_tick                               2543301032500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  74756                       # Simulator instruction rate (inst/s)
host_op_rate                                    96190                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3152487696                       # Simulator tick rate (ticks/s)
host_mem_usage                                 404224                       # Number of bytes of host memory used
host_seconds                                   806.76                       # Real time elapsed on the host
sim_insts                                    60309843                       # Number of instructions simulated
sim_ops                                      77602131                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           508544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4232464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           292032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4862300                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131009324                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       508544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       292032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          800576                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3788480                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1346148                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1669964                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6804592                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7946                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             66166                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4563                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             75980                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293525                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59195                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           336537                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           417491                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813223                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47619423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           805                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              199954                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1664162                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              114824                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1911807                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51511529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         199954                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         114824                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314778                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1489592                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             529292                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             656613                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2675496                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1489592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47619423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          805                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             199954                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2193453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             114824                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2568420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54187025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293525                       # Total number of read requests seen
system.physmem.writeReqs                       813223                       # Total number of write requests seen
system.physmem.cpureqs                         218526                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    978785600                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52046272                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              131009324                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6804592                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       11                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4665                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                956243                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                955738                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                955677                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                956490                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                956276                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                955444                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                955565                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                956160                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                956100                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                955611                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               955526                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               955934                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               956026                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               955429                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               955315                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               955980                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50841                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50418                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50434                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50916                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50190                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50284                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50863                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51375                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 50908                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50806                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51196                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51248                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50726                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                50627                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51229                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32474                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2543299855000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      43                       # Categorize read packet sizes
system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154666                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754028                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  59195                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1054830                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    991608                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    961225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3605146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2718488                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2722266                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2700528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     59953                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59337                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    109948                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   160370                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   109866                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    10050                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     9990                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    10676                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     9203                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32480                       # What write queue length does an incoming req see
system.physmem.totQLat                   346872048750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              440039818750                       # Sum of mem lat for all requests
system.physmem.totBusLat                  76467570000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16700200000                       # Total cycles spent in bank access
system.physmem.avgQLat                       22680.99                       # Average queueing delay per request
system.physmem.avgBankLat                     1091.98                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  28772.97                       # Average memory access latency
system.physmem.avgRdBW                         384.85                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.46                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.51                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                         1.13                       # Average write queue length over time
system.physmem.readRowHits                   15218379                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    794608                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.71                       # Row buffer hit rate for writes
system.physmem.avgGap                       157902.75                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         64434                       # number of replacements
system.l2c.tagsinuse                     51415.067512                       # Cycle average of tags in use
system.l2c.total_refs                         1904100                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         14.666441                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2506327384000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36945.837156                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker      20.213783                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000349                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5214.159096                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          3260.668190                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      16.334221                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          2999.640373                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2958.214345                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.563749                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000308                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.079562                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.049754                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000249                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.045771                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.045139                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.784532                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        32674                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7484                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             493926                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             214255                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        30206                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6691                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             477455                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             172903                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1435594                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          607840                       # number of Writeback hits
system.l2c.Writeback_hits::total               607840                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              18                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  32                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             4                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 9                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            57831                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            55019                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112850                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         32674                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7484                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              493926                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              272086                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         30206                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6691                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              477455                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              227922                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1548444                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        32674                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7484                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             493926                       # number of overall hits
system.l2c.overall_hits::cpu0.data             272086                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        30206                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6691                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             477455                       # number of overall hits
system.l2c.overall_hits::cpu1.data             227922                       # number of overall hits
system.l2c.overall_hits::total                1548444                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           32                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7836                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6093                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           20                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4567                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4625                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23175                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1542                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1367                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          61052                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72150                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133202                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7836                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             67145                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4567                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76775                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156377                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7836                       # number of overall misses
system.l2c.overall_misses::cpu0.data            67145                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           20                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4567                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76775                       # number of overall misses
system.l2c.overall_misses::total               156377                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2696500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    433331500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    351362499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1374500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    265787000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    271348500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1326018499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       182500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       204500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       387000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3189901000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3583059500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6772960500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2696500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    433331500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3541263499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1374500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    265787000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3854408000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8098978999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2696500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    433331500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3541263499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1374500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    265787000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3854408000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8098978999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        32706                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7486                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         501762                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         220348                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        30226                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6691                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         482022                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         177528                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1458769                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       607840                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           607840                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1560                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1381                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2941                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             9                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       118883                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       127169                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246052                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        32706                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7486                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          501762                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          339231                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        30226                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6691                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          482022                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          304697                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1704821                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        32706                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7486                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         501762                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         339231                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        30226                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6691                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         482022                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         304697                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1704821                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000978                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000267                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015617                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.027652                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000662                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009475                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.026052                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015887                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.988462                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989862                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.989119                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.513547                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.567355                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541357                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000978                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000267                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015617                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.197933                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000662                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009475                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.251972                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.091726                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000978                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000267                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015617                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.197933                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000662                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009475                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.251972                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.091726                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84265.625000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55300.089331                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 57666.584441                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        68725                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58197.284870                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58669.945946                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 57217.626710                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   118.352789                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   149.597659                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   133.035407                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52248.918954                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49661.254331                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50847.288329                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84265.625000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55300.089331                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52740.539117                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        68725                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 58197.284870                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 50203.946597                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51791.369568                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84265.625000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55300.089331                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52740.539117                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        68725                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 58197.284870                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 50203.946597                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51791.369568                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59195                       # number of writebacks
system.l2c.writebacks::total                    59195                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            42                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            19                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                74                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             42                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            42                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7827                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6051                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           20                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4563                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4606                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23101                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1542                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1367                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        61052                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72150                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133202                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7827                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        67103                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4563                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76756                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156303                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7827                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        67103                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4563                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76756                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156303                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2297031                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93251                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    335537534                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    273929174                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1125020                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    208772018                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    212715078                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1034469106                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15421542                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13671367                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29092909                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2428445133                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2684323323                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5112768456                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2297031                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93251                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    335537534                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2702374307                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1125020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    208772018                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2897038401                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6147237562                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2297031                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93251                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    335537534                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2702374307                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1125020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    208772018                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2897038401                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6147237562                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5052330                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  84065259767                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82897447004                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166967759101                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  10492990778                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  13230163640                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  23723154418                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76253                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76253                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5052330                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  94558250545                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  96127610644                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190690913519                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000978                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000267                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015599                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027461                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000662                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009466                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025945                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015836                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.988462                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.989862                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.989119                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.513547                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.567355                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541357                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000978                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000267                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015599                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.197809                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000662                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009466                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.251909                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.091683                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000978                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000267                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015599                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.197809                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000662                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009466                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.251909                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.091683                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42869.239044                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45270.066766                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        56251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45753.236467                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46182.170647                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44780.273841                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39776.667972                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37204.758462                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38383.571238                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42869.239044                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40272.034142                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        56251                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45753.236467                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37743.478047                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39328.980007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42869.239044                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40272.034142                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        56251                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45753.236467                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37743.478047                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39328.980007                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                7635591                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          6085397                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           382495                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4962348                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4056906                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            81.753759                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 731596                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             39324                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    26057064                       # DTB read hits
system.cpu0.dtb.read_misses                     40223                       # DTB read misses
system.cpu0.dtb.write_hits                    5918699                       # DTB write hits
system.cpu0.dtb.write_misses                     9531                       # DTB write misses
system.cpu0.dtb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5688                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1419                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   294                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      673                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                26097287                       # DTB read accesses
system.cpu0.dtb.write_accesses                5928230                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31975763                       # DTB hits
system.cpu0.dtb.misses                          49754                       # DTB misses
system.cpu0.dtb.accesses                     32025517                       # DTB accesses
system.cpu0.itb.inst_hits                     6123062                       # ITB inst hits
system.cpu0.itb.inst_misses                      7629                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2663                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1589                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6130691                       # ITB inst accesses
system.cpu0.itb.hits                          6123062                       # DTB hits
system.cpu0.itb.misses                           7629                       # DTB misses
system.cpu0.itb.accesses                      6130691                       # DTB accesses
system.cpu0.numCycles                       239038664                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          15574951                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      47914738                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7635591                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4788502                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10629711                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2569699                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     94247                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              49519281                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             2018                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        51773                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       101169                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          218                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6121027                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               398928                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3254                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          77753565                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.762466                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.119834                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67131545     86.34%     86.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  691431      0.89%     87.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  886662      1.14%     88.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1230744      1.58%     89.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1150970      1.48%     91.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  576090      0.74%     92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1323248      1.70%     93.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  399344      0.51%     94.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4363531      5.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            77753565                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031943                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.200448                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16625563                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             49255605                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9626158                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               554470                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1689651                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1030343                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                91400                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56424531                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               305535                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1689651                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17561755                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               18982691                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27011773                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9171817                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3333839                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              53601005                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                13486                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                625862                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2162558                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             496                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           55732914                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            244003598                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       243955563                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            48035                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             40460066                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                15272848                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            429896                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        381627                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6785358                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10376846                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6807542                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1061382                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1293746                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  49728955                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1043658                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 63251434                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            97401                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10543512                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     26574090                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        266492                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     77753565                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.813486                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.519509                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           54887435     70.59%     70.59% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7226514      9.29%     79.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3706413      4.77%     84.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3121683      4.01%     88.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6295236      8.10%     96.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1399247      1.80%     98.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             816831      1.05%     99.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             232768      0.30%     99.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              67438      0.09%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       77753565                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  32377      0.72%      0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     4      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4226171     94.63%     95.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               207252      4.64%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass           195848      0.31%      0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29986404     47.41%     47.72% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               47518      0.08%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  4      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 3      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              2      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1215      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26774233     42.33%     90.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6246205      9.88%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              63251434                       # Type of FU issued
system.cpu0.iq.rate                          0.264608                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4465804                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.070604                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         208856960                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         61325058                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     44235430                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12232                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6621                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5553                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              67514929                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6461                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          324203                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2284618                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3570                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        16131                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       894521                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17140357                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       367566                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1689651                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               14217323                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               235152                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           50889581                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           104636                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10376846                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6807542                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            742609                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 56975                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3444                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         16131                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        187025                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       148295                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              335320                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             62072955                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26415193                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1178479                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       116968                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32604278                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6035543                       # Number of branches executed
system.cpu0.iew.exec_stores                   6189085                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.259677                       # Inst execution rate
system.cpu0.iew.wb_sent                      61541297                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     44240983                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24348710                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 44715244                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.185079                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.544528                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       10387971                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         777166                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           292435                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     76063914                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.525878                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.507211                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     61806692     81.26%     81.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6917678      9.09%     90.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2055110      2.70%     93.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1140236      1.50%     94.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1042779      1.37%     95.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       551797      0.73%     96.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       701755      0.92%     97.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       371851      0.49%     98.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1476016      1.94%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     76063914                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            31320190                       # Number of instructions committed
system.cpu0.commit.committedOps              40000322                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14005249                       # Number of memory references committed
system.cpu0.commit.loads                      8092228                       # Number of loads committed
system.cpu0.commit.membars                     212474                       # Number of memory barriers committed
system.cpu0.commit.branches                   5211695                       # Number of branches committed
system.cpu0.commit.fp_insts                      5465                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 35344589                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              514446                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1476016                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   123998072                       # The number of ROB reads
system.cpu0.rob.rob_writes                  102508386                       # The number of ROB writes
system.cpu0.timesIdled                         885261                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      161285099                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2289741427                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   31240748                       # Number of Instructions Simulated
system.cpu0.committedOps                     39920880                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             31240748                       # Number of Instructions Simulated
system.cpu0.cpi                              7.651503                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        7.651503                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.130693                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.130693                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               281024230                       # number of integer regfile reads
system.cpu0.int_regfile_writes               45498524                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    22712                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   19798                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               15634103                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                430225                       # number of misc regfile writes
system.cpu0.icache.replacements                984356                       # number of replacements
system.cpu0.icache.tagsinuse               511.608403                       # Cycle average of tags in use
system.cpu0.icache.total_refs                11036978                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                984868                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 11.206556                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6537508000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   359.190801                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst   152.417601                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.701545                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.297691                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999235                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      5577013                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5459965                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       11036978                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5577013                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5459965                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        11036978                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5577013                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5459965                       # number of overall hits
system.cpu0.icache.overall_hits::total       11036978                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       543890                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       521924                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1065814                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       543890                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       521924                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1065814                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       543890                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       521924                       # number of overall misses
system.cpu0.icache.overall_misses::total      1065814                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7368318492                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6936357997                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14304676489                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7368318492                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6936357997                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14304676489                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7368318492                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6936357997                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14304676489                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6120903                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5981889                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     12102792                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6120903                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5981889                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     12102792                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6120903                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5981889                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     12102792                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.088858                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.087251                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.088063                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.088858                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.087251                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.088063                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.088858                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.087251                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.088063                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.442483                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.977079                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13421.362910                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.442483                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13289.977079                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13421.362910                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.442483                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13289.977079                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13421.362910                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4739                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          847                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              348                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.617816                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          847                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        41550                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39375                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        80925                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        41550                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        39375                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        80925                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        41550                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        39375                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        80925                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       502340                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       482549                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       984889                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       502340                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       482549                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       984889                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       502340                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       482549                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       984889                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6009302492                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5650286997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11659589489                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6009302492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5650286997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11659589489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6009302492                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5650286997                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11659589489                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7527500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7527500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7527500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7527500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.082070                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.080668                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.081377                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.082070                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.080668                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.081377                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.082070                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.080668                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.081377                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11962.619923                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11709.250246                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11838.480772                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11962.619923                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11709.250246                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11838.480772                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11962.619923                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11709.250246                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11838.480772                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                643416                       # number of replacements
system.cpu0.dcache.tagsinuse               511.992721                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                21533980                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                643928                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.441596                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43205000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   319.135976                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data   192.856745                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.623312                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.376673                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999986                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7135768                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6642238                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13778006                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3777278                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3484344                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7261622                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       125855                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117826                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       243681                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       127868                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       119748                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247616                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10913046                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10126582                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21039628                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10913046                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10126582                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21039628                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       434985                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       314667                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       749652                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1404591                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1556569                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2961160                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6908                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6675                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13583                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1839576                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1871236                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3710812                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1839576                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1871236                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3710812                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6475247500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   4924263000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11399510500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  53630269354                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  60756601793                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114386871147                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     93311000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     93587500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    186898500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        52000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        65000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       117000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  60105516854                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  65680864793                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125786381647                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  60105516854                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  65680864793                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125786381647                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7570753                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      6956905                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14527658                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5181869                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5040913                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10222782                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       132763                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       124501                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       257264                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       127872                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       119753                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247625                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12752622                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     11997818                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24750440                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12752622                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     11997818                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24750440                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.057456                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.045231                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051602                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.271059                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.308787                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.289663                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.052033                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.053614                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052798                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000031                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000042                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000036                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.144251                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.155965                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149929                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.144251                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.155965                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149929                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14886.139752                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15649.124312                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.403104                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38182.125155                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39032.385839                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38629.074804                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.672264                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14020.599251                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.736435                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32673.570896                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35100.257152                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33897.266056                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32673.570896                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35100.257152                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33897.266056                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        35700                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        14875                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3523                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            259                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.133409                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    57.432432                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       607840                       # number of writebacks
system.cpu0.dcache.writebacks::total           607840                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       220807                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       143078                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       363885                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1284196                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1428063                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2712259                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          690                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          692                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1382                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1505003                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1571141                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3076144                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1505003                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1571141                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3076144                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       214178                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       171589                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       385767                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       120395                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       128506                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       248901                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6218                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5983                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12201                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       334573                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       300095                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       634668                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       334573                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       300095                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       634668                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2912392000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2322926000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5235318000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4032811992                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   4423017439                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8455829431                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72820000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73471000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    146291000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        44000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        55000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        99000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6945203992                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6745943439                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13691147431                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6945203992                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6745943439                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13691147431                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91812195000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90543970000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356165000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  14920751936                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  18671646220                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  33592398156                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106732946936                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109215616220                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948563156                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028290                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024665                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026554                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023234                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025493                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024348                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046835                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.048056                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047426                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000031                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000042                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000036                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026236                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025012                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025643                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026236                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025012                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025643                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13597.997927                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13537.732605                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13571.191937                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33496.507264                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34418.762073                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33972.661544                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11711.161145                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12279.959886                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11990.082780                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20758.411444                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22479.359666                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21572.140759                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20758.411444                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22479.359666                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21572.140759                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                7008518                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5622209                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           340954                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4512372                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3795619                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            84.115826                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 671281                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             35132                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25306381                       # DTB read hits
system.cpu1.dtb.read_misses                     36302                       # DTB read misses
system.cpu1.dtb.write_hits                    5796978                       # DTB write hits
system.cpu1.dtb.write_misses                     9188                       # DTB write misses
system.cpu1.dtb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    5467                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1344                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   228                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      638                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25342683                       # DTB read accesses
system.cpu1.dtb.write_accesses                5806166                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         31103359                       # DTB hits
system.cpu1.dtb.misses                          45490                       # DTB misses
system.cpu1.dtb.accesses                     31148849                       # DTB accesses
system.cpu1.itb.inst_hits                     5983864                       # ITB inst hits
system.cpu1.itb.inst_misses                      6799                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2574                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1412                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 5990663                       # ITB inst accesses
system.cpu1.itb.hits                          5983864                       # DTB hits
system.cpu1.itb.misses                           6799                       # DTB misses
system.cpu1.itb.accesses                      5990663                       # DTB accesses
system.cpu1.numCycles                       234290379                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          15116451                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      46466902                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    7008518                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4466900                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     10252429                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2600331                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     81459                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              47550524                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                 905                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             2006                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        43802                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        94777                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          144                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5981892                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               442637                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2912                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          74921475                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.771035                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.135527                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                64676712     86.33%     86.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  618864      0.83%     87.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  829977      1.11%     88.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1202840      1.61%     89.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1044061      1.39%     91.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  533999      0.71%     91.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1368584      1.83%     93.80% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  349498      0.47%     94.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4296940      5.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            74921475                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.029914                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.198330                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                16127430                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             47340991                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  9302277                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               452157                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1696491                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              939788                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                85014                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              54712393                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               283938                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1696491                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17063579                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               18568678                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      25752424                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8740556                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3097679                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              51550474                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 7120                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                486939                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2114664                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents              95                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           53606265                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            236686025                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       236643642                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            42383                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             37932809                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                15673455                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            402617                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        356688                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6237356                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9815438                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6669487                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           880329                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1133832                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  47508806                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             941900                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 60718178                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            80732                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10491137                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     27821920                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        236570                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     74921475                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.810424                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.521077                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           53226617     71.04%     71.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6639225      8.86%     79.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3521147      4.70%     84.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2865539      3.82%     88.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6243808      8.33%     96.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1415606      1.89%     98.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             739373      0.99%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             210738      0.28%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              59422      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       74921475                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  26168      0.60%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     1      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4150795     94.85%     95.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               199100      4.55%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           167818      0.28%      0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             28373691     46.73%     47.01% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46091      0.08%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           896      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            26040141     42.89%     89.97% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6089511     10.03%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              60718178                       # Type of FU issued
system.cpu1.iq.rate                          0.259158                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4376064                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.072072                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         200849206                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         58949996                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     41661656                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              10739                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              5891                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         4795                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              64920728                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   5696                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          301587                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2252430                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3185                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        14519                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       849951                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     16963490                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       458141                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1696491                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               13989696                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               234454                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           48555942                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            97471                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9815438                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6669487                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            669348                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 52364                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3770                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         14519                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        165263                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       131892                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              297155                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             59347630                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25635579                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1370548                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       105236                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31674399                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5507310                       # Number of branches executed
system.cpu1.iew.exec_stores                   6038820                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.253308                       # Inst execution rate
system.cpu1.iew.wb_sent                      58770434                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     41666451                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 22724136                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 41696356                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.177841                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.544991                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       10406617                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         705330                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           257195                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     73224984                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.515564                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.495876                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     59733735     81.58%     81.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6648402      9.08%     90.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1900730      2.60%     93.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1014899      1.39%     94.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       955667      1.31%     95.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       519546      0.71%     96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       702094      0.96%     97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       374619      0.51%     98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1375292      1.88%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     73224984                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            29140034                       # Number of instructions committed
system.cpu1.commit.committedOps              37752190                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13382544                       # Number of memory references committed
system.cpu1.commit.loads                      7563008                       # Number of loads committed
system.cpu1.commit.membars                     191164                       # Number of memory barriers committed
system.cpu1.commit.branches                   4749934                       # Number of branches committed
system.cpu1.commit.fp_insts                      4747                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 33512913                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              476869                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1375292                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   119137293                       # The number of ROB reads
system.cpu1.rob.rob_writes                   98065994                       # The number of ROB writes
system.cpu1.timesIdled                         872405                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      159368904                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2285729995                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   29069095                       # Number of Instructions Simulated
system.cpu1.committedOps                     37681251                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             29069095                       # Number of Instructions Simulated
system.cpu1.cpi                              8.059775                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.059775                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.124073                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.124073                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               268846383                       # number of integer regfile reads
system.cpu1.int_regfile_writes               42770958                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    22164                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   19740                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               14685681                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                402240                       # number of misc regfile writes
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192848371945                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192848371945                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192848371945                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192848371945                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83051                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------