path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.817566                       # Number of seconds simulated
sim_ticks                                2817566302500                       # Number of ticks simulated
final_tick                               2817566302500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 130714                       # Simulator instruction rate (inst/s)
host_op_rate                                   158652                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3149885183                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588664                       # Number of bytes of host memory used
host_seconds                                   894.50                       # Real time elapsed on the host
sim_insts                                   116922977                       # Number of instructions simulated
sim_ops                                     141913965                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           681792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5202336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           690880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4586120                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11170792                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       681792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       690880                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1372672                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8446592                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8464116                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10653                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             81805                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           76                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10795                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             71660                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175064                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131978                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136359                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              241979                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1846393                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1726                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              245205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1627688                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3964695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         241979                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         245205                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             487184                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2997833                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6217                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3004052                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2997833                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             241979                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1852610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1726                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             245205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1627691                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6968747                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175065                       # Number of read requests accepted
system.physmem.writeReqs                       136359                       # Number of write requests accepted
system.physmem.readBursts                      175065                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     136359                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11195328                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8832                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8476864                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11170856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8464116                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      138                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12026                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11043                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11014                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11213                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11525                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11226                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11723                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11697                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10818                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11281                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10383                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9838                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10204                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10800                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10202                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9934                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8926                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8447                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8579                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8754                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8390                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8423                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8479                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8702                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8251                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8712                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8030                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7698                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7882                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8282                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7677                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7219                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
system.physmem.totGap                    2817566126000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174509                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131978                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    104121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62577                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6503                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1707                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7438                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6887                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       54                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65817                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.891289                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.511638                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.918519                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24962     37.93%     37.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16108     24.47%     62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6699     10.18%     72.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3770      5.73%     78.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2952      4.49%     82.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1615      2.45%     85.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1043      1.58%     86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1102      1.67%     88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7566     11.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65817                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6524                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.807940                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      488.205097                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6522     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6524                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6524                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.302115                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.296217                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.183093                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                18      0.28%      0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 6      0.09%      0.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                6      0.09%      0.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               9      0.14%      0.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5697     87.32%     87.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             177      2.71%     90.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              43      0.66%     91.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              57      0.87%     92.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              27      0.41%     92.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              20      0.31%     92.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              60      0.92%     93.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.15%     93.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             144      2.21%     96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.18%     96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.08%     96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.15%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              63      0.97%     97.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.14%     97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     97.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              26      0.40%     98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              90      1.38%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.05%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             5      0.08%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             9      0.14%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6524                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2763863500                       # Total ticks spent queuing
system.physmem.totMemAccLat                6043744750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    874635000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15800.10                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34550.10                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.74                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.81                       # Average write queue length when enqueuing
system.physmem.readRowHits                     143943                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97617                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.69                       # Row buffer hit rate for writes
system.physmem.avgGap                      9047363.49                       # Average gap between requests
system.physmem.pageHitRate                      78.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  262097640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  143009625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 713442600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                445176000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184029555840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80250373530                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1620143225250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1885986880485                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.367938                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2695137554500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94084640000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     28341635500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  235478880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  128485500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 650980200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                413106480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184029555840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79085591640                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1621164963750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1885708162290                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.269016                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2696848801250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94084640000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26632850750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          273                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              273                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          273                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          273                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          273                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             273                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26582301                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13715885                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           494954                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            15490869                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8022372                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            51.787747                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6629975                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28839                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4497397                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           4389117                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          108280                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        31787                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    58814                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               58814                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17346                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14926                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        26542                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        32272                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   726.791026                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  4755.027696                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        31886     98.80%     98.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          277      0.86%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           61      0.19%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           23      0.07%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           11      0.03%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::163840-180223            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::180224-196607            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        32272                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12665                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13014.923016                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10587.989224                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9127.008729                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        12438     98.21%     98.21% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535          206      1.63%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303            5      0.04%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071            9      0.07%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            6      0.05%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12665                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  90261197040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.667138                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.493122                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  90178529040     99.91%     99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     56487500      0.06%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     11942500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4980500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      3127500      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1706500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1155500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      2289000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       484000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       141500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21        89500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        39000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       163500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        25500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        11500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31        24500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  90261197040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3551     69.31%     69.31% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1572     30.69%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5123                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58814                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58814                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5123                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5123                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        63937                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13996599                       # DTB read hits
system.cpu0.dtb.read_misses                     49814                       # DTB read misses
system.cpu0.dtb.write_hits                   10431599                       # DTB write hits
system.cpu0.dtb.write_misses                     9000                       # DTB write misses
system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3299                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      781                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1241                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      730                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14046413                       # DTB read accesses
system.cpu0.dtb.write_accesses               10440599                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24428198                       # DTB hits
system.cpu0.dtb.misses                          58814                       # DTB misses
system.cpu0.dtb.accesses                     24487012                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     7918                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7918                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2364                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4650                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          904                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         7014                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1709.295694                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  7049.166862                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6549     93.37%     93.37% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          244      3.48%     96.85% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          111      1.58%     98.43% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           40      0.57%     99.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           16      0.23%     99.23% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           20      0.29%     99.52% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            6      0.09%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535           11      0.16%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            6      0.09%     99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.06%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-106495            3      0.04%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::114688-122879            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         7014                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3153                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12090.865842                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9887.284211                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7911.936320                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2500     79.29%     79.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          629     19.95%     99.24% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.60%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            3      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::114688-131071            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3153                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  43016532284                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.690427                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.462733                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    13322631928     30.97%     30.97% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    29689752356     69.02%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2941500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         833500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         255500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          93500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6          24000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  43016532284                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1677     74.57%     74.57% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          572     25.43%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2249                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7918                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7918                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2249                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2249                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10167                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20135553                       # ITB inst hits
system.cpu0.itb.inst_misses                      7918                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2166                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1314                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20143471                       # ITB inst accesses
system.cpu0.itb.hits                         20135553                       # DTB hits
system.cpu0.itb.misses                           7918                       # DTB misses
system.cpu0.itb.accesses                     20143471                       # DTB accesses
system.cpu0.numCycles                       111793147                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39618267                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     104005693                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26582301                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19041464                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     66973533                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3106371                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    109142                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                4323                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              492                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       147946                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       134023                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          629                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20133698                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               348335                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   4138                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         108541503                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.150586                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.270795                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                79990694     73.70%     73.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3816909      3.52%     77.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2386840      2.20%     79.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8006128      7.38%     86.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1535692      1.41%     88.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1070295      0.99%     89.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6024989      5.55%     94.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1046446      0.96%     95.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4663510      4.30%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           108541503                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.237781                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.930341                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27078357                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             63118683                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15442618                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1487824                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1413697                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1876108                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               141386                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              86216951                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               468944                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1413697                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27917312                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6737317                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      45777609                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16085983                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10609270                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              82519213                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1975                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1079762                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                279653                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8498365                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84889546                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            380829987                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        92265906                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6437                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72096231                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12793299                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1560839                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1462535                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8709532                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14755108                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11569793                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          2006584                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2797109                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  79506629                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1117012                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 76470203                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            91035                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10513087                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23255127                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        107098                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    108541503                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.704525                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.408140                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           78039194     71.90%     71.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10217369      9.41%     81.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7697876      7.09%     88.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6506516      5.99%     94.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2324489      2.14%     96.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1523922      1.40%     97.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1470166      1.35%     99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             496796      0.46%     99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             265175      0.24%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      108541503                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 114394     10.01%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                533468     46.67%     56.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               495163     43.32%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             1057      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             50961896     66.64%     66.64% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57056      0.07%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4042      0.01%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14381965     18.81%     85.53% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           11064184     14.47%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              76470203                       # Type of FU issued
system.cpu0.iq.rate                          0.684033                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1143026                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014947                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         262701898                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         91181243                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     74205181                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              14072                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              8084                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6077                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              77604626                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7546                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          356476                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2025396                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2046                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        53693                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1019422                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       206190                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       120975                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1413697                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5422271                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1092121                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80743722                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           103923                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14755108                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11569793                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            575298                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 45368                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1034932                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         53693                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        203963                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       218205                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              422168                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             75920997                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14162652                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           490566                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       120081                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25131819                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14053120                       # Number of branches executed
system.cpu0.iew.exec_stores                  10969167                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.679120                       # Inst execution rate
system.cpu0.iew.wb_sent                      75353130                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     74211258                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38909862                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 67987561                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.663827                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.572309                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10505736                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1009914                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           355428                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    106122323                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.661384                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.563144                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     78982453     74.43%     74.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12211696     11.51%     85.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6095376      5.74%     91.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2654698      2.50%     94.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1273985      1.20%     95.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       842007      0.79%     96.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1777365      1.67%     97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       427049      0.40%     98.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1857694      1.75%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    106122323                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            57860770                       # Number of instructions committed
system.cpu0.commit.committedOps              70187602                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23280083                       # Number of memory references committed
system.cpu0.commit.loads                     12729712                       # Number of loads committed
system.cpu0.commit.membars                     412824                       # Number of memory barriers committed
system.cpu0.commit.branches                  13343572                       # Number of branches committed
system.cpu0.commit.fp_insts                      5690                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61639242                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2627168                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        46847826     66.75%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55651      0.08%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4042      0.01%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12729712     18.14%     84.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10550371     15.03%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70187602                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1857694                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   172582589                       # The number of ROB reads
system.cpu0.rob.rob_writes                  163805074                       # The number of ROB writes
system.cpu0.timesIdled                         387475                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3251644                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2095657765                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   57783718                       # Number of Instructions Simulated
system.cpu0.committedOps                     70110550                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.934682                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.934682                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.516881                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.516881                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                82769836                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47340037                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16967                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13430                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                268235222                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27675650                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              149360983                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                774294                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           854223                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.975115                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42339802                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           854735                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.535589                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        151893500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   245.630516                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   266.344600                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.479747                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.520204                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189188933                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189188933                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12328240                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12835653                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25163893                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7920383                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      7983564                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15903947                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       182811                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180265                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       363076                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       228283                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       217996                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446279                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       234405                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       224906                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459311                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20248623                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20819217                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41067840                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20431434                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     20999482                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41430916                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       442900                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       397658                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       840558                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1859287                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1835881                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3695168                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       116986                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66485                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183471                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13472                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14295                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27767                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           32                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           43                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           75                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2302187                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2233539                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4535726                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2419173                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2300024                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4719197                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7358360000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7222407500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14580767500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 134221650085                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 118315842261                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252537492346                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    214336000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    197120000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    411456000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       910500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1874000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      2784500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 141580010085                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 125538249761                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267118259846                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 141580010085                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 125538249761                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267118259846                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12771140                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13233311                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26004451                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9779670                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9819445                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19599115                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       299797                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246750                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       546547                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       241755                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       232291                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474046                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       234437                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       224949                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459386                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22550810                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23052756                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45603566                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22850607                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23299506                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46150113                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034680                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030050                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032324                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.190118                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.186964                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188537                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.390217                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.269443                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335691                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055726                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061539                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058574                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000136                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000191                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000163                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102089                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096888                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099460                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.105869                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098716                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102258                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16614.043802                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18162.359364                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17346.533493                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 72189.850241                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 64446.356959                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68342.628088                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15909.738717                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13789.436866                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14818.165448                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28453.125000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 43581.395349                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 37126.666667                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61498.049500                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56205.980626                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58892.062670                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 58524.136176                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 54581.278178                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56602.481279                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1652801                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       341100                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            53373                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2981                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.966987                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   114.424690                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       704221                       # number of writebacks
system.cpu0.dcache.writebacks::total           704221                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       232430                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       181638                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       414068                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1709286                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1686419                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3395705                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8906                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9969                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18875                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1941716                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1868057                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3809773                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1941716                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1868057                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3809773                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210470                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216020                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426490                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       150001                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149462                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299463                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74238                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48665                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122903                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4566                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4326                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8892                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           32                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           43                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           75                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       360471                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       365482                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       725953                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       434709                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       414147                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       848856                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14976                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16153                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15353                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12235                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30329                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28388                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3376686000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3344381500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6721067500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10980513336                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10043251436                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21023764772                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1117542000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    750771500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1868313500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     92062500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58470500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    150533000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       878500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1831000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2709500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14357199336                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13387632936                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  27744832272                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15474741336                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14138404436                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29613145772                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3016953500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3284093000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301046500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3016953500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3284093000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6301046500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016480                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016324                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016401                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015338                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015221                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.247628                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.197224                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224872                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018887                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018623                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018758                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000136                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000191                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000163                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015985                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015854                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015919                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019024                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017775                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018393                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16043.550150                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15481.814184                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.027175                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73202.934220                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67196.019296                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70204.882647                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15053.503597                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15427.339977                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15201.528848                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20162.614980                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.065650                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16929.037337                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27453.125000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 42581.395349                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36126.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39828.999659                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36630.074630                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38218.496613                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35597.931803                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34138.613671                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34885.947407                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201452.557425                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203311.644896                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.247583                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 99474.216097                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115685.958856                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107312.132772                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          1940234                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.477808                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38724516                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1940746                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            19.953418                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11116168500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   198.827128                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   312.650680                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.388334                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.610646                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998980                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42755477                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42755477                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19119275                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19605241                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38724516                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19119275                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19605241                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38724516                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19119275                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19605241                       # number of overall hits
system.cpu0.icache.overall_hits::total       38724516                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1013751                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1076327                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2090078                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1013751                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1076327                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2090078                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1013751                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1076327                       # number of overall misses
system.cpu0.icache.overall_misses::total      2090078                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14430104978                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15364755477                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  29794860455                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14430104978                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  15364755477                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  29794860455                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14430104978                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  15364755477                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  29794860455                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20133026                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20681568                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40814594                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20133026                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20681568                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40814594                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20133026                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20681568                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40814594                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050353                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052043                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051209                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050353                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052043                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051209                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050353                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052043                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051209                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14234.368181                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14275.174252                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14255.382074                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14234.368181                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14275.174252                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14255.382074                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14234.368181                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14275.174252                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14255.382074                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        21109                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              839                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.159714                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1940234                       # number of writebacks
system.cpu0.icache.writebacks::total          1940234                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        72829                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76365                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       149194                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        72829                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76365                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       149194                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        72829                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76365                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       149194                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       940922                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       999962                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1940884                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       940922                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       999962                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1940884                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       940922                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       999962                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1940884                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12649517983                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13451239983                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  26100757966                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12649517983                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13451239983                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  26100757966                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12649517983                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13451239983                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  26100757966                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     85612500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     85612500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     85612500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     85612500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047554                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047554                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047554                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13447.871159                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13447.871159                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13447.871159                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 128354.572714                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 128354.572714                       # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups               27807268                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14522614                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           521884                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17250489                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                8558251                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            49.611643                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6837595                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             30253                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4638011                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           4524834                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          113177                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        32246                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    59403                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               59403                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19503                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14179                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25721                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33682                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   625.541832                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  4121.027251                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        33293     98.85%     98.85% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          302      0.90%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           51      0.15%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33682                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        13282                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14572.202981                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12211.597102                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8282.780589                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         9027     67.96%     67.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767         3941     29.67%     97.64% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151          289      2.18%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535           20      0.15%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-98303            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-114687            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        13282                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  93940791836                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.786357                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.432735                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  93856164336     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     59118500      0.06%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     13540500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4598500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2377500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1150500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       641500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      2158000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       464500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       154000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21       113500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        32000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       104000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        24000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29        20500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31       130000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  93940791836                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3783     68.79%     68.79% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1716     31.21%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5499                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59403                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59403                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5499                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5499                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        64902                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14363291                       # DTB read hits
system.cpu1.dtb.read_misses                     51304                       # DTB read misses
system.cpu1.dtb.write_hits                   10466548                       # DTB write hits
system.cpu1.dtb.write_misses                     8099                       # DTB write misses
system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3703                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      789                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1302                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      692                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14414595                       # DTB read accesses
system.cpu1.dtb.write_accesses               10474647                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24829839                       # DTB hits
system.cpu1.dtb.misses                          59403                       # DTB misses
system.cpu1.dtb.accesses                     24889242                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     8176                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                8176                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2725                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4550                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          901                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7275                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1291.065292                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  5441.618044                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         6876     94.52%     94.52% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          235      3.23%     97.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575           98      1.35%     99.09% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           22      0.30%     99.40% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           16      0.22%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           13      0.18%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343            4      0.05%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            4      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::90112-98303            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7275                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         3329                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13317.062181                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11226.218881                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7219.287794                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095           33      0.99%      0.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          951     28.57%     29.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          591     17.75%     47.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          974     29.26%     76.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           56      1.68%     78.25% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575          639     19.19%     97.45% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           50      1.50%     98.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            7      0.21%     99.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            8      0.24%     99.40% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            9      0.27%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            7      0.21%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.03%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         3329                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  16626242508                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.560807                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.496851                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     7305801500     43.94%     43.94% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1     9317469508     56.04%     99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2523000      0.02%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         191000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         257500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  16626242508                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1825     75.16%     75.16% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          603     24.84%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2428                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8176                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8176                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2428                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2428                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10604                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20684254                       # ITB inst hits
system.cpu1.itb.inst_misses                      8176                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2403                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1403                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20692430                       # ITB inst accesses
system.cpu1.itb.hits                         20684254                       # DTB hits
system.cpu1.itb.misses                           8176                       # DTB misses
system.cpu1.itb.accesses                     20692430                       # DTB accesses
system.cpu1.numCycles                       114171883                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          41307055                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     106903297                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27807268                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19920680                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     67458241                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3216021                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    121509                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              400                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       160606                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       131997                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          578                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20681575                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               364929                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   4168                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         110795501                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.160287                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.270583                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                81287702     73.37%     73.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3968445      3.58%     76.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2465737      2.23%     79.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8227247      7.43%     86.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1665467      1.50%     88.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1110283      1.00%     89.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6325144      5.71%     94.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1155008      1.04%     95.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4590468      4.14%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           110795501                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.243556                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.936336                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                28346426                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             63534954                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15742282                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1712283                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1459261                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1949115                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               150539                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              88605226                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               497888                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1459261                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                29272328                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                6824679                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46697941                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16517482                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             10023500                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              84831585                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 5826                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1700956                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                268416                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               7295598                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           88095005                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            390290446                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94261831                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6556                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             74597964                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13497041                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1571787                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1475121                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  9868182                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15213702                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11513965                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2143340                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2824110                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  81772790                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1092881                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78357937                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            92895                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11062256                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24614502                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        108703                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    110795501                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.707230                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.397571                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           79253115     71.53%     71.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10577284      9.55%     81.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8128095      7.34%     88.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6656902      6.01%     94.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2466913      2.23%     96.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1485866      1.34%     97.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1541530      1.39%     99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             478773      0.43%     99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             207023      0.19%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      110795501                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  96333      8.58%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     5      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                530832     47.29%     55.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               495255     44.12%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             1280      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52536411     67.05%     67.05% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59049      0.08%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4537      0.01%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14749265     18.82%     85.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11007390     14.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78357937                       # Type of FU issued
system.cpu1.iq.rate                          0.686316                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1122425                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014324                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268712676                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         93970035                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     76074139                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14019                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8104                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6058                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79471535                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7547                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          353893                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2138712                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2178                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51387                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1026051                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       208095                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        80598                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1459261                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5474450                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1047007                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           82982431                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           112348                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15213702                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11513965                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            559325                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44311                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               989592                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51387                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        224281                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       227429                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              451710                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77795994                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14521150                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           502664                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       116760                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25431924                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14791580                       # Number of branches executed
system.cpu1.iew.exec_stores                  10910774                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.681394                       # Inst execution rate
system.cpu1.iew.wb_sent                      77262283                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     76080197                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39863669                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69476168                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.666365                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.573775                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       11052926                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         984178                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           373097                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    108271763                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.663897                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.547392                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     80200179     74.07%     74.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12516978     11.56%     85.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6520368      6.02%     91.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2652401      2.45%     94.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1417496      1.31%     95.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       923552      0.85%     96.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1918077      1.77%     98.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       411551      0.38%     98.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1711161      1.58%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    108271763                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            59217112                       # Number of instructions committed
system.cpu1.commit.committedOps              71881268                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23562904                       # Number of memory references committed
system.cpu1.commit.loads                     13074990                       # Number of loads committed
system.cpu1.commit.membars                     401228                       # Number of memory barriers committed
system.cpu1.commit.branches                  14038691                       # Number of branches committed
system.cpu1.commit.fp_insts                      5738                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62807538                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2710976                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        48256450     67.13%     67.13% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57377      0.08%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4537      0.01%     67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13074990     18.19%     85.41% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10487914     14.59%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71881268                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1711161                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   176735150                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168391360                       # The number of ROB writes
system.cpu1.timesIdled                         416029                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        3376382                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3313480178                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   59139259                       # Number of Instructions Simulated
system.cpu1.committedOps                     71803415                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.930560                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.930560                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.517984                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.517984                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84439414                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48406893                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    17104                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13298                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                275043982                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29275058                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              152546731                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                745677                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49489000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               335500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               612500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6433500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38433500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187130237                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36423                       # number of replacements
system.iocache.tags.tagsinuse                1.038891                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         236424190000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.038891                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064931                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064931                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
system.iocache.tags.data_accesses              328113                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36457                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36457                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36457                       # number of overall misses
system.iocache.overall_misses::total            36457                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30201377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30201377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4553154860                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4553154860                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4583356237                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4583356237                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4583356237                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4583356237                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36457                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36457                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36457                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36457                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129619.643777                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129619.643777                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125694.425243                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125694.425243                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125719.511671                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125719.511671                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125719.511671                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125719.511671                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36457                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36457                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36457                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36457                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18551377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18551377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2740534329                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2740534329                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2759085706                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2759085706                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2759085706                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2759085706                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79619.643777                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79619.643777                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75655.210054                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75655.210054                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75680.547110                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75680.547110                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75680.547110                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75680.547110                       # average overall mshr miss latency
system.l2c.tags.replacements                   104324                       # number of replacements
system.l2c.tags.tagsinuse                65103.705276                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5150799                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169522                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.384251                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              74565493500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48889.400560                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    39.621431                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000315                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5209.577965                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3051.295581                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    57.223536                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5380.787536                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2475.798353                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.745993                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000605                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.079492                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.046559                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000873                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.082104                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.037778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993404                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           95                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65103                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           95                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3204                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8943                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52585                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001450                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.993393                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45530803                       # Number of tag accesses
system.l2c.tags.data_accesses                45530803                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        34635                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6743                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        37358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7553                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  86289                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       704221                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          704221                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1901578                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1901578                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              58                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              72                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 130                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            25                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                49                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            74630                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            82104                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156734                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        930758                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        988927                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1919685                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       280791                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       262096                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           542887                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         34635                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6743                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              930758                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              355421                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         37358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7553                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              988927                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              344200                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2705595                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        34635                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6743                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             930758                       # number of overall hits
system.l2c.overall_hits::cpu0.data             355421                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        37358                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7553                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             988927                       # number of overall hits
system.l2c.overall_hits::cpu1.data             344200                       # number of overall hits
system.l2c.overall_hits::total                2705595                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           59                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           76                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  136                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1494                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1371                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2865                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            7                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           19                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              26                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73838                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          65928                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139766                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        10008                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10799                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20807                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8464                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         6902                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15366                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           59                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             10008                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             82302                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           76                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10799                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             72830                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176075                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           59                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            10008                       # number of overall misses
system.l2c.overall_misses::cpu0.data            82302                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           76                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10799                       # number of overall misses
system.l2c.overall_misses::cpu1.data            72830                       # number of overall misses
system.l2c.overall_misses::total               176075                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      8367000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     10398500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       18898000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1170500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1793500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2964000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        77500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       709000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       786500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9841436000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8835802500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18677238500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1342423500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1437498498                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2779921998                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1153652000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    952961500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2106613500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      8367000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1342423500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  10995088000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     10398500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1437498498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9788764000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23582671998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      8367000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1342423500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  10995088000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     10398500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1437498498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9788764000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23582671998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        34694                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6744                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        37434                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7553                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              86425                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       704221                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       704221                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1901578                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1901578                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1552                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1443                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2995                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           32                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           43                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            75                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       148468                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       148032                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296500                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       940766                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       999726                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1940492                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       289255                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       268998                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       558253                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        34694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6744                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          940766                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          437723                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        37434                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7553                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          999726                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          417030                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2881670                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        34694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6744                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         940766                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         437723                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        37434                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7553                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         999726                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         417030                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2881670                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001701                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000148                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002030                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001574                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962629                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.950104                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.956594                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.218750                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.441860                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.346667                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.497333                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.445363                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.471386                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010638                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010802                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010723                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029261                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.025658                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027525                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001701                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000148                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010638                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.188023                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.002030                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010802                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.174640                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061102                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001701                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000148                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010638                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.188023                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.002030                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010802                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.174640                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061102                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 141813.559322                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136822.368421                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 138955.882353                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   783.467202                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1308.169220                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1034.554974                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11071.428571                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 37315.789474                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        30250                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133284.162626                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134022.001274                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 133632.203111                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 134135.041966                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 133114.038152                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133605.132792                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136301.039698                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138070.341930                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 137095.763374                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141813.559322                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134135.041966                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133594.420549                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136822.368421                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133114.038152                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134405.657009                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 133935.379798                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141813.559322                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134135.041966                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133594.420549                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136822.368421                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133114.038152                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134405.657009                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 133935.379798                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               95788                       # number of writebacks
system.l2c.writebacks::total                    95788                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           67                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           76                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          143                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             67                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             76                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                154                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            67                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            76                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               154                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           59                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           76                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             136                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1494                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1371                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2865                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           19                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           26                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73838                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        65928                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139766                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10001                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10795                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20796                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8397                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6826                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15223                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           59                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        10001                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        82235                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           76                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10795                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        72754                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           175921                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           59                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        10001                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        82235                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           76                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10795                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        72754                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          175921                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14976                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16153                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31796                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15353                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12235                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30329                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        28388                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59384                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7777000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9638500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17538000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    101680000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     93227000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    194907000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       476500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1301000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1777500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9103056000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8176522500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  17279578500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1242027505                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1328983000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2571010505                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1061729002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    875386503                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1937115505                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      7777000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1242027505                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  10164785002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      9638500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1328983000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   9051909003                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21805242510                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      7777000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1242027505                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  10164785002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      9638500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1328983000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   9051909003                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21805242510                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     75239000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2829703000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3082124500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5987066500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     75239000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2829703000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3082124500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5987066500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001701                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000148                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002030                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001574                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.962629                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.950104                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.956594                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.218750                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.441860                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.346667                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.497333                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.445363                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.471386                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010631                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010798                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010717                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.029030                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025376                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027269                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001701                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000148                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010631                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.187870                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002030                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010798                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.174457                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061048                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001701                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000148                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010631                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.187870                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002030                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010798                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.174457                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061048                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 131813.559322                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126822.368421                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 128955.882353                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68058.902276                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67999.270605                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68030.366492                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68071.428571                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68473.684211                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68365.384615                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123284.162626                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124022.001274                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123632.203111                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124190.331467                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 123110.977304                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123630.049288                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126441.467429                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128242.968503                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127249.261315                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131813.559322                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124190.331467                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123606.554411                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126822.368421                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123110.977304                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124418.025167                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123949.059578                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131813.559322                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124190.331467                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123606.554411                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126822.368421                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123110.977304                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124418.025167                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123949.059578                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112802.098951                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188949.185363                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190808.178047                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188296.216505                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112802.098951                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 93300.240694                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 108571.385797                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 100819.522093                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               31796                       # Transaction distribution
system.membus.trans_dist::ReadResp              68183                       # Transaction distribution
system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131978                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8769                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4666                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137965                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137965                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36388                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       575742                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 648637                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17317788                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17481845                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19798965                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              501                       # Total snoops (count)
system.membus.snoop_fanout::samples            415426                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  415426    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              415426                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95665000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1698498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           923038607                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1006596250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1263123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5631885                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2836272                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        46849                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            558                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          558                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             150344                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2649691                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       836223                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1940234                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          158771                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2995                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            75                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           3070                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296500                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296500                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1940884                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       558486                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5822943                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2687514                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37786                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       167187                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8715430                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    248409088                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99970933                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        57188                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       288512                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              348725721                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          209954                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3153965                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027355                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.163116                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                3067688     97.26%     97.26% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  86277      2.74%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3153965                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5543895402                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           377377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2914118404                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1329027112                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          23521931                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          95501099                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------