path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.823470                       # Number of seconds simulated
sim_ticks                                2823469739500                       # Number of ticks simulated
final_tick                               2823469739500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 118468                       # Simulator instruction rate (inst/s)
host_op_rate                                   143788                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2861405792                       # Simulator tick rate (ticks/s)
host_mem_usage                                 590036                       # Number of bytes of host memory used
host_seconds                                   986.74                       # Real time elapsed on the host
sim_insts                                   116897717                       # Number of instructions simulated
sim_ops                                     141881589                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         3648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           661824                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5279456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         5184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           711040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4517256                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11179432                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       661824                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       711040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1372864                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8427776                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8445300                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           57                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10341                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             83010                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           81                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             11110                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             70584                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175199                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131684                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136065                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1292                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              234401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1869847                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1836                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              251832                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1599895                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3959466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         234401                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         251832                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             486233                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2984900                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2991107                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2984900                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1292                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             234401                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1876051                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1836                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             251832                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1599898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6950573                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175200                       # Number of read requests accepted
system.physmem.writeReqs                       136065                       # Number of write requests accepted
system.physmem.readBursts                      175200                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     136065                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11204096                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8457920                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11179496                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8445300                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11402                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10980                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11431                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11297                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11015                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10541                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11443                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11405                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11226                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11073                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10487                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10069                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10629                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11393                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10671                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10002                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8635                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8267                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8885                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8812                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7853                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7875                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8475                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8544                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8488                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8484                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7865                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7711                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8199                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8763                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7974                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7325                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    2823469561500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174644                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131684                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    107528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59207                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6570                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1738                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65621                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      299.627985                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.164139                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.976570                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24746     37.71%     37.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16151     24.61%     62.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6763     10.31%     72.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3694      5.63%     78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2894      4.41%     82.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1678      2.56%     85.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1076      1.64%     86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1118      1.70%     88.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7501     11.43%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65621                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6504                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.912515                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      489.223467                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6502     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6504                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6504                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.319034                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.351442                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.828317                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                14      0.22%      0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 3      0.05%      0.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                6      0.09%      0.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              10      0.15%      0.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5684     87.39%     87.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             149      2.29%     90.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              43      0.66%     90.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              73      1.12%     91.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              39      0.60%     92.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              21      0.32%     92.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              44      0.68%     93.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.12%     93.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             147      2.26%     95.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              14      0.22%     96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              10      0.15%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              16      0.25%     96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              67      1.03%     97.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              29      0.45%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              91      1.40%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             3      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.11%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6504                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2746267751                       # Total ticks spent queuing
system.physmem.totMemAccLat                6028717751                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    875320000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15687.22                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34437.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.99                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.46                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.82                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144099                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97497                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.31                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.76                       # Row buffer hit rate for writes
system.physmem.avgGap                      9070951.00                       # Average gap between requests
system.physmem.pageHitRate                      78.63                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  256253760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  139821000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 698209200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                436402080                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184415044320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80123978880                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1623795284250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1889864993490                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.342266                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2701214527000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94281720000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27969560500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  239841000                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  130865625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 667274400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                419962320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184415044320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79167823830                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1624634016750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1889674828245                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.274915                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2702617863750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94281720000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26569403250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          249                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             249                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26557765                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13711788                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           500128                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            15985074                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12420856                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.702837                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6637719                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             27705                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    56410                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               56410                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17224                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13674                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        25512                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        30898                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   845.750534                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  5234.094520                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        30449     98.55%     98.55% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          313      1.01%     99.56% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           71      0.23%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           28      0.09%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           18      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        30898                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12695                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13609.491926                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11056.421088                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9278.462681                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         9267     73.00%     73.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3157     24.87%     97.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          251      1.98%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            4      0.03%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455           12      0.09%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12695                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  96164849040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.577862                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.515354                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  96082852540     99.91%     99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     55229500      0.06%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     12746000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      5020500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2459000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1673000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1038500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      2619500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       401000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       384500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21        78000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25        82500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        33000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        25000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31       171500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  96164849040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3408     68.65%     68.65% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1556     31.35%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         4964                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56410                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56410                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4964                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4964                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        61374                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13949693                       # DTB read hits
system.cpu0.dtb.read_misses                     47052                       # DTB read misses
system.cpu0.dtb.write_hits                   10497167                       # DTB write hits
system.cpu0.dtb.write_misses                     9358                       # DTB write misses
system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     469                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3271                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      792                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1257                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      589                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                13996745                       # DTB read accesses
system.cpu0.dtb.write_accesses               10506525                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24446860                       # DTB hits
system.cpu0.dtb.misses                          56410                       # DTB misses
system.cpu0.dtb.accesses                     24503270                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     7368                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7368                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2261                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4959                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          148                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         7220                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1816.274238                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  7833.781399                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-16383         6926     95.93%     95.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-32767          219      3.03%     98.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-49151           37      0.51%     99.47% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-65535           15      0.21%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-81919           11      0.15%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-98303            3      0.04%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-114687            3      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::114688-131071            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-147455            2      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::147456-163839            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         7220                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2362                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 14046.570703                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11793.338706                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  8758.063441                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         1730     73.24%     73.24% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          589     24.94%     98.18% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           40      1.69%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2362                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  14560346416                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.888625                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.316568                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1627388500     11.18%     11.18% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    12929178416     88.80%     99.97% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2653000      0.02%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         688000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         200500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5         118000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6          93000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::7          27000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  14560346416                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1654     74.71%     74.71% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          560     25.29%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2214                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7368                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7368                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2214                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2214                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         9582                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20130827                       # ITB inst hits
system.cpu0.itb.inst_misses                      7368                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     469                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2134                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1230                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20138195                       # ITB inst accesses
system.cpu0.itb.hits                         20130827                       # DTB hits
system.cpu0.itb.misses                           7368                       # DTB misses
system.cpu0.itb.accesses                     20138195                       # DTB accesses
system.cpu0.numCycles                       111738620                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39370893                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     103893622                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26557765                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19058575                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     67178812                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3103708                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    121878                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                4445                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              455                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       181503                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       118118                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          630                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20129808                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               348342                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3505                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         108528550                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.150700                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.270125                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                79971422     73.69%     73.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3809838      3.51%     77.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2395726      2.21%     79.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8000248      7.37%     86.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1536985      1.42%     88.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1087405      1.00%     89.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6042952      5.57%     94.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1032695      0.95%     95.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4651279      4.29%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           108528550                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.237678                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.929792                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26850691                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             63349616                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15400515                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1518743                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1408634                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1870918                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               145274                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              86265723                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               468688                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1408634                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27702966                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6709898                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      45858480                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16063551                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10784636                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              82553580                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 2255                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1112646                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                250108                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8658376                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84742438                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            381431947                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        92563624                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             5398                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72236094                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12506336                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1563816                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1466607                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8828288                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14723258                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11669783                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          2112846                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2835315                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  79509095                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1118195                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 76512604                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            87402                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10382395                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23148584                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        102807                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    108528550                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.705000                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.405850                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           77845712     71.73%     71.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10446148      9.63%     81.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7706696      7.10%     88.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6443833      5.94%     94.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2340710      2.16%     96.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1522105      1.40%     97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1475778      1.36%     99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             487012      0.45%     99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             260556      0.24%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      108528550                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 112196      9.79%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                526196     45.92%     55.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               507404     44.28%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass              229      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             50972770     66.62%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56817      0.07%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4037      0.01%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14339886     18.74%     85.44% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           11138856     14.56%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              76512604                       # Type of FU issued
system.cpu0.iq.rate                          0.684746                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1145797                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014975                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         262775124                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         91056518                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     74263785                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11833                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6292                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5221                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              77651808                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6364                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          356016                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1994121                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2352                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54275                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1081195                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       202898                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       121276                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1408634                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5278024                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1213431                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80756832                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           118260                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14723258                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11669783                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            571666                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 45870                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1155376                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54275                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        221116                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       201841                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              422957                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             75956383                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14119834                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           499950                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       129542                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25156609                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14059078                       # Number of branches executed
system.cpu0.iew.exec_stores                  11036775                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.679768                       # Inst execution rate
system.cpu0.iew.wb_sent                      75400529                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     74269006                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38924107                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 68260827                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.664667                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.570226                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10419079                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1015388                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           356870                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    106130883                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.662591                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.560067                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     78790716     74.24%     74.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12390417     11.67%     85.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6092521      5.74%     91.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2656832      2.50%     94.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1363229      1.28%     95.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       834290      0.79%     96.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1725699      1.63%     97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       420589      0.40%     98.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1856590      1.75%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    106130883                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            57976816                       # Number of instructions committed
system.cpu0.commit.committedOps              70321358                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23317725                       # Number of memory references committed
system.cpu0.commit.loads                     12729137                       # Number of loads committed
system.cpu0.commit.membars                     416530                       # Number of memory barriers committed
system.cpu0.commit.branches                  13368661                       # Number of branches committed
system.cpu0.commit.fp_insts                      5158                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61739692                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2627704                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        46944316     66.76%     66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55281      0.08%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4036      0.01%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12729137     18.10%     84.94% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10588588     15.06%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70321358                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1856590                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   172663195                       # The number of ROB reads
system.cpu0.rob.rob_writes                  163882503                       # The number of ROB writes
system.cpu0.timesIdled                         381139                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3210070                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2095442854                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   57900349                       # Number of Instructions Simulated
system.cpu0.committedOps                     70244891                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.929844                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.929844                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.518177                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.518177                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                82925717                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47305162                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16275                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13170                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                268288985                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27711504                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              149937912                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                778798                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           855446                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.968774                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42352962                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           855958                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.480187                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   248.778719                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   263.190055                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.485896                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.514043                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189257101                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189257101                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12292677                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12889220                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25181897                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7937758                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      7960928                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15898686                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       184092                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180023                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       364115                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       230395                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       215508                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       445903                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236843                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       222450                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459293                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20230435                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20850148                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41080583                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20414527                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21030171                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41444698                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       435537                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       405293                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       840830                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1875767                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1821477                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3697244                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117122                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        67245                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       184367                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13669                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14208                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27877                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           34                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           32                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           66                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2311304                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2226770                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4538074                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2428426                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2294015                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4722441                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7243575000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7414080000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14657655000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137609322451                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 115018271250                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252627593701                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    217997500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    196866000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    414863500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       871500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1111000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1982500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 144852897451                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 122432351250                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267285248701                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 144852897451                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 122432351250                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267285248701                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12728214                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13294513                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26022727                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9813525                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9782405                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19595930                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       301214                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       247268                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       548482                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       244064                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       229716                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       473780                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236877                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       222482                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459359                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22541739                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23076918                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45618657                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22842953                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23324186                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46167139                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034218                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030486                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032311                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191141                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.186199                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188674                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.388833                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.271952                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336140                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056006                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061850                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058840                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000144                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000144                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000144                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102534                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096493                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099478                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106310                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098353                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102290                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16631.365418                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18293.136077                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17432.364449                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73361.628844                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63145.607246                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68328.623618                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15948.313703                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13855.996622                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14881.927754                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25632.352941                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 34718.750000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30037.878788                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62671.503814                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 54982.037323                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58898.389207                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59648.882631                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53370.335961                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56598.959881                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1668296                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       342631                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            53683                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           3010                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.076803                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   113.830897                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       705279                       # number of writebacks
system.cpu0.dcache.writebacks::total           705279                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       226700                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       187202                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       413902                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1724389                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1673184                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3397573                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9000                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9812                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18812                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1951089                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1860386                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3811475                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1951089                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1860386                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3811475                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       208837                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       218091                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426928                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151378                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148293                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299671                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        73921                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        49222                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       123143                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4669                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4396                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9065                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           34                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           32                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           66                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       360215                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       366384                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       726599                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       434136                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       415606                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       849742                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14759                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16370                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15231                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12357                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29990                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3332077500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3393296500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6725374000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11184886384                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9853624962                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21038511346                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1108891500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    759475500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1868367000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     93281500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     59417500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    152699000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       837500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1079000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1916500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14516963884                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13246921462                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  27763885346                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15625855384                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14006396962                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29632252346                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2963964500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3337097500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301062000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2593528424                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2490666452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084194876                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5557492924                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5827763952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385256876                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016407                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016405                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016406                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015425                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015159                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015293                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.245410                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.199063                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224516                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019130                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019137                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019133                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000144                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000144                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000144                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015980                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015877                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015928                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019005                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017819                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018406                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15955.398229                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15559.085428                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15752.946633                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73887.132767                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66446.999939                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70205.363035                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15001.034889                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15429.594490                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15172.336227                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19978.903405                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.264786                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16844.897959                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24632.352941                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33718.750000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29037.878788                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40300.831126                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36155.840490                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38210.739825                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35992.996167                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33701.142337                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34872.058044                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200824.208957                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203854.459377                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.745511                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170279.589259                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201559.152869                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.085399                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185311.534645                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202867.126814                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193900.520735                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1935383                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.471478                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38825027                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1935895                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.055337                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11154875500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   204.816833                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.654644                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400033                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598935                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998968                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          140                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42844828                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42844828                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19123752                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19701275                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38825027                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19123752                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19701275                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38825027                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19123752                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19701275                       # number of overall hits
system.cpu0.icache.overall_hits::total       38825027                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1005384                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1078455                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2083839                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1005384                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1078455                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2083839                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1005384                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1078455                       # number of overall misses
system.cpu0.icache.overall_misses::total      2083839                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14269626482                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15427948989                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  29697575471                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14269626482                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  15427948989                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  29697575471                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14269626482                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  15427948989                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  29697575471                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20129136                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20779730                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40908866                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20129136                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20779730                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40908866                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20129136                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20779730                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40908866                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.049947                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051899                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050939                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.049947                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.051899                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050939                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.049947                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051899                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050939                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14193.210238                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14305.602912                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14251.377132                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14193.210238                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14305.602912                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14251.377132                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14193.210238                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14305.602912                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14251.377132                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        20209                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              793                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.484237                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1935383                       # number of writebacks
system.cpu0.icache.writebacks::total          1935383                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71315                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76561                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       147876                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71315                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76561                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       147876                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71315                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76561                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       147876                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       934069                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1001894                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1935963                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       934069                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1001894                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1935963                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       934069                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1001894                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1935963                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12517523985                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13510096493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  26027620478                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12517523985                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13510096493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  26027620478                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12517523985                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13510096493                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  26027620478                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86506500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     86506500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046404                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048215                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047324                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046404                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048215                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047324                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046404                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048215                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047324                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13401.069926                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13484.556743                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.275783                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13401.069926                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13484.556743                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.275783                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13401.069926                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13484.556743                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.275783                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27845769                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14562032                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           548670                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17327416                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               13125788                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            75.751560                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6844508                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29088                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    58263                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58263                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19122                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13746                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25395                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        32868                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   735.822076                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  5166.451241                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32439     98.69%     98.69% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          307      0.93%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           56      0.17%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           28      0.09%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           13      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            7      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            6      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        32868                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        13303                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14575.358942                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12191.227269                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8603.178174                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        12998     97.71%     97.71% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535          295      2.22%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303            7      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        13303                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  91468436244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.768300                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.445212                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  91380739744     99.90%     99.90% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     61381000      0.07%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     13682000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4674500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2423500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1725000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       730000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      2073000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       390500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       252000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21        85000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        23000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       127500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        26000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29        16000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31        87500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  91468436244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3764     68.66%     68.66% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1718     31.34%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5482                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58263                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58263                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5482                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5482                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        63745                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14429074                       # DTB read hits
system.cpu1.dtb.read_misses                     50206                       # DTB read misses
system.cpu1.dtb.write_hits                   10478740                       # DTB write hits
system.cpu1.dtb.write_misses                     8057                       # DTB write misses
system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     448                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3590                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      793                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1278                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      676                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14479280                       # DTB read accesses
system.cpu1.dtb.write_accesses               10486797                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24907814                       # DTB hits
system.cpu1.dtb.misses                          58263                       # DTB misses
system.cpu1.dtb.accesses                     24966077                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     7966                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7966                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2733                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         5041                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          192                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7774                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1441.214304                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6187.766292                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         7329     94.28%     94.28% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          184      2.37%     96.64% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575          160      2.06%     98.70% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           32      0.41%     99.11% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           22      0.28%     99.40% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           15      0.19%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343           13      0.17%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535           10      0.13%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.06%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7774                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2664                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 14886.824324                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12507.436482                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8471.321316                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          630     23.65%     23.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1227     46.06%     69.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          650     24.40%     94.11% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           95      3.57%     97.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           18      0.68%     98.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151           35      1.31%     99.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.15%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535            3      0.11%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2664                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  31323904600                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.850464                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.357128                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     4688399000     14.97%     14.97% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    26632295600     85.02%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2300000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         720500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         157500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          32000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  31323904600                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1884     76.21%     76.21% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          588     23.79%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2472                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7966                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7966                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2472                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2472                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10438                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20781807                       # ITB inst hits
system.cpu1.itb.inst_misses                      7966                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     448                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2418                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1467                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20789773                       # ITB inst accesses
system.cpu1.itb.hits                         20781807                       # DTB hits
system.cpu1.itb.misses                           7966                       # DTB misses
system.cpu1.itb.accesses                     20789773                       # DTB accesses
system.cpu1.numCycles                       114304919                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          41262739                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     107285498                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27845769                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19970296                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     67416194                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3259780                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    133608                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                6817                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              414                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       250513                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       129856                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          415                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20779736                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               377856                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3597                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         110830408                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.164170                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.274550                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                81247279     73.31%     73.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3969752      3.58%     76.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2463714      2.22%     79.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8233608      7.43%     86.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1683058      1.52%     88.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1119193      1.01%     89.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6323043      5.71%     94.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1165134      1.05%     95.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4625627      4.17%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           110830408                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.243610                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.938590                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                28323614                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             63478712                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15848046                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1704488                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1475224                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1967997                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               156746                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              89079205                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               507140                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1475224                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                29256624                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                7018147                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46666766                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16607219                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              9806111                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              85232877                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 3842                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1674461                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                301333                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               7083529                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           88409572                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            391941986                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94718838                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6483                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             74424798                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13984774                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1569429                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1471935                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  9797660                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15298042                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11560096                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2146916                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2735796                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  82036026                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1094252                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78550725                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            92381                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11493580                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     25147781                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        115638                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    110830408                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.708747                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.399658                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           79265861     71.52%     71.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10536379      9.51%     81.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8138054      7.34%     88.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6692872      6.04%     94.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2461657      2.22%     96.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1496595      1.35%     97.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1550739      1.40%     99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             480423      0.43%     99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             207828      0.19%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      110830408                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 101678      9.04%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                527402     46.88%     55.91% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               496001     44.09%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             2108      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52628627     67.00%     67.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59575      0.08%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   2      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4540      0.01%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14828760     18.88%     85.96% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11027108     14.04%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78550725                       # Type of FU issued
system.cpu1.iq.rate                          0.687203                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1125087                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014323                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         269134534                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         94666903                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     76208953                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14792                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7758                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6343                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79665710                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7994                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          356293                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2229171                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2454                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        52006                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1113437                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       210295                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        83250                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1475224                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5653041                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1062018                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           83263917                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           132733                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15298042                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11560096                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            563089                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44760                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1004107                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         52006                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        252720                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       221535                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              474255                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77947224                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14588142                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           545356                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       133639                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25509801                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14792912                       # Number of branches executed
system.cpu1.iew.exec_stores                  10921659                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.681924                       # Inst execution rate
system.cpu1.iew.wb_sent                      77399015                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     76215296                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39901204                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69370380                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.666772                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.575191                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       11469424                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         978614                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           393966                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    108251669                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.662485                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.545489                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     80229014     74.11%     74.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12491692     11.54%     85.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6522560      6.03%     91.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2655731      2.45%     94.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1400574      1.29%     95.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       922085      0.85%     96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1916585      1.77%     98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       408524      0.38%     98.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1704904      1.57%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    108251669                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            59075806                       # Number of instructions committed
system.cpu1.commit.committedOps              71715136                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23515530                       # Number of memory references committed
system.cpu1.commit.loads                     13068871                       # Number of loads committed
system.cpu1.commit.membars                     397484                       # Number of memory barriers committed
system.cpu1.commit.branches                  14003876                       # Number of branches committed
system.cpu1.commit.fp_insts                      6270                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62677784                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2707088                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        48137267     67.12%     67.12% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57800      0.08%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4539      0.01%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13068871     18.22%     85.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10446659     14.57%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71715136                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1704904                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   176979703                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168952003                       # The number of ROB writes
system.cpu1.timesIdled                         412631                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        3474511                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3325420537                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   58997368                       # Number of Instructions Simulated
system.cpu1.committedOps                     71636698                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.937458                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.937458                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.516140                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.516140                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84576354                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48518132                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    17186                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13576                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                275590302                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29300189                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              152556946                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                741089                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49499000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               333000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                86000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               613000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6444000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38197000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187138887                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36413                       # number of replacements
system.iocache.tags.tagsinuse                1.069482                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         236543521000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.069482                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.066843                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.066843                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
system.iocache.tags.data_accesses              328023                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          223                       # number of overall misses
system.iocache.overall_misses::total              223                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28108377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28108377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4550219510                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4550219510                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28108377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28108377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28108377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28108377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126046.533632                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125613.391950                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125613.391950                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126046.533632                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126046.533632                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16958377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16958377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737617166                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2737617166                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16958377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16958377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16958377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16958377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75574.678832                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75574.678832                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104258                       # number of replacements
system.l2c.tags.tagsinuse                65109.968422                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5143670                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169575                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.332714                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              74702530500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48981.284671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    35.148352                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000314                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4875.960146                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2904.898694                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    61.768888                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5697.678778                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2553.228578                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.747395                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000536                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074401                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.044325                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000943                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.086940                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.038959                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993499                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65233                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           84                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3237                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9000                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52639                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001282                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995377                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45464154                       # Number of tag accesses
system.l2c.tags.data_accesses                45464154                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        34252                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7496                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36721                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         8197                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  86666                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       705279                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          705279                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1894881                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1894881                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              44                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              43                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  87                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            28                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            22                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            74636                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            82245                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156881                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        924234                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        990635                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1914869                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       279153                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       264599                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           543752                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         34252                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7496                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              924234                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              353789                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36721                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          8197                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              990635                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              346844                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2702168                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        34252                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7496                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             924234                       # number of overall hits
system.l2c.overall_hits::cpu0.data             353789                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36721                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         8197                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             990635                       # number of overall hits
system.l2c.overall_hits::cpu1.data             346844                       # number of overall hits
system.l2c.overall_hits::total                2702168                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           57                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           81                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  139                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1408                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1323                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2731                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            6                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           10                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              16                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          75306                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          64702                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140008                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         9696                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        11114                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20810                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8258                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         7090                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15348                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           57                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9696                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             83564                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           81                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             11114                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             71792                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176305                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           57                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9696                       # number of overall misses
system.l2c.overall_misses::cpu0.data            83564                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           81                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            11114                       # number of overall misses
system.l2c.overall_misses::cpu1.data            71792                       # number of overall misses
system.l2c.overall_misses::total               176305                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      8272000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     11019000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       19423500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1637500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1712500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      3350000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       237500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       627500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       865000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  10051279000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8650358500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18701637500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1291659500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1477796499                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2769455999                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1119203500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    978588000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2097791500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      8272000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1291659500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  11170482500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     11019000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1477796499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9628946500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23588308499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      8272000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1291659500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  11170482500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     11019000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1477796499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9628946500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23588308499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        34309                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7497                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36802                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         8197                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              86805                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       705279                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       705279                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1894881                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1894881                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1452                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1366                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2818                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           34                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           32                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            66                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       149942                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       146947                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296889                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       933930                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1001749                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1935679                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       287411                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       271689                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       559100                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        34309                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7497                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          933930                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          437353                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36802                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         8197                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1001749                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          418636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2878473                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        34309                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7497                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         933930                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         437353                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36802                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         8197                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1001749                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         418636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2878473                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001661                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000133                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002201                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001601                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.969697                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.968521                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.969127                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.176471                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.312500                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.242424                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.502234                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.440308                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.471584                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010382                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011095                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010751                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028732                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.026096                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027451                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001661                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000133                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010382                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.191068                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.002201                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011095                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.171490                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061249                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001661                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000133                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010382                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.191068                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.002201                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011095                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.171490                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061249                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 145122.807018                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136037.037037                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 139737.410072                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1162.997159                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1294.406652                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1226.656902                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 39583.333333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        62750                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 54062.500000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133472.485592                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133695.380359                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 133575.492115                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133215.707508                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132967.113461                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133082.940846                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 135529.607653                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138023.695346                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 136681.750065                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 145122.807018                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133215.707508                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133675.775454                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136037.037037                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132967.113461                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134122.834021                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 133792.623573                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 145122.807018                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133215.707508                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133675.775454                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136037.037037                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132967.113461                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134122.834021                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 133792.623573                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95494                       # number of writebacks
system.l2c.writebacks::total                    95494                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           65                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           80                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          145                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             65                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             80                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                158                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            65                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            80                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               158                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           57                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           81                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             139                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1408                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1323                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2731                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           10                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           16                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        75306                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        64702                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140008                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         9687                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        11110                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20797                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8193                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         7010                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15203                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           57                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         9687                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        83499                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           81                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        11110                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        71712                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176147                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           57                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         9687                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        83499                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           81                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        11110                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        71712                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176147                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14759                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16370                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31797                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15231                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12357                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        29990                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        28727                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59385                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7702000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     10209000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     18033500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     95767000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     89981000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    185748000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       411000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       683500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1094500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9298219000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8003338001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  17301557001                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1194237004                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1366258502                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2560495506                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1029470503                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    899320001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1928790504                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      7702000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1194237004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  10327689503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     10209000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1366258502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   8902658002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21808876511                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      7702000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1194237004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  10327689503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     10209000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1366258502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   8902658002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21808876511                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2779455000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3132448000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5987910997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2416256500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2348489000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4764745500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5195711500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5480937000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10752656497                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001661                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000133                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002201                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001601                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.969697                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.968521                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.969127                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.176471                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.312500                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.242424                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.502234                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.440308                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.471584                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010372                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011091                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010744                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028506                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025802                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027192                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001661                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000133                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010372                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.190919                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002201                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011091                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.171299                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061195                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001661                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000133                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010372                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.190919                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002201                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011091                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.171299                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061195                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 129737.410072                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68016.335227                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68012.849584                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68014.646650                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        68500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        68350                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68406.250000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123472.485592                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123695.372647                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123575.488551                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123282.440797                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122975.562736                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123118.502957                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125652.447577                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128291.012981                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126869.072157                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123282.440797                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123686.385502                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122975.562736                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124144.606230                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123810.661044                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123282.440797                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123686.385502                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122975.562736                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124144.606230                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123810.661044                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188322.718341                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191352.962737                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188316.853697                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158640.699888                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190053.330096                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.798173                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173248.132711                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190793.922094                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.877107                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
system.membus.trans_dist::ReadResp              68158                       # Transaction distribution
system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131684                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8987                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4621                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             16                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138118                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138118                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36362                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468311                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       575893                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 648768                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17307612                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17471605                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19788725                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              495                       # Total snoops (count)
system.membus.snoop_fanout::samples            415409                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  415409    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              415409                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95443000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1716000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           922132455                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1008187748                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5622550                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2830625                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        48155                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            418                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          418                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             147977                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2643178                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       836971                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1935383                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          159154                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2818                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            66                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2884                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296889                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296889                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1935963                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       559323                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5808360                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2690765                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        40688                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162297                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8702110                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247790656                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100113141                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62776                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284444                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              348251017                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          206924                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3147531                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027177                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.162600                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                3061989     97.28%     97.28% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  85542      2.72%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3147531                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5535076493                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           269377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2906930517                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1330817051                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          25031921                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          91623614                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------