path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.542409                       # Number of seconds simulated
sim_ticks                                2542409356000                       # Number of ticks simulated
final_tick                               2542409356000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  77322                       # Simulator instruction rate (inst/s)
host_op_rate                                    99492                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3259551931                       # Simulator tick rate (ticks/s)
host_mem_usage                                 413868                       # Number of bytes of host memory used
host_seconds                                   779.99                       # Real time elapsed on the host
sim_insts                                    60310148                       # Number of instructions simulated
sim_ops                                      77602492                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         1600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           506624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4283408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           292928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4810268                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131006892                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       506624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       292928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          799552                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3787072                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1340604                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1675508                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6803184                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           25                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7916                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             66962                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           21                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4577                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             75167                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293487                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59173                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           335151                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           418877                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813201                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47636124                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           629                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              199269                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1684783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              115217                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1892012                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51528638                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         199269                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         115217                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314486                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1489560                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             527297                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             659024                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2675881                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1489560                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47636124                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          629                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             199269                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2212080                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          529                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             115217                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2551035                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54204519                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293487                       # Total number of read requests seen
system.physmem.writeReqs                       813201                       # Total number of write requests seen
system.physmem.cpureqs                         218488                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    978783168                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52044864                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              131006892                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6803184                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       10                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4687                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                956241                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                955734                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                955678                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                956495                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                956264                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                955436                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                955557                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                956169                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                956091                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                955615                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               955522                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               955928                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               956030                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               955423                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               955313                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               955981                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50841                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50416                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50438                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50906                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50184                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50278                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50865                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51363                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 50911                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50805                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51195                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51248                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50723                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                50636                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51230                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     1790732                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2542408198000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      43                       # Categorize read packet sizes
system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154628                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                2544760                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  59173                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 4687                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                   1054866                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    991514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    961470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3604976                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2718322                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2722144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2700252                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     60049                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59439                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    110004                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   160498                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   109966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    10070                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     9996                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    10911                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     8954                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32404                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    31921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    31858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    31803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    31723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    31647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    31605                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                   346733530557                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              439908911807                       # Sum of mem lat for all requests
system.physmem.totBusLat                  76467385000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16707996250                       # Total cycles spent in bank access
system.physmem.avgQLat                       22671.99                       # Average queueing delay per request
system.physmem.avgBankLat                     1092.49                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  28764.48                       # Average memory access latency
system.physmem.avgRdBW                         384.98                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.47                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.53                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                         1.11                       # Average write queue length over time
system.physmem.readRowHits                   15218342                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    794645                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.72                       # Row buffer hit rate for writes
system.physmem.avgGap                       157847.98                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         64396                       # number of replacements
system.l2c.tagsinuse                     51411.059605                       # Cycle average of tags in use
system.l2c.total_refs                         1936288                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        129787                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         14.918967                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2506346605000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        36969.089517                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker      15.370678                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000349                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5186.086135                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          3274.725116                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      19.219664                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.104011                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3007.163435                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2939.300701                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.564104                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000235                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.079133                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.049968                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000293                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000002                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.045886                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.044850                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.784471                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        48837                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7271                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             488824                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             211032                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        48027                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7206                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             482673                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             176185                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1470055                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          607854                       # number of Writeback hits
system.l2c.Writeback_hits::total               607854                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              17                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              16                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  33                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56342                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            56524                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112866                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         48837                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7271                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              488824                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              267374                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         48027                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7206                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              482673                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              232709                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1582921                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        48837                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7271                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             488824                       # number of overall hits
system.l2c.overall_hits::cpu0.data             267374                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        48027                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7206                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             482673                       # number of overall hits
system.l2c.overall_hits::cpu1.data             232709                       # number of overall hits
system.l2c.overall_hits::total                1582921                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           25                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7806                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6093                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           21                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4582                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4589                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23119                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1580                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1330                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2910                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          61797                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          71443                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133240                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           25                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7806                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             67890                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           21                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4582                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76032                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156359                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           25                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7806                       # number of overall misses
system.l2c.overall_misses::cpu0.data            67890                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           21                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4582                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76032                       # number of overall misses
system.l2c.overall_misses::total               156359                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1700500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    431133000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    345731497                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1924500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    269379000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    269289000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1319343997                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       205000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       274000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       479000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3242523998                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3517580500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6760104498                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1700500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    431133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3588255495                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1924500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        68500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    269379000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3786869500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8079448495                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1700500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    431133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3588255495                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1924500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        68500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    269379000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3786869500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8079448495                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        48862                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7273                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         496630                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         217125                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        48048                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7207                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         487255                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         180774                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1493174                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       607854                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           607854                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1597                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1346                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2943                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             8                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       118139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       127967                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246106                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        48862                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7273                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          496630                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          335264                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        48048                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7207                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          487255                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          308741                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1739280                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        48862                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7273                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         496630                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         335264                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        48048                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7207                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         487255                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         308741                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1739280                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000512                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000275                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015718                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.028062                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000437                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000139                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009404                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.025385                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015483                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989355                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988113                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.988787                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.523087                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.558292                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541393                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000512                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000275                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015718                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.202497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000437                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000139                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009404                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.246265                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.089899                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000512                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000275                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015718                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.202497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000437                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000139                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009404                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.246265                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.089899                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        68020                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55230.976172                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56742.408830                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 91642.857143                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58790.702750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58681.412072                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 57067.520092                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   129.746835                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   206.015038                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   164.604811                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52470.572973                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49236.181291                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50736.299144                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        68020                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 55230.976172                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52853.962218                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91642.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        68500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 58790.702750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 49806.259207                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51672.423685                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        68020                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 55230.976172                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52853.962218                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91642.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        68500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 58790.702750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 49806.259207                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51672.423685                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59173                       # number of writebacks
system.l2c.writebacks::total                    59173                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            20                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                73                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             20                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 73                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            20                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                73                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           25                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7797                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6054                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           21                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4577                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4569                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23046                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1580                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1330                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2910                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        61797                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        71443                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133240                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           25                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7797                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        67851                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           21                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4577                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76012                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156286                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           25                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7797                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        67851                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           21                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4577                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76012                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156286                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1388048                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    333715736                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    268789023                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1661538                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        56252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    212136240                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    211485699                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1029325788                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15908517                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13301330                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29209847                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2471692908                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2627616827                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5099309735                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1388048                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93252                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    333715736                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2740481931                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1661538                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        56252                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    212136240                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2839102526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6128635523                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1388048                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93252                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    333715736                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2740481931                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1661538                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        56252                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    212136240                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2839102526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6128635523                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5050907                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  84092703276                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82869988008                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166967742191                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  10187478145                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  12920441542                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  23107919687                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76254                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76254                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5050907                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  94280181421                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  95790429550                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190075661878                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000512                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000275                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015700                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027883                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000437                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000139                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009393                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025275                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015434                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989355                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.988113                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.988787                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.523087                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.558292                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541393                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000512                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000275                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015700                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.202381                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000437                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000139                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009393                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.246200                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.089857                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000512                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000275                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015700                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.202381                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000437                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000139                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009393                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.246200                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.089857                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        56252                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        56252                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39214.232388                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46626                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        56252                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39214.232388                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups                7548901                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          6013590                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           377467                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4898170                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4008296                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            81.832521                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 726547                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             38944                       # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25977003                       # DTB read hits
system.cpu0.dtb.read_misses                     44168                       # DTB read misses
system.cpu0.dtb.write_hits                    5905544                       # DTB write hits
system.cpu0.dtb.write_misses                    10435                       # DTB write misses
system.cpu0.dtb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                753                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    8487                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1476                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   307                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      629                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                26021171                       # DTB read accesses
system.cpu0.dtb.write_accesses                5915979                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31882547                       # DTB hits
system.cpu0.dtb.misses                          54603                       # DTB misses
system.cpu0.dtb.accesses                     31937150                       # DTB accesses
system.cpu0.itb.inst_hits                     6053570                       # ITB inst hits
system.cpu0.itb.inst_misses                      7437                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         257                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                753                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2703                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1556                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6061007                       # ITB inst accesses
system.cpu0.itb.hits                          6053570                       # DTB hits
system.cpu0.itb.misses                           7437                       # DTB misses
system.cpu0.itb.accesses                      6061007                       # DTB accesses
system.cpu0.numCycles                       238938486                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          15394391                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      47363199                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7548901                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4734843                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10514679                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2521350                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     88217                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              49746520                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1647                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             1973                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        54986                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       100350                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          256                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6051440                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               388609                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3416                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          77647495                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.755624                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.112120                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67140338     86.47%     86.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  685224      0.88%     87.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  881384      1.14%     88.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1215413      1.57%     90.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1119001      1.44%     91.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  577018      0.74%     92.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1310230      1.69%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  395483      0.51%     94.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4323404      5.57%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            77647495                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031593                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.198223                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16447301                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             49466389                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9519649                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               555058                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1656976                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1018880                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                89951                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              55851060                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               301878                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1656976                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17376198                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               19158247                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27017971                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9071618                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3364444                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              53098048                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                14247                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                629745                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2187800                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents           13035                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           55196889                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            241870306                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       241822297                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            48009                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             40273759                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14923130                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            426834                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        378971                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6800028                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10269000                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6780798                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1063277                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1318043                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  49318736                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1023913                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 62924434                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            96522                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10293246                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     26052938                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        249929                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     77647495                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.810386                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.515841                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           54849449     70.64%     70.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7244024      9.33%     79.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3688560      4.75%     84.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3114192      4.01%     88.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6252852      8.05%     96.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1400137      1.80%     98.59% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             804405      1.04%     99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             228817      0.29%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              65059      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       77647495                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  28907      0.65%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     5      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.65% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4221672     94.79%     95.44% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               203228      4.56%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass           196078      0.31%      0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29762339     47.30%     47.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               47254      0.08%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  9      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1214      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26685508     42.41%     90.10% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6232016      9.90%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              62924434                       # Type of FU issued
system.cpu0.iq.rate                          0.263350                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4453812                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.070780                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         208088796                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         60644934                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     43952872                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12311                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6553                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5522                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              67175656                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6512                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          321336                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2241404                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3447                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        16174                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       877395                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17145295                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       358927                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1656976                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               14313344                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               236698                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           50458165                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           105115                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10269000                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6780798                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            724480                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 58024                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3552                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         16174                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        184745                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       145643                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              330388                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             61778089                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26333265                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1146345                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       115516                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32508411                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 5980040                       # Number of branches executed
system.cpu0.iew.exec_stores                   6175146                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.258552                       # Inst execution rate
system.cpu0.iew.wb_sent                      61260719                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     43958394                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24186405                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 44536826                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.183974                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.543065                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       10181243                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         773984                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           288739                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     75990519                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.523900                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.505441                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     61812445     81.34%     81.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6884323      9.06%     90.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2031918      2.67%     93.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1127942      1.48%     94.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1041381      1.37%     95.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       554423      0.73%     96.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       699295      0.92%     97.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       364332      0.48%     98.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1474460      1.94%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     75990519                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            31157319                       # Number of instructions committed
system.cpu0.commit.committedOps              39811398                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13930999                       # Number of memory references committed
system.cpu0.commit.loads                      8027596                       # Number of loads committed
system.cpu0.commit.membars                     211461                       # Number of memory barriers committed
system.cpu0.commit.branches                   5178005                       # Number of branches committed
system.cpu0.commit.fp_insts                      5497                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 35182368                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              511213                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1474460                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   123547695                       # The number of ROB reads
system.cpu0.rob.rob_writes                  101683929                       # The number of ROB writes
system.cpu0.timesIdled                         881879                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      161290991                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2289851507                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   31079277                       # Number of Instructions Simulated
system.cpu0.committedOps                     39733356                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             31079277                       # Number of Instructions Simulated
system.cpu0.cpi                              7.688032                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        7.688032                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.130072                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.130072                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               279629599                       # number of integer regfile reads
system.cpu0.int_regfile_writes               45168223                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    22746                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   19898                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               15538839                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                427973                       # number of misc regfile writes
system.cpu0.icache.replacements                984670                       # number of replacements
system.cpu0.icache.tagsinuse               511.607871                       # Cycle average of tags in use
system.cpu0.icache.total_refs                10994375                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                985182                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 11.159740                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6536916000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   357.062519                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst   154.545352                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.697388                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.301846                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999234                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      5513374                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5481001                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       10994375                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5513374                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5481001                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        10994375                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5513374                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5481001                       # number of overall hits
system.cpu0.icache.overall_hits::total       10994375                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       537943                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       527405                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1065348                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       537943                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       527405                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1065348                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       537943                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       527405                       # number of overall misses
system.cpu0.icache.overall_misses::total      1065348                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7287778496                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   7022356993                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14310135489                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7287778496                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   7022356993                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14310135489                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7287778496                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   7022356993                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14310135489                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6051317                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      6008406                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     12059723                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6051317                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      6008406                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     12059723                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6051317                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      6008406                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     12059723                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.088897                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.087778                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.088339                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.088897                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.087778                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.088339                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.088897                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.087778                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.088339                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.492013                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13314.923053                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.357773                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.492013                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13314.923053                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13432.357773                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.492013                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13314.923053                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13432.357773                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4400                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1635                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              334                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.173653                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets         1635                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        40608                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39535                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        80143                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        40608                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        39535                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        80143                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        40608                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        39535                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        80143                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       497335                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       487870                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       985205                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       497335                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       487870                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       985205                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       497335                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       487870                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       985205                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5948053496                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5711985994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11660039490                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5948053496                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5711985994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11660039490                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5948053496                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5711985994                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11660039490                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7526000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7526000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7526000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7526000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.082186                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.081198                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.081694                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.082186                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.081198                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.081694                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.082186                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.081198                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.081694                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11959.853009                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.008269                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.140392                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11959.853009                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.008269                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.140392                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11959.853009                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.008269                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.140392                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                643493                       # number of replacements
system.cpu0.dcache.tagsinuse               511.992715                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                21548288                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                644005                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.459815                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              43208000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   318.069743                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data   193.922971                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.621230                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.378756                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999986                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7070467                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6719560                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13790027                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3778333                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3485501                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7263834                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       125105                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       118624                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       243729                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       127190                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       120429                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247619                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10848800                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10205061                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21053861                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10848800                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10205061                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21053861                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       426518                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       319237                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       745755                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1396624                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1562374                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2958998                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6770                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6794                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13564                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            3                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1823142                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1881611                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3704753                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1823142                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1881611                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3704753                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6341434500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   4955315500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11296750000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  54124528351                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  59881914802                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114006443153                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91205000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     94667500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    185872500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        39000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        65000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       104000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  60465962851                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  64837230302                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125303193153                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  60465962851                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  64837230302                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125303193153                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7496985                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      7038797                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14535782                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5174957                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5047875                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10222832                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       131875                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       125418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       257293                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       127193                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       120434                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247627                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12671942                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     12086672                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24758614                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12671942                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     12086672                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24758614                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.056892                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.045354                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051305                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.269881                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.309511                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.289450                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.051336                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054171                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052718                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000024                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000042                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000032                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.143872                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.155677                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149635                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.143872                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.155677                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149635                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14867.917649                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15522.372093                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15148.071418                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38753.829485                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.516204                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38528.732751                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13471.935007                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13933.985870                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13703.369213                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33165.799949                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 34458.360576                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33822.279961                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33165.799949                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 34458.360576                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33822.279961                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        35965                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        14941                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3389                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            263                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.612275                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    56.809886                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       607854                       # number of writebacks
system.cpu0.dcache.writebacks::total           607854                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215439                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       144497                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       359936                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1276945                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1433111                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2710056                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          667                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          710                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1377                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1492384                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1577608                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3069992                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1492384                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1577608                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3069992                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       211079                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       174740                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       385819                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       119679                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       129263                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       248942                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6103                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         6084                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12187                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       330758                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       304003                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       634761                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       330758                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       304003                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       634761                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2867323500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2359031500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5226355000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4068255992                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   4371447438                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8439703430                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     71165500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73921500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    145087000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        33000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        55000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        88000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6935579492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6730478938                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13666058430                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6935579492                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6730478938                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13666058430                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91842786000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90513364000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356150000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  14606778738                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  18392840622                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  32999619360                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       118000                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106449564738                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 108906204622                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215355769360                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028155                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024825                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026543                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023127                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025607                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024352                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046279                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.048510                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047366                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000024                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000042                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026102                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025152                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025638                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026102                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025152                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025638                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13584.124901                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.237496                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13546.131735                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33993.064715                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33818.242173                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                7102253                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5695769                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           349355                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4570648                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3841672                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            84.050927                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 676938                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             35276                       # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25380131                       # DTB read hits
system.cpu1.dtb.read_misses                     40834                       # DTB read misses
system.cpu1.dtb.write_hits                    5811015                       # DTB write hits
system.cpu1.dtb.write_misses                     9771                       # DTB write misses
system.cpu1.dtb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                686                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    8065                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1494                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   315                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      637                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25420965                       # DTB read accesses
system.cpu1.dtb.write_accesses                5820786                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         31191146                       # DTB hits
system.cpu1.dtb.misses                          50605                       # DTB misses
system.cpu1.dtb.accesses                     31241751                       # DTB accesses
system.cpu1.itb.inst_hits                     6010554                       # ITB inst hits
system.cpu1.itb.inst_misses                      6924                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         254                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                686                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2690                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1453                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 6017478                       # ITB inst accesses
system.cpu1.itb.hits                          6010554                       # DTB hits
system.cpu1.itb.misses                           6924                       # DTB misses
system.cpu1.itb.accesses                      6017478                       # DTB accesses
system.cpu1.numCycles                       234669310                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          15209580                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      46712783                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    7102253                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4518610                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     10317375                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2619576                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     83943                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              47843149                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                1067                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             2062                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        49108                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        95676                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  6008408                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               439180                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3193                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          75397416                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.769986                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.133362                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                65087895     86.33%     86.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  627947      0.83%     87.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  837408      1.11%     88.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1205044      1.60%     89.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1066340      1.41%     91.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  537838      0.71%     92.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1370888      1.82%     93.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  355288      0.47%     94.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4308768      5.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            75397416                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.030265                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.199058                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                16234163                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             47629419                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  9365333                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               455355                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1710994                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              954633                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                86850                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              54991941                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               289065                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1710994                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17174187                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               18737860                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      25818505                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8802452                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3151356                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              51852963                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 7784                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                495819                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2156102                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           16790                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           53921236                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            237794819                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       237752758                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            42061                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             38119457                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                15801778                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            406275                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        360043                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6312412                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9898501                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6682455                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           887681                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1092966                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  47793867                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             962748                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 60992947                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            83561                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10588710                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     27790687                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        254225                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     75397416                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.808953                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.518534                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           53544512     71.02%     71.02% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6720979      8.91%     79.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3575565      4.74%     84.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2884458      3.83%     88.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6227948      8.26%     96.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1437657      1.91%     98.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             736271      0.98%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             210447      0.28%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              59579      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       75397416                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  24253      0.55%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     3      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4149284     94.86%     95.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               200652      4.59%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           167588      0.27%      0.27% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             28559163     46.82%     47.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46488      0.08%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  8      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              5      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           897      0.00%     47.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     47.18% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.18% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            26112884     42.81%     89.99% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6105909     10.01%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              60992947                       # Type of FU issued
system.cpu1.iq.rate                          0.259910                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4374192                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.071716                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         201880877                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         59353845                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     41952881                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              10603                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              5821                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         4743                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              65193949                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   5602                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          306044                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2270775                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3168                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        14837                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       853246                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     16957357                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       451019                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1710994                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               14077639                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               237686                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           48863462                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            99358                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9898501                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6682455                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            687943                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 54116                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 4064                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         14837                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        169399                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       135230                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              304629                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             59633634                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25710347                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1359313                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       106847                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31763994                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5570991                       # Number of branches executed
system.cpu1.iew.exec_stores                   6053647                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.254118                       # Inst execution rate
system.cpu1.iew.wb_sent                      59059835                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     41957624                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 22877560                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 41856848                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.178795                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.546567                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       10488461                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         708523                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           263786                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     73686422                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.514905                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.496046                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     60141742     81.62%     81.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6665026      9.05%     90.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1916982      2.60%     93.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1022287      1.39%     94.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       952512      1.29%     95.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       518669      0.70%     96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       704589      0.96%     97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       372223      0.51%     98.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1392392      1.89%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     73686422                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            29303210                       # Number of instructions committed
system.cpu1.commit.committedOps              37941475                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13456935                       # Number of memory references committed
system.cpu1.commit.loads                      7627726                       # Number of loads committed
system.cpu1.commit.membars                     192181                       # Number of memory barriers committed
system.cpu1.commit.branches                   4783662                       # Number of branches committed
system.cpu1.commit.fp_insts                      4715                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 33675461                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              480108                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1392392                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   119835622                       # The number of ROB reads
system.cpu1.rob.rob_writes                   98622587                       # The number of ROB writes
system.cpu1.timesIdled                         873829                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      159271894                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2285541005                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   29230871                       # Number of Instructions Simulated
system.cpu1.committedOps                     37869136                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             29230871                       # Number of Instructions Simulated
system.cpu1.cpi                              8.028133                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.028133                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.124562                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.124562                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               270257014                       # number of integer regfile reads
system.cpu1.int_regfile_writes               43086162                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    22099                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   19636                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               14849439                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                404495                       # number of misc regfile writes
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192737213912                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83053                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------