path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.814515                       # Number of seconds simulated
sim_ticks                                2814515403000                       # Number of ticks simulated
final_tick                               2814515403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 109456                       # Simulator instruction rate (inst/s)
host_op_rate                                   132849                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2632808896                       # Simulator tick rate (ticks/s)
host_mem_usage                                 624704                       # Number of bytes of host memory used
host_seconds                                  1069.02                       # Real time elapsed on the host
sim_insts                                   117010217                       # Number of instructions simulated
sim_ops                                     142017883                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         4416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           748224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5094496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           629568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4721220                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11203044                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       748224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       629568                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1377792                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8429952                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8447476                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           69                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             11691                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             80120                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           64                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9837                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             73770                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175567                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131718                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136099                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              265845                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1810079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1455                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              223686                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1677454                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3980452                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         265845                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         223686                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             489531                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2995170                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6223                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3001396                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2995170                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1569                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             265845                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1816303                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1455                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             223686                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1677457                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6981848                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175568                       # Number of read requests accepted
system.physmem.writeReqs                       172295                       # Number of write requests accepted
system.physmem.readBursts                      175568                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     172295                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11229120                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7232                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10657088                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11203108                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10764020                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      113                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5755                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4657                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11278                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11187                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11389                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10916                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11527                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11542                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11806                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11898                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10235                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10554                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10596                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9816                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10461                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11360                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10541                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10349                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10520                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10540                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10805                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10377                       # Per bank write bursts
system.physmem.perBankWrBursts::4               10808                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10825                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10943                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10998                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9971                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10108                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9937                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9693                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10233                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10896                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10053                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9810                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2814515217000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  175013                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 167914                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    104295                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61178                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1516                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    12006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    11257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        66987                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      326.722260                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     189.177109                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     345.277059                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24335     36.33%     36.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15823     23.62%     59.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6599      9.85%     69.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3701      5.52%     75.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2840      4.24%     79.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1617      2.41%     81.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1134      1.69%     83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1090      1.63%     85.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9848     14.70%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          66987                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7135                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.589488                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      462.801411                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7132     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7135                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7135                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.338052                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.587494                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.995044                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                12      0.17%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 6      0.08%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                5      0.07%      0.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               6      0.08%      0.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5911     82.85%     83.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             110      1.54%     84.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              53      0.74%     85.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             225      3.15%     88.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             144      2.02%     90.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              50      0.70%     91.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              36      0.50%     91.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              29      0.41%     92.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             105      1.47%     93.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.24%     94.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              10      0.14%     94.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.20%     94.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              31      0.43%     94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              18      0.25%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.13%     95.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              33      0.46%     95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              56      0.78%     96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              14      0.20%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               6      0.08%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              11      0.15%     96.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              75      1.05%     97.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             8      0.11%     98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            14      0.20%     98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            17      0.24%     98.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             5      0.07%     98.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             6      0.08%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             5      0.07%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            32      0.45%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             7      0.10%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.03%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             6      0.08%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             5      0.07%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             7      0.10%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             9      0.13%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.04%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.07%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.04%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7135                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2670855500                       # Total ticks spent queuing
system.physmem.totMemAccLat                5960636750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    877275000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15222.45                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33972.45                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.79                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.20                       # Average write queue length when enqueuing
system.physmem.readRowHits                     145151                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    129833                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.73                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.96                       # Row buffer hit rate for writes
system.physmem.avgGap                      8090872.61                       # Average gap between requests
system.physmem.pageHitRate                      80.41                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  265386240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  144804000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 714027600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                556087680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           183830200320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            77881590900                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1620389778750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1883781875490                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.310395                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2695567326750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     93982720000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     24965345250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  241035480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  131517375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 654513600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                522942480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           183830200320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            77208822180                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1620979926750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1883568958185                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.234745                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2696551299250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     93982720000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     23977600750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           10                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             10                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          227                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              227                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          227                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          227                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          227                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             227                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               27466718                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         14314218                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           559197                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            17107445                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12928393                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            75.571735                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6777363                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             30194                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    58720                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               58720                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19962                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14154                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        24604                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        34116                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   475.187595                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3075.067201                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        33369     97.81%     97.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          426      1.25%     99.06% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          228      0.67%     99.73% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767           49      0.14%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           15      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343            6      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::122880-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        34116                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12972                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12168.830173                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9642.893366                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7992.253434                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-8191         3564     27.47%     27.47% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::8192-16383         6077     46.85%     74.32% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2864     22.08%     96.40% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::24576-32767          230      1.77%     98.17% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-40959           90      0.69%     98.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::40960-49151          115      0.89%     99.75% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-57343           10      0.08%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::57344-65535            3      0.02%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::73728-81919           10      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-90111            4      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::90112-98303            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-106495            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12972                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  78620736948                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.741175                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.458010                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  78549397948     99.91%     99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     52259000      0.07%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5      9664500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      3325500      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2093000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1088000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13       676500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1423500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       291000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       117500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21        73500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        71500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       138500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        55500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29         6000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31        55500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  78620736948                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3790     68.96%     68.96% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1706     31.04%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5496                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58720                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58720                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5496                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5496                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        64216                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    14377700                       # DTB read hits
system.cpu0.dtb.read_misses                     50689                       # DTB read misses
system.cpu0.dtb.write_hits                   10391095                       # DTB write hits
system.cpu0.dtb.write_misses                     8031                       # DTB write misses
system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3541                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1016                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1359                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      592                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14428389                       # DTB read accesses
system.cpu0.dtb.write_accesses               10399126                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24768795                       # DTB hits
system.cpu0.dtb.misses                          58720                       # DTB misses
system.cpu0.dtb.accesses                     24827515                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     8876                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                8876                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3394                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5333                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          149                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         8727                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1034.949009                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  4440.773831                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         8334     95.50%     95.50% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          202      2.31%     97.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          114      1.31%     99.12% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           44      0.50%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           18      0.21%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151            9      0.10%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            3      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         8727                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2584                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12070.828560                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9384.773588                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7691.454372                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          754     29.18%     29.18% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1107     42.84%     72.02% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          648     25.08%     97.10% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           49      1.90%     98.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           17      0.66%     99.65% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            4      0.15%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.12%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2584                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  31375770192                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.875900                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.330034                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     3896845928     12.42%     12.42% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    27476174764     87.57%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2435000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         275000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4          39500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  31375770192                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1855     76.18%     76.18% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          580     23.82%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2435                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8876                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8876                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2435                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2435                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        11311                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20634228                       # ITB inst hits
system.cpu0.itb.inst_misses                      8876                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2373                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1477                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20643104                       # ITB inst accesses
system.cpu0.itb.hits                         20634228                       # DTB hits
system.cpu0.itb.misses                           8876                       # DTB misses
system.cpu0.itb.accesses                     20643104                       # DTB accesses
system.cpu0.numCycles                       108167671                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          40851007                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     106236775                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   27466718                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19705756                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     62062972                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3267693                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    153669                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                7048                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              432                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       489783                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       144519                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          202                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20632894                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               382391                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3679                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         105343442                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.211364                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.309053                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                76103279     72.24%     72.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3910098      3.71%     75.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2412212      2.29%     78.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8199484      7.78%     86.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1671331      1.59%     87.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1069053      1.01%     88.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6251821      5.93%     94.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1074556      1.02%     95.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4651608      4.42%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           105343442                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.253927                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.982149                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                28225112                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58231710                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15904811                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1498973                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1482577                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1930879                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               153387                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              88028064                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               497001                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1482577                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                29091969                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                7814173                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      44573853                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16523893                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              5856699                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              84168015                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 2790                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1211369                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                234681                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               3674238                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           86834114                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            387462225                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        93765985                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6215                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72808994                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14025104                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1551576                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1456348                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8924255                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            15135142                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11528605                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1955130                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2746979                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  80972727                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1061733                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 77600115                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            93477                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10225467                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     25113988                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        116264                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    105343442                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.736639                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.430545                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           74430085     70.65%     70.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10248464      9.73%     80.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7900647      7.50%     87.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6607763      6.27%     94.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2341378      2.22%     96.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1506364      1.43%     97.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1572871      1.49%     99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             494450      0.47%     99.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             241420      0.23%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      105343442                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 114775     10.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     3      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                538516     46.90%     56.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               494955     43.11%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2213      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             51768146     66.71%     66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57542      0.07%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   2      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  1      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4481      0.01%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14787493     19.06%     85.85% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10980227     14.15%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              77600115                       # Type of FU issued
system.cpu0.iq.rate                          0.717406                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1148249                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014797                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         261771758                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         92305365                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     75123288                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              13640                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              7254                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5910                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              78738792                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7359                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          349889                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2246274                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2500                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        53675                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1142950                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       210780                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       206750                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1482577                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5380945                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              2158862                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           82157406                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           132522                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             15135142                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11528605                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            554173                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44324                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              2102450                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         53675                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        259338                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       224546                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              483884                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             76981591                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14546003                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           559940                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       122946                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25419191                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14512373                       # Number of branches executed
system.cpu0.iew.exec_stores                  10873188                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.711688                       # Inst execution rate
system.cpu0.iew.wb_sent                      76311316                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     75129198                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 39246313                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 68010606                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.694562                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.577062                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       11503261                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         945469                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           407891                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    102758261                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.686747                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.577053                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     75291319     73.27%     73.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12321005     11.99%     85.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6288153      6.12%     91.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2655881      2.58%     93.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1298740      1.26%     95.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       839233      0.82%     96.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1891164      1.84%     97.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       416236      0.41%     98.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1756530      1.71%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    102758261                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            58183568                       # Number of instructions committed
system.cpu0.commit.committedOps              70568955                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23274523                       # Number of memory references committed
system.cpu0.commit.loads                     12888868                       # Number of loads committed
system.cpu0.commit.membars                     375842                       # Number of memory barriers committed
system.cpu0.commit.branches                  13706650                       # Number of branches committed
system.cpu0.commit.fp_insts                      5838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61788721                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2663542                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        47234123     66.93%     66.93% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55828      0.08%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4481      0.01%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12888868     18.26%     85.28% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10385655     14.72%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70568955                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1756530                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   170410924                       # The number of ROB reads
system.cpu0.rob.rob_writes                  166734025                       # The number of ROB writes
system.cpu0.timesIdled                         403289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2824229                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2462180705                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   58113002                       # Number of Instructions Simulated
system.cpu0.committedOps                     70498389                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.861333                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.861333                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.537249                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.537249                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                83710036                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47877732                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16593                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13071                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                272135235                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                28380305                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              192072102                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                725098                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           853107                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.984634                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42535549                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           853619                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.829665                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         91705250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   327.353563                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   184.631071                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.639362                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.360608                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189955198                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189955198                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12681674                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12667533                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25349207                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7766233                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8148068                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15914301                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181732                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180331                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       362063                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209455                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237675                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       447130                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       215313                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       244405                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459718                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20447907                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20815601                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41263508                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20629639                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     20995932                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41625571                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       429725                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       402525                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       832250                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1921923                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1778424                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3700347                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        98138                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        84449                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       182587                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13508                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14201                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27709                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           30                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           48                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           78                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2351648                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2180949                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4532597                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2449786                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2265398                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4715184                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7060794359                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6694788448                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  13755582807                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83430874942                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  75332466558                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 158763341500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183117244                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    210458494                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    393575738                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       643510                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       802514                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1446024                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  90491669301                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  82027255006                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 172518924307                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  90491669301                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  82027255006                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 172518924307                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     13111399                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13070058                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26181457                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9688156                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9926492                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19614648                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       279870                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       264780                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       544650                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222963                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251876                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474839                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       215343                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       244453                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459796                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22799555                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     22996550                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45796105                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     23079425                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23261330                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46340755                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032775                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030797                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031788                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198379                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179159                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188652                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.350656                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.318940                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335237                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060584                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056381                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058355                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000139                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000196                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000170                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103144                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094838                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.098973                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106146                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097389                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.101750                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16430.960170                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16631.981735                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16528.186010                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43410.102768                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42359.114901                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42904.987424                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13556.206988                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14819.977044                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14203.895413                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21450.333333                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16719.041667                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38480.108120                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37610.808417                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 38061.827316                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36938.601699                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36208.761112                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36587.951670                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1102752                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       157342                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            69674                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2409                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.827310                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    65.314238                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       703765                       # number of writebacks
system.cpu0.dcache.writebacks::total           703765                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215820                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       190387                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       406207                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1767730                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1633312                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3401042                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9415                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8962                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18377                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1983550                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1823699                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3807249                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1983550                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1823699                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3807249                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       213905                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212138                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426043                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       154193                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       145112                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299305                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        64082                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57716                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       121798                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4093                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5239                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9332                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           30                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           48                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           78                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       368098                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       357250                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       725348                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       432180                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       414966                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       847146                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2879120711                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2930558911                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5809679622                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6700541283                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6184063438                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12884604721                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    975154510                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    900261506                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1875416016                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     47931501                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     80133502                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    128065003                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       583490                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       706486                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1289976                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9579661994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9114622349                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  18694284343                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10554816504                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10014883855                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  20569700359                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3162299001                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2622267000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784566001                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2409236377                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2026898500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436134877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5571535378                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4649165500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220700878                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016314                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016231                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016273                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015916                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014619                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015259                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228971                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.217977                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223626                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018357                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020800                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019653                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000139                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000196                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000170                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016145                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015535                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015839                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018726                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017839                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018281                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13459.810248                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13814.398698                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13636.369151                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43455.547807                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42615.796337                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43048.411223                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15217.292063                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15598.127140                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15397.757073                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11710.603714                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15295.572056                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13723.210780                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19449.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14718.458333                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26024.759694                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25513.288591                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25772.848816                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24422.269665                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24134.227515                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24281.175097                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1946899                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.580862                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           39112552                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1947411                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.084385                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9482142250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   275.928996                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   235.651865                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.538924                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.460258                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999181                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         43147534                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        43147534                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19581661                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19530891                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       39112552                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19581661                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19530891                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        39112552                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19581661                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19530891                       # number of overall hits
system.cpu0.icache.overall_hits::total       39112552                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1050570                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1036904                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2087474                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1050570                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1036904                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2087474                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1050570                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1036904                       # number of overall misses
system.cpu0.icache.overall_misses::total      2087474                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14373129884                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14097990125                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28471120009                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14373129884                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14097990125                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28471120009                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14373129884                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14097990125                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28471120009                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20632231                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20567795                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     41200026                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20632231                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20567795                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     41200026                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20632231                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20567795                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     41200026                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050919                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050414                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050667                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050919                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050414                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050667                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050919                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050414                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050667                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13681.268153                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.234680                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13639.029760                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13681.268153                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13596.234680                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13639.029760                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13681.268153                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13596.234680                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13639.029760                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         8502                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              563                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.101243                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70345                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        69620                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       139965                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        70345                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        69620                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       139965                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        70345                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        69620                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       139965                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       980225                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       967284                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1947509                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       980225                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       967284                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1947509                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       980225                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       967284                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1947509                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11736390069                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11515392307                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  23251782376                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11736390069                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11515392307                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  23251782376                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11736390069                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11515392307                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  23251782376                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     49454750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     49454750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     49454750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     49454750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047270                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047270                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047270                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11939.242579                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11939.242579                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11939.242579                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27252662                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14161158                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           545075                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17238794                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               12795126                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            74.222860                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6755804                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29339                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    58706                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58706                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19477                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14176                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25053                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33653                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   557.840311                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3475.112155                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-8191        32827     97.55%     97.55% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-16383          501      1.49%     99.03% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-24575          206      0.61%     99.65% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-32767           52      0.15%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-40959           23      0.07%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-49151           18      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-57343           14      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-73727            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-90111            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::90112-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-106495            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::122880-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33653                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        11554                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10457.034101                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  8151.140813                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7042.402736                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         4078     35.30%     35.30% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5524     47.81%     83.11% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1648     14.26%     97.37% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          166      1.44%     98.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           76      0.66%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151           59      0.51%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::73728-81919            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        11554                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  82024244244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.681515                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.487291                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  81955384244     99.92%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     50513000      0.06%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5      9145000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      3183000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      1958500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1084000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       660000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15       995500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       376500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       124000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21        98500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        69500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25        91500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        76000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29       274000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31       211000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  82024244244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3372     68.52%     68.52% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1549     31.48%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         4921                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58706                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58706                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         4921                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         4921                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        63627                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14299827                       # DTB read hits
system.cpu1.dtb.read_misses                     48713                       # DTB read misses
system.cpu1.dtb.write_hits                   10649623                       # DTB write hits
system.cpu1.dtb.write_misses                     9993                       # DTB write misses
system.cpu1.dtb.flush_tlb                         175                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3345                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      749                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1307                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      516                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14348540                       # DTB read accesses
system.cpu1.dtb.write_accesses               10659616                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24949450                       # DTB hits
system.cpu1.dtb.misses                          58706                       # DTB misses
system.cpu1.dtb.accesses                     25008156                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     7607                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7607                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2551                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4918                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          138                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7469                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1253.983130                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  5505.331618                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         7086     94.87%     94.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          200      2.68%     97.55% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575          109      1.46%     99.01% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           32      0.43%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           14      0.19%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           11      0.15%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            6      0.08%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::106496-114687            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7469                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2377                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11683.850652                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  8982.900240                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7620.243918                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          698     29.36%     29.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191           50      2.10%     31.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          916     38.54%     70.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383           82      3.45%     73.45% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           34      1.43%     74.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575          536     22.55%     97.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           26      1.09%     98.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            4      0.17%     98.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            7      0.29%     98.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959           17      0.72%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            6      0.25%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2377                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  26182117896                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.680154                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.466824                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     8377919500     32.00%     32.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    17801455396     67.99%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2155000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         325500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         194500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          68000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  26182117896                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1688     75.39%     75.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          551     24.61%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2239                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7607                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7607                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2239                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2239                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         9846                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20569517                       # ITB inst hits
system.cpu1.itb.inst_misses                      7607                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         175                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2207                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1289                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20577124                       # ITB inst accesses
system.cpu1.itb.hits                         20569517                       # DTB hits
system.cpu1.itb.misses                           7607                       # DTB misses
system.cpu1.itb.accesses                     20577124                       # DTB accesses
system.cpu1.numCycles                       107002102                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40500350                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     106310459                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27252662                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19550930                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     61683449                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3213099                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    111780                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                3981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              436                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       347701                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       135656                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          234                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20567798                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               376508                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3292                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         104390100                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.225611                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.323253                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                75144035     71.98%     71.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3907124      3.74%     75.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2485008      2.38%     78.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8099840      7.76%     85.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1578542      1.51%     87.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1169165      1.12%     88.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6151960      5.89%     94.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1142182      1.09%     95.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4712244      4.51%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           104390100                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.254693                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.993536                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27682693                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             57882458                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15650277                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1716894                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1457466                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1955529                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               151159                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              88694873                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               489106                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1457466                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28625802                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                6604433                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      45361321                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16416425                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              5924344                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              84834346                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2307                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1574765                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                278233                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               3285499                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           87641847                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            391276070                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94803920                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5749                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             73988395                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13653452                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1589936                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1488982                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10049361                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15102779                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11808907                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2150791                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2768917                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  81595404                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1156818                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78284353                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93210                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        9952134                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     25073057                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        106330                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    104390100                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.749921                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.429238                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           72870740     69.81%     69.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10640655     10.19%     80.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8029126      7.69%     87.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6654786      6.37%     94.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2478739      2.37%     96.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1537519      1.47%     97.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1459463      1.40%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             490817      0.47%     99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             228255      0.22%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      104390100                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 100798      8.75%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                535574     46.51%     55.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               515204     44.74%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              124      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52262651     66.76%     66.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59116      0.08%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4115      0.01%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             1      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14698419     18.78%     85.62% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11259924     14.38%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78284353                       # Type of FU issued
system.cpu1.iq.rate                          0.731615                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1151580                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014710                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         262190696                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         92748647                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     75915598                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              12900                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6883                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5649                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79428849                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6960                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          366149                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2166601                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2614                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        52391                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1139774                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       191651                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       153600                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1457466                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4280991                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              2091777                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           82896193                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           132170                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15102779                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11808907                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            583505                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 47325                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2032029                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         52391                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        250395                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       218336                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              468731                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77684491                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14461832                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           541313                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       143971                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25613639                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14454387                       # Number of branches executed
system.cpu1.iew.exec_stores                  11151807                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.726009                       # Inst execution rate
system.cpu1.iew.wb_sent                      77065601                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     75921247                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39733715                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69689049                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.709530                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.570157                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       11280608                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1050488                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           395955                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    101852201                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.703017                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.586598                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     73888394     72.54%     72.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12531229     12.30%     84.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6432271      6.32%     91.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2665520      2.62%     93.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1405579      1.38%     95.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       922819      0.91%     96.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1826114      1.79%     97.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       423793      0.42%     98.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1756482      1.72%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    101852201                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            58981554                       # Number of instructions committed
system.cpu1.commit.committedOps              71603833                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23605311                       # Number of memory references committed
system.cpu1.commit.loads                     12936178                       # Number of loads committed
system.cpu1.commit.membars                     439363                       # Number of memory barriers committed
system.cpu1.commit.branches                  13694258                       # Number of branches committed
system.cpu1.commit.fp_insts                      5590                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62751370                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2679190                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        47937101     66.95%     66.95% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57311      0.08%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4110      0.01%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       12936178     18.07%     85.10% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10669133     14.90%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71603833                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1756482                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   170496195                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168311101                       # The number of ROB writes
system.cpu1.timesIdled                         389572                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2612002                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2951648369                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   58897215                       # Number of Instructions Simulated
system.cpu1.committedOps                     71519494                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.816760                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.816760                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.550430                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.550430                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84567520                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48323955                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16256                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13038                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                274360839                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                28850413                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              191580382                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                795927                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30210                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30210                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480421                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347059161                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36834571                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36411                       # number of replacements
system.iocache.tags.tagsinuse                1.036460                       # Cycle average of tags in use
system.iocache.tags.total_refs                     28                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36427                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000769                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234008190000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.036460                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064779                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064779                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328229                       # Number of tag accesses
system.iocache.tags.data_accesses              328229                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide           27                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total           27                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36197                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36197                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          249                       # number of overall misses
system.iocache.overall_misses::total              249                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29657377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29657377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9617288213                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9617288213                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29657377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29657377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29657377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29657377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.999255                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.999255                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119105.931727                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119105.931727                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265692.963864                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265692.963864                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119105.931727                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119105.931727                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119105.931727                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119105.931727                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         56457                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7214                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.826033                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36162                       # number of writebacks
system.iocache.writebacks::total                36162                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36197                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36197                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16708377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16708377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7734902355                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7734902355                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16708377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16708377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16708377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16708377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67101.915663                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67101.915663                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213689.044810                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213689.044810                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67101.915663                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67101.915663                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67101.915663                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67101.915663                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104467                       # number of replacements
system.l2c.tags.tagsinuse                65129.957708                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3116952                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169707                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    18.366667                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48713.108693                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    48.622899                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000234                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5546.203044                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2803.513756                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    43.406508                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4962.784204                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3012.318369                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.743303                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000742                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.084628                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000662                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.075726                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.045964                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993804                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           90                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65150                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           90                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3220                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9019                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52534                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001373                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994110                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 29257096                       # Number of tag accesses
system.l2c.tags.data_accesses                29257096                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        37572                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         9067                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             969052                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             275148                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36337                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7588                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             957278                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             266835                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2558877                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          703765                       # number of Writeback hits
system.l2c.Writeback_hits::total               703765                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              49                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              57                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 106                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                52                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            78975                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            77026                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156001                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         37572                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          9067                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              969052                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              354123                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36337                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7588                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              957278                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              343861                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2714878                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        37572                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         9067                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             969052                       # number of overall hits
system.l2c.overall_hits::cpu0.data             354123                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36337                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7588                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             957278                       # number of overall hits
system.l2c.overall_hits::cpu1.data             343861                       # number of overall hits
system.l2c.overall_hits::total                2714878                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           69                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            11048                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6910                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           64                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             9843                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             8238                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36173                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1336                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1398                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2734                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           12                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           14                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              26                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73855                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          66651                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140506                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           69                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             11048                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             80765                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           64                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9843                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             74889                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176679                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           69                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            11048                       # number of overall misses
system.l2c.overall_misses::cpu0.data            80765                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           64                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9843                       # number of overall misses
system.l2c.overall_misses::cpu1.data            74889                       # number of overall misses
system.l2c.overall_misses::total               176679                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5336500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    838505750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    551999991                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5114500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    750478500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    687098992                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2838608733                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       370984                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       464480                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       835464                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       262495                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       139494                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       401989                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5637036528                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5153264325                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10790300853                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5336500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    838505750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6189036519                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5114500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    750478500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   5840363317                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     13628909586                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5336500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    838505750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6189036519                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5114500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    750478500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   5840363317                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    13628909586                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        37641                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         9068                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         980100                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         282058                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36401                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7588                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         967121                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         275073                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2595050                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       703765                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           703765                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1385                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1455                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2840                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           30                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           48                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            78                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       152830                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       143677                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296507                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        37641                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         9068                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          980100                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          434888                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36401                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7588                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          967121                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          418750                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2891557                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        37641                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         9068                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         980100                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         434888                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36401                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7588                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         967121                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         418750                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2891557                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001833                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000110                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.011272                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.024499                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001758                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010178                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.029948                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.013939                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.964621                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.960825                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.962676                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.291667                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.483249                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.463895                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.473871                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001833                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000110                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.011272                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.185714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001758                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010178                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.178839                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061102                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001833                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000110                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.011272                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.185714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001758                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010178                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.178839                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061102                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77340.579710                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75896.610246                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 79884.224457                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79914.062500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76244.894849                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 83406.044185                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 78473.135571                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   277.682635                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   332.246066                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   305.583029                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 21874.583333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9963.857143                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15461.115385                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76325.726464                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77317.134402                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76796.014782                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77340.579710                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 75896.610246                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 76630.180388                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79914.062500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76244.894849                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77986.931552                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77139.386039                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77340.579710                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 75896.610246                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 76630.180388                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79914.062500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76244.894849                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77986.931552                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77139.386039                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95556                       # number of writebacks
system.l2c.writebacks::total                    95556                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            69                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            68                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               148                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             69                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             68                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                148                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            69                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            68                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               148                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           69                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        11041                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6841                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           64                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         9839                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         8170                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           36025                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1336                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1398                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2734                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           14                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           26                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73855                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        66651                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140506                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           69                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11041                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        80696                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           64                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9839                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        74821                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176531                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           69                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11041                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        80696                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           64                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9839                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        74821                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176531                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4480000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    699224000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    462918491                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4323000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    626250000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    581032492                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2378290483                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13361336                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14241398                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     27602734                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       221010                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       140014                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       361024                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4714978472                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4324409175                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9039387647                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      4480000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    699224000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5177896963                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      4323000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    626250000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4905441667                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  11417678130                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      4480000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    699224000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5177896963                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      4323000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    626250000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4905441667                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  11417678130                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     35704750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2941058500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2438229500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5414992750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2208397500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1893885000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4102282500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     35704750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5149456000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4332114500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   9517275250                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001833                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000110                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.011265                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.024254                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001758                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010173                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.029701                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.013882                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.964621                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.960825                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.962676                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.291667                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.483249                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.463895                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.473871                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001833                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000110                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.011265                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.185556                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001758                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010173                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.178677                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061050                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001833                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000110                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.011265                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.185556                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001758                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010173                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.178677                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061050                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63329.770854                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67668.248940                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63649.761155                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71117.808078                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 66017.778848                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10186.979971                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.098756                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18417.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13885.538462                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.019186                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64881.384750                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64334.531244                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63329.770854                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64165.472427                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63649.761155                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65562.364403                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 64678.034623                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63329.770854                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64165.472427                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63649.761155                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65562.364403                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 64678.034623                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               68075                       # Transaction distribution
system.membus.trans_dist::ReadResp              68074                       # Transaction distribution
system.membus.trans_dist::WriteReq              27609                       # Transaction distribution
system.membus.trans_dist::WriteResp             27609                       # Transaction distribution
system.membus.trans_dist::Writeback            131718                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36196                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4633                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4659                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138608                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138608                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465023                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       572669                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 681489                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17335192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17499181                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4631872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22131053                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              522                       # Total snoops (count)
system.membus.snoop_fanout::samples            347455                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  347455    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              347455                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81552000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               15812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1759525499                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1732085345                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38509429                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            2659236                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2659139                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27609                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27609                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           703765                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2841                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            78                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2918                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296507                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296507                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3896051                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2534528                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        43103                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       170141                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               6643823                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124664384                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99866733                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        66624                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       296168                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              224893909                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           68735                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3666824                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            5.009939                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.099200                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                3630378     99.01%     99.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                  36446      0.99%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3666824                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4674174231                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           688500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        8773601584                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3912223359                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          26520841                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          96916821                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3042                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------