path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.804565                       # Number of seconds simulated
sim_ticks                                2804565276000                       # Number of ticks simulated
final_tick                               2804565276000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 101255                       # Simulator instruction rate (inst/s)
host_op_rate                                   122895                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2428978767                       # Simulator tick rate (ticks/s)
host_mem_usage                                 586736                       # Number of bytes of host memory used
host_seconds                                  1154.63                       # Real time elapsed on the host
sim_insts                                   116911386                       # Number of instructions simulated
sim_ops                                     141898031                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         4032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           684608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5013536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           686976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4780808                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11175528                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       684608                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       686976                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1371584                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8423424                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8440948                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           63                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10697                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             78855                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           71                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10734                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             74702                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175138                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131616                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               135997                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              244105                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1787634                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1620                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              244949                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1704652                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3984763                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         244105                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         244949                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             489054                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3003469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3009717                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3003469                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             244105                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1793879                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1620                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             244949                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1704655                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6994480                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175139                       # Number of read requests accepted
system.physmem.writeReqs                       135997                       # Number of write requests accepted
system.physmem.readBursts                      175139                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     135997                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11199488                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8453504                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11175592                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8440948                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11119                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11081                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11640                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11194                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11361                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11364                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11912                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11778                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10214                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10385                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10562                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9757                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10332                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11401                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10617                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10275                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8313                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8440                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9041                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8539                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8335                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8538                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8956                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8814                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7742                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7782                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7931                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7392                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7874                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8749                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8038                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7602                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    2804565097500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174583                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131616                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103547                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8418                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1715                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6955                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       25                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64824                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      303.173639                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     178.438923                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.896368                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24325     37.52%     37.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16003     24.69%     62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6580     10.15%     72.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3580      5.52%     77.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2814      4.34%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1563      2.41%     84.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1120      1.73%     86.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1064      1.64%     88.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7775     11.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64824                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6666                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.249925                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      478.560077                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6664     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6666                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6666                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.814881                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.232650                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.394597                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                11      0.17%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.11%      0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                4      0.06%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              12      0.18%      0.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5751     86.27%     86.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             132      1.98%     88.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              86      1.29%     90.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              46      0.69%     90.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             272      4.08%     94.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              61      0.92%     95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              24      0.36%     96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              14      0.21%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              13      0.20%     96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.12%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.09%     96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             155      2.33%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.08%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.02%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.05%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               9      0.14%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.05%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.09%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             8      0.12%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.17%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6666                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2635898000                       # Total ticks spent queuing
system.physmem.totMemAccLat                5916998000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    874960000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15062.96                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33812.96                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.88                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144615                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97638                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.64                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.91                       # Row buffer hit rate for writes
system.physmem.avgGap                      9013952.41                       # Average gap between requests
system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  258899760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  141264750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 713294400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                446964480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           183180260640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            77917696695                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1614387610500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1877045991225                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.283406                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2685583279000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     93650440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     25331546500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  231169680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  126134250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 651635400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                408952800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           183180260640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            76668612660                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1615483298250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1876750063680                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.177890                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2687409308250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     93650440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     23501044250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              274                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          274                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             274                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26568186                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13757380                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           498035                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            15521852                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8027077                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            51.714686                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6610878                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28698                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4514253                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           4401271                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          112982                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        32075                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    58842                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               58842                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17810                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14845                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        26187                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        32655                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   632.200276                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3881.293866                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        32316     98.96%     98.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          258      0.79%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           49      0.15%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           18      0.06%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        32655                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12803                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12389.596188                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10179.754175                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7970.003099                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-8191         4327     33.80%     33.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5843     45.64%     79.43% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2208     17.25%     96.68% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::24576-32767          213      1.66%     98.34% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-40959          113      0.88%     99.23% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::40960-49151           69      0.54%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-57343           10      0.08%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::73728-81919            1      0.01%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-90111            7      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::90112-98303            4      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-106495            4      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12803                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  80889831836                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.654695                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.499418                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  80811540336     99.90%     99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     53922000      0.07%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     11918500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4370000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2811000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1565500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13       964000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      1576000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       313500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       197500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21       119500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        36500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       186500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        25500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        24000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31       261500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  80889831836                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3539     69.42%     69.42% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1559     30.58%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5098                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58842                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58842                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5098                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5098                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        63940                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13766353                       # DTB read hits
system.cpu0.dtb.read_misses                     49364                       # DTB read misses
system.cpu0.dtb.write_hits                   10259633                       # DTB write hits
system.cpu0.dtb.write_misses                     9478                       # DTB write misses
system.cpu0.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3387                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      892                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1297                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      658                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                13815717                       # DTB read accesses
system.cpu0.dtb.write_accesses               10269111                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24025986                       # DTB hits
system.cpu0.dtb.misses                          58842                       # DTB misses
system.cpu0.dtb.accesses                     24084828                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     7885                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7885                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2420                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4556                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          909                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         6976                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1209.934060                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  4914.790808                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6588     94.44%     94.44% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          240      3.44%     97.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575           86      1.23%     99.11% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           32      0.46%     99.57% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           14      0.20%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151            8      0.11%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         6976                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3232                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 11727.877475                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9548.081517                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7530.941401                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191         1404     43.44%     43.44% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1169     36.17%     79.61% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          601     18.60%     98.21% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.08%     99.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           11      0.34%     99.63% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            7      0.22%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3232                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  33645212080                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.830268                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.375687                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     5713730428     16.98%     16.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    27928860152     83.01%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2282500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         253000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4          59500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          26500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  33645212080                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1739     74.86%     74.86% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          584     25.14%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2323                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7885                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7885                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2323                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2323                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10208                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    19916742                       # ITB inst hits
system.cpu0.itb.inst_misses                      7885                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2222                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1235                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                19924627                       # ITB inst accesses
system.cpu0.itb.hits                         19916742                       # DTB hits
system.cpu0.itb.misses                           7885                       # DTB misses
system.cpu0.itb.accesses                     19924627                       # DTB accesses
system.cpu0.numPwrStateTransitions               3162                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1581                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    934903714.786211                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   18749967267.112076                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1545     97.72%     97.72% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10           33      2.09%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.06%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            2      0.13%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499976755656                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1581                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   1326482502923                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478082773077                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       106412241                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39807667                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     102389396                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26568186                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19039226                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     62026637                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3110102                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    107465                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                3850                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              421                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       155531                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       127911                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          368                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 19914927                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               350256                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3998                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         103784864                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.186876                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.290419                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                75488274     72.74%     72.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3815041      3.68%     76.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2353974      2.27%     78.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 7979190      7.69%     86.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1587719      1.53%     87.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  994623      0.96%     88.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6057014      5.84%     94.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1019102      0.98%     95.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4489927      4.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           103784864                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.249672                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.962196                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27473759                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58173812                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15291505                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1432841                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1412652                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1823499                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               144249                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              84520525                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               475248                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1412652                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                28280194                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6736942                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      43934801                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 15910349                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7509629                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              80887884                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 3905                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1038108                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                267593                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               5492226                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           83297539                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            373007231                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        90195870                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6961                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             70398676                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12898863                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1526830                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1432825                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8315442                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14569662                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11312381                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1968850                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2730392                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  77926980                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1058477                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 74778360                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            90763                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10627433                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23204178                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        112737                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    103784864                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.720513                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.414461                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           73826337     71.13%     71.13% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10059193      9.69%     80.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7635969      7.36%     88.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6342907      6.11%     94.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2283033      2.20%     96.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1456613      1.40%     97.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1481922      1.43%     99.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             479341      0.46%     99.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             219549      0.21%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      103784864                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  96825      8.81%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                525523     47.82%     56.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               476662     43.37%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2194      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             49752146     66.53%     66.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57180      0.08%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4372      0.01%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14148422     18.92%     85.54% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10814044     14.46%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              74778360                       # Type of FU issued
system.cpu0.iq.rate                          0.702723                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1099011                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014697                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         254516336                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         89657321                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     72555337                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              15022                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              8945                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6550                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              75867097                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   8080                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          352646                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2054023                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2148                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54598                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1028244                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       203435                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        82087                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1412652                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5873643                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               655367                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           79110277                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           106917                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14569662                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11312381                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            551702                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44436                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               599579                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54598                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        206066                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       219140                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              425206                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             74227613                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             13928296                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           492013                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       124820                       # number of nop insts executed
system.cpu0.iew.exec_refs                    24646290                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14030699                       # Number of branches executed
system.cpu0.iew.exec_stores                  10717994                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.697548                       # Inst execution rate
system.cpu0.iew.wb_sent                      73714298                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     72561887                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 37730883                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 65693607                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.681894                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.574346                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10582820                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         945740                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           355599                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    101354368                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.675249                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.564531                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     74626886     73.63%     73.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12088537     11.93%     85.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6044710      5.96%     91.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2569505      2.54%     94.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1279385      1.26%     95.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       839259      0.83%     96.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1807050      1.78%     97.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       395487      0.39%     98.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1703549      1.68%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    101354368                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            56197107                       # Number of instructions committed
system.cpu0.commit.committedOps              68439408                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      22799776                       # Number of memory references committed
system.cpu0.commit.loads                     12515639                       # Number of loads committed
system.cpu0.commit.membars                     380661                       # Number of memory barriers committed
system.cpu0.commit.branches                  13306067                       # Number of branches committed
system.cpu0.commit.fp_insts                      6109                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 59926267                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2612600                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        45579664     66.60%     66.60% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55599      0.08%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4369      0.01%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.69% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12515639     18.29%     84.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10284137     15.03%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         68439408                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1703549                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   166286675                       # The number of ROB reads
system.cpu0.rob.rob_writes                  160474100                       # The number of ROB writes
system.cpu0.timesIdled                         401346                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2627377                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2956165518                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   56115723                       # Number of Instructions Simulated
system.cpu0.committedOps                     68358024                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.896300                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.896300                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.527343                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.527343                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                80796649                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46187734                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    17075                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13292                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                262559417                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27235047                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              188033527                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                725405                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           851456                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.984383                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42342080                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           851968                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.699144                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         92671500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   183.852002                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   328.132381                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359086                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.640884                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999969                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189174693                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189174693                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     12241825                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12926435                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25168260                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7660735                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8240746                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15901481                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177973                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       185251                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       363224                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210012                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236500                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446512                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216376                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       242998                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459374                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     19902560                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21167181                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41069741                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20080533                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21352432                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41432965                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       399594                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       432990                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       832584                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1948359                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1749519                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3697878                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        78958                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       104644                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183602                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13682                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        13994                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27676                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           42                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           43                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           85                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2347953                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2182509                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4530462                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2426911                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2287153                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4714064                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5954800500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6571091500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12525892000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  86724909183                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  78793160939                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 165518070122                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    180271000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    207675500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    387946500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       854000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       810000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1664000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  92679709683                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  85364252439                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 178043962122                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  92679709683                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  85364252439                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 178043962122                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12641419                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13359425                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26000844                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9609094                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9990265                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19599359                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       256931                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       289895                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       546826                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223694                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250494                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474188                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216418                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243041                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459459                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22250513                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23349690                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45600203                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22507444                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23639585                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46147029                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031610                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032411                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032021                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202762                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.175122                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188673                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.307312                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.360972                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335759                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061164                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055866                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058365                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000194                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000177                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000185                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105524                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093471                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099352                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107827                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096751                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102153                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.126909                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15176.081434                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15044.598503                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44511.770769                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45037.042146                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44760.284174                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13175.778395                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14840.324425                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14017.433878                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20333.333333                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18837.209302                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19576.470588                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39472.557450                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39112.898246                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39299.294889                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38188.342994                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37323.367715                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37768.677329                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1136536                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       185396                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            52540                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2932                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.631823                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    63.231924                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       702421                       # number of writebacks
system.cpu0.dcache.writebacks::total           702421                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       189399                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       219838                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       409237                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1792246                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1606080                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3398326                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9509                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9097                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18606                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1981645                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1825918                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3807563                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1981645                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1825918                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3807563                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210195                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       213152                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       423347                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156113                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143439                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299552                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        54836                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        68047                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122883                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4173                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4897                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9070                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           42                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           43                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           85                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       366308                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       356591                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       722899                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       421144                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       424638                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       845782                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16327                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14800                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15920                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11664                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32247                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26464                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2991440000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3075969500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6067409500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7265470369                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6699556943                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13965027312                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    768840000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    969057000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737897000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     54425000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82975500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137400500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       812000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       767000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1579000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10256910369                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9775526443                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  20032436812                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11025750369                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10744583443                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  21770333812                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3299950500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3004338000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6304288500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3299950500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3004338000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6304288500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016627                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015955                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016282                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016246                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014358                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015284                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.213427                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.234730                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224720                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018655                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019549                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019127                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000194                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000177                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000185                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016463                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015272                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015853                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018711                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017963                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018328                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14231.737196                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14430.873274                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14332.000699                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46539.816473                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46706.662365                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46619.709807                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14020.716318                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14240.995194                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14142.696712                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13042.175893                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16944.149479                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15148.897464                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17837.209302                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18576.470588                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28000.781771                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27413.833897                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27711.252626                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26180.475963                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25302.924945                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25739.887834                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202116.157285                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202995.810811                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202534.407428                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102333.565913                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113525.468561                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107378.319225                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1933722                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.561114                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38706921                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1934234                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.011499                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9780443500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   229.301603                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   282.259511                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.447855                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.551288                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999143                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          227                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42723428                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42723428                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     18879325                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19827596                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38706921                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     18879325                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19827596                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38706921                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     18879325                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19827596                       # number of overall hits
system.cpu0.icache.overall_hits::total       38706921                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1034931                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1047206                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2082137                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1034931                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1047206                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2082137                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1034931                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1047206                       # number of overall misses
system.cpu0.icache.overall_misses::total      2082137                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14029669987                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14232269988                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28261939975                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14029669987                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14232269988                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28261939975                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14029669987                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14232269988                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28261939975                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     19914256                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20874802                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40789058                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     19914256                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20874802                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40789058                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     19914256                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20874802                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40789058                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051969                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050166                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051046                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051969                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050166                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051046                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051969                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050166                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051046                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13556.140445                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13590.707070                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13573.525649                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13556.140445                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13590.707070                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13573.525649                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13556.140445                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13590.707070                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13573.525649                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        12122                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              623                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.457464                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1933722                       # number of writebacks
system.cpu0.icache.writebacks::total          1933722                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71718                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76048                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       147766                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71718                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76048                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       147766                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71718                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76048                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       147766                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       963213                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       971158                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1934371                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       963213                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       971158                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1934371                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       963213                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       971158                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1934371                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12408483492                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12567838491                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  24976321983                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12408483492                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12567838491                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  24976321983                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12408483492                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12567838491                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  24976321983                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     53482500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     53482500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047424                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047424                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047424                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12911.857127                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12911.857127                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12911.857127                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171                       # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups               27798204                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14470719                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           518667                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17368333                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                8539564                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            49.167436                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6849209                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29775                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4616738                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           4505967                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          110771                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        32761                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    58826                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58826                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18872                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14273                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25681                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33145                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   585.865138                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3677.608561                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32788     98.92%     98.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          287      0.87%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           48      0.14%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           12      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919            7      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33145                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        13049                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12961.567936                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10723.007113                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7830.239554                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         3942     30.21%     30.21% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         6071     46.52%     76.73% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2547     19.52%     96.25% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          256      1.96%     98.21% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959          106      0.81%     99.03% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151          110      0.84%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            9      0.07%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            4      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        13049                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  90145173428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.714972                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.473357                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  90067700428     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     53747000      0.06%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     11656000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4441500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2654000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1196000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       758000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      1848500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       266500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       153500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21       119500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23       164000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       321500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29         7500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31       104500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  90145173428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3714     69.38%     69.38% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1639     30.62%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5353                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58826                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58826                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5353                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5353                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        64179                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14560023                       # DTB read hits
system.cpu1.dtb.read_misses                     50490                       # DTB read misses
system.cpu1.dtb.write_hits                   10636581                       # DTB write hits
system.cpu1.dtb.write_misses                     8336                       # DTB write misses
system.cpu1.dtb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3352                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      784                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1139                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      621                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14610513                       # DTB read accesses
system.cpu1.dtb.write_accesses               10644917                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25196604                       # DTB hits
system.cpu1.dtb.misses                          58826                       # DTB misses
system.cpu1.dtb.accesses                     25255430                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     7718                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7718                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2370                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4511                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          837                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         6881                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1585.234704                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6902.284757                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-16383         6686     97.17%     97.17% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-32767          129      1.87%     99.04% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-49151           34      0.49%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-65535           16      0.23%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-81919            8      0.12%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-98303            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-114687            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-147455            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         6881                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         3170                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12167.034700                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9891.169611                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8057.359944                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         2478     78.17%     78.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          663     20.91%     99.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-49151           24      0.76%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-65535            4      0.13%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         3170                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  34310573580                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.816220                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.387901                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     6310834876     18.39%     18.39% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    27996313204     81.60%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2293000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         658500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         333500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          91000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6          49500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  34310573580                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1756     75.27%     75.27% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          577     24.73%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2333                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7718                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7718                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2333                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2333                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10051                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20877340                       # ITB inst hits
system.cpu1.itb.inst_misses                      7718                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         176                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2200                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1355                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20885058                       # ITB inst accesses
system.cpu1.itb.hits                         20877340                       # DTB hits
system.cpu1.itb.misses                           7718                       # DTB misses
system.cpu1.itb.accesses                     20885058                       # DTB accesses
system.cpu1.numPwrStateTransitions               2914                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         1457                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    836230234.840082                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   15860875866.076208                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1422     97.60%     97.60% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10           32      2.20%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.07%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.07%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 499953982692                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           1457                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   1586177823838                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218387452162                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       109746430                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40895986                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108462285                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27798204                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19894740                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     64228270                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3210503                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    105636                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              364                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       136679                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       127439                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          259                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20874803                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               362169                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3960                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         107107154                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.215557                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.316339                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                77373213     72.24%     72.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3963895      3.70%     75.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2490638      2.33%     78.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8243801      7.70%     85.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1611366      1.50%     87.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1186347      1.11%     88.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6289453      5.87%     94.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1183134      1.10%     95.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4765307      4.45%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           107107154                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.253295                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.988299                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27921866                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             60067662                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15890093                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1767595                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1459620                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1999442                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               147513                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              90274906                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               488786                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1459620                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28874792                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                5214847                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      47170555                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16697712                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              7689265                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              86435062                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2196                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1738246                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                216044                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               4936698                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           89654559                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            397922384                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        96312255                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6119                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             76275352                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13379191                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1604332                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1503289                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10206476                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15384658                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11766815                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2187303                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2806337                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  83309557                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1151208                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 79998202                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91456                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       10920754                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24595973                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        103002                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    107107154                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.746899                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.431011                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           75017466     70.04%     70.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10766554     10.05%     80.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8172110      7.63%     87.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6817962      6.37%     94.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2501926      2.34%     96.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1553712      1.45%     97.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1535084      1.43%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             491946      0.46%     99.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             250394      0.23%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      107107154                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 114052      9.86%      9.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     7      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.87% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                527984     45.67%     55.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               514092     44.47%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              143      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             53728973     67.16%     67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59111      0.07%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4201      0.01%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14948674     18.69%     85.93% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11257095     14.07%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              79998202                       # Type of FU issued
system.cpu1.iq.rate                          0.728937                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1156135                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014452                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268337940                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         95424057                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     77696965                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              13209                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7523                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5720                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              81147055                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7139                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          351994                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2099522                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2035                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51133                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1012143                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       193136                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       112329                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1459620                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4216196                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               746434                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           84577573                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           108382                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15384658                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11766815                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            582249                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44240                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               689439                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51133                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        222163                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       226496                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              448659                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             79436293                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14722883                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           503246                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       116808                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25882990                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14805311                       # Number of branches executed
system.cpu1.iew.exec_stores                  11160107                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.723817                       # Inst execution rate
system.cpu1.iew.wb_sent                      78872387                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     77702685                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 41015418                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 71702227                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.708020                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.572024                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       10950045                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1048206                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           372999                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    104597545                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.703779                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.594224                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     76066046     72.72%     72.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12690674     12.13%     84.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6559681      6.27%     91.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2745344      2.62%     93.75% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1426512      1.36%     95.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       937004      0.90%     96.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1881396      1.80%     97.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       439088      0.42%     98.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1851800      1.77%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    104597545                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            60869184                       # Number of instructions committed
system.cpu1.commit.committedOps              73613528                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      24039808                       # Number of memory references committed
system.cpu1.commit.loads                     13285136                       # Number of loads committed
system.cpu1.commit.membars                     433641                       # Number of memory barriers committed
system.cpu1.commit.branches                  14069734                       # Number of branches committed
system.cpu1.commit.fp_insts                      5319                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 64506591                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2723384                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        49512063     67.26%     67.26% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57459      0.08%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4198      0.01%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.34% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13285136     18.05%     85.39% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10754672     14.61%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         73613528                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1851800                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   174575850                       # The number of ROB reads
system.cpu1.rob.rob_writes                  171636243                       # The number of ROB writes
system.cpu1.timesIdled                         396046                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2639276                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2436774880                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   60795663                       # Number of Instructions Simulated
system.cpu1.committedOps                     73540007                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.805169                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.805169                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.553965                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.553965                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                86363747                       # number of integer regfile reads
system.cpu1.int_regfile_writes               49530768                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16607                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   12960                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                280533576                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29711691                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              195918297                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                794253                       # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49485500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                87500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               623500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6415000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38220500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187814925                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36409                       # number of replacements
system.iocache.tags.tagsinuse                0.981737                       # Cycle average of tags in use
system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234297107000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.981737                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.061359                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.061359                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
system.iocache.tags.data_accesses              328227                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
system.iocache.demand_hits::total                  29                       # number of demand (read+write) hits
system.iocache.overall_hits::realview.ide           29                       # number of overall hits
system.iocache.overall_hits::total                 29                       # number of overall hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
system.iocache.overall_misses::total            36444                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31227677                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31227677                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4282542248                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4282542248                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4313769925                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4313769925                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4313769925                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4313769925                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36473                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36473                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36473                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36473                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide     0.999205                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 125412.357430                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125412.357430                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118318.614394                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118318.614394                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118367.081687                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118367.081687                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118367.081687                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118367.081687                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           191                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    95.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36160                       # number of writebacks
system.iocache.writebacks::total                36160                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36444                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18777677                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18777677                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2470659836                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2470659836                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2489437513                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2489437513                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2489437513                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2489437513                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.999205                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.999205                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75412.357430                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75412.357430                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68259.699848                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68259.699848                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68308.569669                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68308.569669                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68308.569669                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68308.569669                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   104028                       # number of replacements
system.l2c.tags.tagsinuse                65127.134110                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5124806                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169274                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.275211                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48520.895373                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    39.974246                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000253                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4816.133274                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2437.796190                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    54.318644                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5831.963518                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3426.052612                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.740370                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000610                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.073488                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.037198                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000829                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.088989                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.052277                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993761                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           66                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65180                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3219                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8979                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52594                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001007                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994568                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45359933                       # Number of tag accesses
system.l2c.tags.data_accesses                45359933                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker        34998                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6494                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36104                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6670                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  84266                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       702421                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          702421                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1894027                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1894027                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              70                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              58                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 128                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            30                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                64                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            82284                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            74312                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156596                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        952993                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        960231                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1913224                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       262086                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       277994                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           540080                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         34998                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6494                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              952993                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              344370                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36104                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6670                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              960231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              352306                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2694166                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        34998                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6494                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             952993                       # number of overall hits
system.l2c.overall_hits::cpu0.data             344370                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36104                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6670                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             960231                       # number of overall hits
system.l2c.overall_hits::cpu1.data             352306                       # number of overall hits
system.l2c.overall_hits::total                2694166                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           63                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           71                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  135                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1443                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1292                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2735                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           12                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            9                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              21                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          72336                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          67790                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140126                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        10050                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10740                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20790                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         7098                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         8089                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15187                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           63                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             10050                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             79434                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           71                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10740                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             75879                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176238                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           63                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            10050                       # number of overall misses
system.l2c.overall_misses::cpu0.data            79434                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           71                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10740                       # number of overall misses
system.l2c.overall_misses::cpu1.data            75879                       # number of overall misses
system.l2c.overall_misses::total               176238                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5438000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5981000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       11502500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       318500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       435500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       754000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       257500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       140000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       397500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6112105000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5653905000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11766010000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst    831609998                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    901691000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1733300998                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    612012500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    728546000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1340558500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5438000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    831609998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6724117500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5981000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    901691000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6382451000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     14851371998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5438000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    831609998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6724117500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5981000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    901691000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6382451000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    14851371998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        35061                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6495                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36175                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6670                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              84401                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       702421                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       702421                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1894027                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1894027                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1513                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1350                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2863                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           42                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           43                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            85                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       154620                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       142102                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296722                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       963043                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       970971                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1934014                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       269184                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       286083                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       555267                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        35061                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6495                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          963043                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          423804                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36175                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6670                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          970971                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          428185                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2870404                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        35061                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6495                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         963043                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         423804                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36175                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6670                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         970971                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         428185                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2870404                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001797                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000154                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001963                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001600                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.953734                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.957037                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.955292                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.209302                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.247059                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.467831                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.477052                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472247                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010436                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011061                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010750                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.026369                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.028275                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027351                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001797                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000154                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010436                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.187431                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001963                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011061                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.177211                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061398                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001797                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000154                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010436                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.187431                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001963                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011061                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.177211                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061398                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86317.460317                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84239.436620                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 85203.703704                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   220.720721                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   337.074303                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   275.685558                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 21458.333333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15555.555556                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 18928.571429                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84496.032404                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83403.230565                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 83967.357949                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82747.263483                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83956.331471                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 83371.861376                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86223.231896                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90066.262826                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 88270.132350                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86317.460317                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82747.263483                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 84650.370119                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84239.436620                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83956.331471                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84113.536024                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 84268.840988                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86317.460317                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82747.263483                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 84650.370119                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84239.436620                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83956.331471                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84113.536024                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 84268.840988                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               95456                       # number of writebacks
system.l2c.writebacks::total                    95456                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           74                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           64                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          138                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             64                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                149                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            74                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            64                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               149                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           63                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           71                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             135                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1443                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1292                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2735                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            9                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           21                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        72336                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        67790                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140126                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10044                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10735                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20779                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         7024                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         8025                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15049                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           63                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        10044                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        79360                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           71                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10735                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        75815                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176089                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           63                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        10044                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        79360                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           71                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10735                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        75815                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176089                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16327                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14800                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31794                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15920                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11664                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32247                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26464                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59378                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4808000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5271000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     10152500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27463500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     24555000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     52018500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       288000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       228000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       516000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5388745000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4976005000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10364750000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    730832498                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    794082501                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1524914999                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    536116501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    643856500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1179973001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      4808000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    730832498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5924861501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      5271000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    794082501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5619861500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  13079790500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      4808000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    730832498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5924861501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      5271000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    794082501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5619861500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  13079790500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3095805000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2819282000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5958190498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3095805000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2819282000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5958190498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000154                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001963                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001600                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.953734                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.957037                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.955292                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.209302                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.247059                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.467831                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.477052                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472247                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010429                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010744                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.026094                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.028051                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027102                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000154                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.187256                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001963                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.177061                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061346                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000154                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.187256                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001963                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.177061                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061346                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 75203.703704                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19032.224532                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19005.417957                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19019.561243                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        24000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25333.333333                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24571.428571                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74496.032404                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73403.230565                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73967.357949                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73387.314067                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76326.381122                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80231.339564                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78408.731544                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74658.033027                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74125.984304                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 74279.429720                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74658.033027                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74125.984304                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 74279.429720                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189612.604888                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190492.027027                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187399.839529                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96002.883989                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106532.723700                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 100343.401563                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        355735                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       149872                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               31794                       # Transaction distribution
system.membus.trans_dist::ReadResp              68005                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131616                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8821                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4625                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             21                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138237                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138237                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36212                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       467969                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       575541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 648409                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17301276                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17465309                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19780509                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              523                       # Total snoops (count)
system.membus.snoopTraffic                      33344                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            274669                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019252                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.137411                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  269381     98.07%     98.07% # Request fanout histogram
system.membus.snoop_fanout::1                    5288      1.93%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              274669                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95445000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1705498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           921900685                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1007122750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1322824                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      5612083                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2825755                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        47584                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            189                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq             149636                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2639439                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       797877                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1933722                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          157607                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2864                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            85                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2948                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296722                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296722                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1934371                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       555503                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4762                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5803440                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2678918                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        36089                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166154                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8684601                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247577728                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99675933                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        52660                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              347591265                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          142991                       # Total snoops (count)
system.toL2Bus.snoopTraffic                   6276420                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          3079674                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027770                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.164315                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2994150     97.22%     97.22% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  85524      2.78%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3079674                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5529901884                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           310676                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2904308481                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1324888971                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          22963918                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          95377065                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------