path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.822600                       # Number of seconds simulated
sim_ticks                                2822599892000                       # Number of ticks simulated
final_tick                               2822599892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 133046                       # Simulator instruction rate (inst/s)
host_op_rate                                   161483                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3211959283                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588416                       # Number of bytes of host memory used
host_seconds                                   878.78                       # Real time elapsed on the host
sim_insts                                   116918246                       # Number of instructions simulated
sim_ops                                     141908177                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         3520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           680320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5169248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           692096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4617224                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11168360                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       680320                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       692096                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1372416                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8444928                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8462452                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           55                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10630                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             81288                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           77                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10814                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             72146                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175026                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131952                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136333                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1247                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              241026                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1831378                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1746                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              245198                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1635805                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3956763                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         241026                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         245198                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             486224                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2991897                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6206                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2998105                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2991897                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1247                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             241026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1837584                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             245198                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1635808                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6954869                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175027                       # Number of read requests accepted
system.physmem.writeReqs                       136333                       # Number of write requests accepted
system.physmem.readBursts                      175027                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     136333                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11191872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8475200                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11168424                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8462452                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12029                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11047                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10999                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11203                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11530                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11229                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11724                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11678                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10819                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11281                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10383                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9840                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10191                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10806                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10203                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9911                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8929                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8449                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8574                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8748                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8391                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8421                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8483                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8696                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8251                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8705                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8031                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7697                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7872                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8288                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7672                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7218                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    2822599715500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174471                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131952                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103905                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62755                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6452                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1740                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7065                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8086                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65893                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.468851                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.439020                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.218127                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          25043     38.01%     38.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15993     24.27%     62.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6828     10.36%     72.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3804      5.77%     78.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2929      4.45%     82.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1589      2.41%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1152      1.75%     87.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1015      1.54%     88.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7540     11.44%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65893                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6529                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.779139                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      488.211156                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6527     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6529                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6529                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.282585                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.331559                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.915612                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                13      0.20%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 5      0.08%      0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                7      0.11%      0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              17      0.26%      0.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5686     87.09%     87.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             170      2.60%     90.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              40      0.61%     90.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              72      1.10%     92.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              34      0.52%     92.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              20      0.31%     92.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              58      0.89%     93.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              12      0.18%     93.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             145      2.22%     96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               7      0.11%     96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              12      0.18%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              68      1.04%     97.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.08%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              23      0.35%     98.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             100      1.53%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             7      0.11%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             4      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6529                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2732692250                       # Total ticks spent queuing
system.physmem.totMemAccLat                6011561000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    874365000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15626.72                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34376.72                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.74                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.39                       # Average write queue length when enqueuing
system.physmem.readRowHits                     143838                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97566                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.66                       # Row buffer hit rate for writes
system.physmem.avgGap                      9065389.63                       # Average gap between requests
system.physmem.pageHitRate                      78.55                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  262589040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  143277750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 713224200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                445117680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80173196100                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1623228875250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1889324365620                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.357529                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2700270963250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94252600000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     28070184250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  235562040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  128530875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 650777400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                412996320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79158702690                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1624118781750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1889063436675                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.265086                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2701767276500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94252600000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26580005000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          272                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              272                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          272                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          272                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          272                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             272                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26616996                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13742017                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           493041                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            15603811                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8045769                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            51.562846                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6633595                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28274                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4499378                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           4391333                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          108045                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted        31802                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    58233                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               58233                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17222                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14806                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        26205                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        32028                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   716.310728                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  4455.738407                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        31643     98.80%     98.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          285      0.89%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           60      0.19%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           11      0.03%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        32028                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12683                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13005.479776                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10522.110524                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9554.054292                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        12456     98.21%     98.21% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535          198      1.56%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303            4      0.03%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071           15      0.12%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            9      0.07%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12683                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  95295475040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.626262                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.503838                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  95214863040     99.92%     99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     54562500      0.06%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     11789500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      5218000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      3107500      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1725500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13       925000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      2340500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       429500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       156000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21       103500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        23000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       167000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27         8500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        11000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31        45000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  95295475040                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3556     69.39%     69.39% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1569     30.61%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5125                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58233                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58233                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5125                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5125                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        63358                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    14003627                       # DTB read hits
system.cpu0.dtb.read_misses                     49308                       # DTB read misses
system.cpu0.dtb.write_hits                   10435159                       # DTB write hits
system.cpu0.dtb.write_misses                     8925                       # DTB write misses
system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3323                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      748                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1266                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      726                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14052935                       # DTB read accesses
system.cpu0.dtb.write_accesses               10444084                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24438786                       # DTB hits
system.cpu0.dtb.misses                          58233                       # DTB misses
system.cpu0.dtb.accesses                     24497019                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     7841                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7841                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2269                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4662                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          910                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         6931                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1597.099986                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  6530.842043                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6483     93.54%     93.54% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          245      3.53%     97.07% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          100      1.44%     98.51% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           38      0.55%     99.06% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           21      0.30%     99.37% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.23%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.12%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            6      0.09%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            6      0.09%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-106495            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         6931                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         3149                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12098.126389                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9906.288908                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7800.353471                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2504     79.52%     79.52% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          621     19.72%     99.24% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.60%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            3      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-114687            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         3149                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  35165227396                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.607117                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.488806                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    13821063428     39.30%     39.30% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    21340361468     60.69%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2726000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         763000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         254500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          59000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  35165227396                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1680     75.03%     75.03% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          559     24.97%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2239                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2239                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2239                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10080                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20129466                       # ITB inst hits
system.cpu0.itb.inst_misses                      7841                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2157                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1367                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20137307                       # ITB inst accesses
system.cpu0.itb.hits                         20129466                       # DTB hits
system.cpu0.itb.misses                           7841                       # DTB misses
system.cpu0.itb.accesses                     20137307                       # DTB accesses
system.cpu0.numCycles                       111772551                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39602252                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     104018130                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26616996                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19070697                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     66981465                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3101347                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    109391                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                4554                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              495                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       137372                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       131975                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          607                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20127570                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               345492                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   4051                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         108518747                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.151083                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.270431                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                79947267     73.67%     73.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3818944      3.52%     77.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2390633      2.20%     79.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8016162      7.39%     86.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1540680      1.42%     88.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1082847      1.00%     89.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6027122      5.55%     94.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1035069      0.95%     95.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4660023      4.29%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           108518747                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.238135                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.930623                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27080846                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             63086875                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15439246                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1499474                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1411975                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1879709                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               140548                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              86265439                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               466335                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1411975                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27919581                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6708694                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      45822380                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16094749                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10561036                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              82571629                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1978                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1083684                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                247104                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8473675                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84960464                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            381127577                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        92351519                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6511                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72285025                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12675423                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1561908                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1463600                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8728047                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14766139                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11575214                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          2006179                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2797578                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  79563534                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1113915                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 76525093                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            91014                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10394891                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23261666                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        100529                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    108518747                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.705179                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.408066                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           77980499     71.86%     71.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10237558      9.43%     81.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7702853      7.10%     88.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6507672      6.00%     94.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2342197      2.16%     96.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1521714      1.40%     97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1465392      1.35%     99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             497793      0.46%     99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             263069      0.24%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      108518747                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 115286     10.03%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     2      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.03% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                533290     46.39%     56.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               501036     43.58%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass              257      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             51005106     66.65%     66.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57020      0.07%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4013      0.01%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.73% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14388531     18.80%     85.53% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           11070162     14.47%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              76525093                       # Type of FU issued
system.cpu0.iq.rate                          0.684650                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1149614                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.015023                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         262795692                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         91116693                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     74267630                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              13869                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              8272                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6120                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              77667016                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7434                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          356348                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2003014                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2146                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        53724                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1008418                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       205247                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       123541                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1411975                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5317808                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1170288                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80797143                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           102579                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14766139                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11575214                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            569653                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44979                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1113707                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         53724                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        203717                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       217691                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              421408                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             75980075                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14169520                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           486959                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       119694                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25144307                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14085484                       # Number of branches executed
system.cpu0.iew.exec_stores                  10974787                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.679774                       # Inst execution rate
system.cpu0.iew.wb_sent                      75414321                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     74273750                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38951887                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 68092338                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.664508                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.572045                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10417951                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1013386                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           354305                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    106111246                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.663072                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.565077                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     78913412     74.37%     74.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12236512     11.53%     85.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6105044      5.75%     91.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2654450      2.50%     94.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1291559      1.22%     95.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       838114      0.79%     96.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1777849      1.68%     97.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       428900      0.40%     98.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1865406      1.76%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    106111246                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            58013653                       # Number of instructions committed
system.cpu0.commit.committedOps              70359398                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23329921                       # Number of memory references committed
system.cpu0.commit.loads                     12763125                       # Number of loads committed
system.cpu0.commit.membars                     416120                       # Number of memory barriers committed
system.cpu0.commit.branches                  13382810                       # Number of branches committed
system.cpu0.commit.fp_insts                      5642                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61776783                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2631243                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        46969916     66.76%     66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55548      0.08%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4013      0.01%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12763125     18.14%     84.98% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10566796     15.02%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70359398                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1865406                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   172653686                       # The number of ROB reads
system.cpu0.rob.rob_writes                  163961445                       # The number of ROB writes
system.cpu0.timesIdled                         387576                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3253804                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2105668651                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   57936809                       # Number of Instructions Simulated
system.cpu0.committedOps                     70282554                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.929215                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.929215                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.518346                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.518346                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                82848883                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47347730                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16917                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13431                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                268451571                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27744432                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              149385288                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                777097                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           854224                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.968814                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42339027                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           854736                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.534625                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        186719500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   247.066049                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   264.902765                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.482551                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.517388                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189179253                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189179253                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12336272                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12826656                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25162928                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7919461                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      7984444                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15903905                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       182552                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180556                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       363108                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229758                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216608                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446366                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236004                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223300                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459304                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20255733                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20811100                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41066833                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20438285                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     20991656                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41429941                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       442915                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       396796                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       839711                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1873310                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1821129                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3694439                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117650                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        65870                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183520                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13470                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14295                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27765                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           38                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           41                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           79                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2316225                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2217925                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4534150                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2433875                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2283795                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4717670                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7322202500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7290660500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14612863000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133766411504                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 118455634259                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252222045763                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    214289000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    197755000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    412044000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      1125000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1641500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      2766500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 141088614004                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 125746294759                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 266834908763                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 141088614004                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 125746294759                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 266834908763                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12779187                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13223452                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26002639                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9792771                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9805573                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19598344                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       300202                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246426                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       546628                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243228                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230903                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474131                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236042                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223341                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459383                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22571958                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23029025                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45600983                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22872160                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23275451                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46147611                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034659                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030007                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032293                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191295                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185724                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188508                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.391903                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.267301                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335731                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055380                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061909                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058560                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000161                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000184                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000172                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102615                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096310                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099431                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106412                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098120                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102230                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16531.845839                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18373.825593                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17402.252680                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71406.447146                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 65045.163884                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68270.729538                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15908.611730                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13833.857992                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14840.410589                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 29605.263158                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 40036.585366                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35018.987342                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 60913.172945                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56695.467502                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58850.039977                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 57968.718198                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 55060.237350                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56560.740527                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1654202                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       345656                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            52729                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2989                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.371769                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   115.642690                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       704118                       # number of writebacks
system.cpu0.dcache.writebacks::total           704118                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       232529                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       180764                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       413293                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1722359                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1672656                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3395015                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9004                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9776                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18780                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954888                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1853420                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3808308                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954888                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1853420                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3808308                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210386                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216032                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426418                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       150951                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148473                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299424                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74802                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48133                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122935                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4466                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4519                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8985                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           38                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           41                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           79                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       361337                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       364505                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       725842                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       436139                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       412638                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       848777                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14870                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16259                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15297                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12291                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30167                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28550                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3362092000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3357394000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6719486000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10934577332                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10063021934                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  20997599266                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1126321500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    742845500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1869167000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     90886000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61004000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    151890000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1087000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1600500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2687500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14296669332                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13420415934                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  27717085266                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15422990832                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14163261434                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29586252266                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2991260000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3309772500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301032500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2610677924                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2474267452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084945376                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5601937924                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5784039952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385977876                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016463                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016337                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016399                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015415                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015142                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.249172                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.195324                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224897                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018361                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019571                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018950                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000161                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000184                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000172                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016008                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015828                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015917                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019069                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017728                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018393                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15980.588062                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15541.188342                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15757.979260                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72437.925764                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67776.780519                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70126.640703                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15057.371461                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15433.185133                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15204.514581                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20350.649351                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13499.446780                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16904.841402                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28605.263158                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 39036.585366                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34018.987342                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39566.026540                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36818.194357                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38186.113873                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35362.558340                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34323.696397                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34857.509412                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201160.726295                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203565.563688                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.797841                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170666.007975                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201307.253437                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184317.289256                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185697.547784                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202593.343327                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193912.799973                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1939563                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.473934                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38722182                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1940075                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            19.959116                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11152079500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   204.334938                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   307.138996                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.399092                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.599881                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998973                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          165                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42750946                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42750946                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19115401                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19606781                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38722182                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19115401                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19606781                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38722182                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19115401                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19606781                       # number of overall hits
system.cpu0.icache.overall_hits::total       38722182                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1011498                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1077049                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2088547                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1011498                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1077049                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2088547                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1011498                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1077049                       # number of overall misses
system.cpu0.icache.overall_misses::total      2088547                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14396633977                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15378251986                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  29774885963                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14396633977                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  15378251986                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  29774885963                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14396633977                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  15378251986                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  29774885963                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126899                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20683830                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40810729                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20126899                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20683830                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40810729                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20126899                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20683830                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40810729                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050256                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052072                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051176                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050256                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052072                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051176                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050256                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052072                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051176                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14232.983137                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14278.135894                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14256.268096                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14256.268096                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14256.268096                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        20294                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              818                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.809291                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1939563                       # number of writebacks
system.cpu0.icache.writebacks::total          1939563                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71879                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76450                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       148329                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71879                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76450                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       148329                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71879                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76450                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       148329                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       939619                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1000599                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1940218                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       939619                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1000599                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1940218                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       939619                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1000599                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1940218                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12628351483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13458642491                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  26086993974                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12628351483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13458642491                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  26086993974                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12628351483                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13458642491                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  26086993974                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86307500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     86307500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047542                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047542                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047542                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13445.393236                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129396.551724                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129396.551724                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27771206                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14500509                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           522402                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17226329                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                8535757                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            49.550644                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6833635                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             30645                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4632770                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           4521609                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          111161                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        32231                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    59668                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               59668                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19466                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14180                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        26022                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33646                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   657.210367                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  4292.478693                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        33233     98.77%     98.77% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          307      0.91%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           64      0.19%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           23      0.07%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33646                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        13510                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14754.441155                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12483.879781                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8047.547321                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         9092     67.30%     67.30% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767         4121     30.50%     97.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151          269      1.99%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535           27      0.20%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        13510                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  94672983040                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.774011                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.442469                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  94586502540     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     59948000      0.06%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     13676000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4818000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2374500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1378000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       809000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      2250500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       491500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       205500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21       133000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        51500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       144500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        33000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29        26000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31       141500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  94672983040                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3789     68.70%     68.70% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1726     31.30%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5515                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59668                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59668                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5515                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5515                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        65183                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14351950                       # DTB read hits
system.cpu1.dtb.read_misses                     51492                       # DTB read misses
system.cpu1.dtb.write_hits                   10462781                       # DTB write hits
system.cpu1.dtb.write_misses                     8176                       # DTB write misses
system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3688                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      817                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1295                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      676                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14403442                       # DTB read accesses
system.cpu1.dtb.write_accesses               10470957                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24814731                       # DTB hits
system.cpu1.dtb.misses                          59668                       # DTB misses
system.cpu1.dtb.accesses                     24874399                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     8103                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                8103                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2668                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4534                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          901                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7202                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1511.663427                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6714.706424                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         6781     94.15%     94.15% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          223      3.10%     97.25% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575           95      1.32%     98.57% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           31      0.43%     99.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           22      0.31%     99.31% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           21      0.29%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343            6      0.08%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535            5      0.07%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.07%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            4      0.06%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::90112-98303            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7202                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         3356                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13427.145411                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11321.856073                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7351.367505                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          969     28.87%     28.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1595     47.53%     76.40% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          704     20.98%     97.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           60      1.79%     99.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           15      0.45%     99.61% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151           10      0.30%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-106495            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         3356                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  30238902600                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.763443                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.425547                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     7158457500     23.67%     23.67% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    23076737600     76.31%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2728500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         531500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         338000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         109500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  30238902600                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1852     75.44%     75.44% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          603     24.56%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2455                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8103                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8103                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2455                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2455                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10558                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20686520                       # ITB inst hits
system.cpu1.itb.inst_misses                      8103                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2423                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1387                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20694623                       # ITB inst accesses
system.cpu1.itb.hits                         20686520                       # DTB hits
system.cpu1.itb.misses                           8103                       # DTB misses
system.cpu1.itb.accesses                     20694623                       # DTB accesses
system.cpu1.numCycles                       114249642                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          41315815                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     106868458                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27771206                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19891001                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     67522618                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3218365                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    120489                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7203                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              373                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       155077                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       135282                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          428                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20683839                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               366531                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   4147                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         110866430                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.159053                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.270352                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                81385669     73.41%     73.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3966024      3.58%     76.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2458990      2.22%     79.20% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8216379      7.41%     86.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1659206      1.50%     88.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1099479      0.99%     89.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1169763      1.06%     95.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4589422      4.14%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           110866430                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.243075                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.935394                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                28349810                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             63611088                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15737668                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1707179                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1460344                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1943796                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               150726                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              88547543                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               497407                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1460344                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                29270752                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                6941234                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46643920                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16512645                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             10037169                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              84769560                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 3293                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1700452                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                295960                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               7294084                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           88006736                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            389941348                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94160116                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6639                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             74402972                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13603764                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1570437                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1473591                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  9835455                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15202584                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11508546                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2153155                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2847808                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  81703406                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1095595                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78289936                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93469                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11173378                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24596663                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        114922                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    110866430                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.706164                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.396793                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           79351505     71.57%     71.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10562137      9.53%     81.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8130695      7.33%     88.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6659293      6.01%     94.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2446771      2.21%     96.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1483581      1.34%     97.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1548529      1.40%     99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             478985      0.43%     99.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             204934      0.18%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      110866430                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  95398      8.54%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     6      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                529553     47.39%     55.93% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               492367     44.07%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             2080      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52483936     67.04%     67.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59147      0.08%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4561      0.01%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.12% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14738514     18.83%     85.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11001690     14.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78289936                       # Type of FU issued
system.cpu1.iq.rate                          0.685253                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1117324                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014272                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268642821                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         94014634                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     76000311                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14274                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8222                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6128                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79397497                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7683                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          354386                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2162238                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2091                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51645                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1037860                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       208157                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        79710                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1460344                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5576526                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1063680                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           82916416                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           111836                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15202584                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11508546                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            564987                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44159                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1006496                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51645                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        224871                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       227319                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              452190                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77723399                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14509905                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           506997                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       117415                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25415143                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14757344                       # Number of branches executed
system.cpu1.iew.exec_stores                  10905238                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.680294                       # Inst execution rate
system.cpu1.iew.wb_sent                      77189704                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     76006439                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39824876                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69384097                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.665266                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.573977                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       11134037                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         980673                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           373526                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    108332250                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.661887                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.544752                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     80307491     74.13%     74.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12497635     11.54%     85.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6520784      6.02%     91.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2657688      2.45%     94.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1393058      1.29%     95.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       929919      0.86%     96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1912801      1.77%     98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       410208      0.38%     98.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1702666      1.57%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    108332250                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            59059498                       # Number of instructions committed
system.cpu1.commit.committedOps              71703684                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23511032                       # Number of memory references committed
system.cpu1.commit.loads                     13040346                       # Number of loads committed
system.cpu1.commit.membars                     397932                       # Number of memory barriers committed
system.cpu1.commit.branches                  13998335                       # Number of branches committed
system.cpu1.commit.fp_insts                      5786                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62664719                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2706612                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        48130630     67.12%     67.12% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57462      0.08%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4560      0.01%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13040346     18.19%     85.40% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10470686     14.60%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71703684                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1702666                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   176703276                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168209083                       # The number of ROB writes
system.cpu1.timesIdled                         415823                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        3383212                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3313474839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   58981437                       # Number of Instructions Simulated
system.cpu1.committedOps                     71625623                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.937044                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.937044                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.516251                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.516251                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84346535                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48387599                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    17183                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13302                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                274779775                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29204766                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              152559581                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                742832                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49488500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               334000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                87000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               605000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6450500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38437500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187145990                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36423                       # number of replacements
system.iocache.tags.tagsinuse                1.065406                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         236452882000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.065406                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.066588                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.066588                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
system.iocache.tags.data_accesses              328113                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          233                       # number of overall misses
system.iocache.overall_misses::total              233                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28955877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28955877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4552500113                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4552500113                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28955877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28955877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28955877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28955877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124274.150215                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124274.150215                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125676.350293                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125676.350293                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124274.150215                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124274.150215                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124274.150215                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124274.150215                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17305877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17305877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2739873610                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2739873610                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17305877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17305877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17305877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17305877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74274.150215                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74274.150215                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75636.970241                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75636.970241                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74274.150215                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74274.150215                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74274.150215                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74274.150215                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104290                       # number of replacements
system.l2c.tags.tagsinuse                65099.515899                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5149580                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169486                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.383513                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              74585715500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48909.873990                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    35.822123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000314                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5194.098796                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3030.838811                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    60.011828                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5395.002066                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2473.867973                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.746305                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000547                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.079256                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.046247                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000916                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.082321                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.037748                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993340                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           97                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65099                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           97                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3206                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8948                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52577                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001480                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.993332                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45521334                       # Number of tag accesses
system.l2c.tags.data_accesses                45521334                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        34415                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6607                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        37770                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7570                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  86362                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       704118                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          704118                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1900937                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1900937                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              67                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              75                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 142                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            25                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                54                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            75969                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            80733                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156702                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        929462                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        989553                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1919015                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       281279                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       261671                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           542950                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         34415                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6607                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              929462                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              357248                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         37770                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7570                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              989553                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              342404                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2705029                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        34415                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6607                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             929462                       # number of overall hits
system.l2c.overall_hits::cpu0.data             357248                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        37770                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7570                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             989553                       # number of overall hits
system.l2c.overall_hits::cpu1.data             342404                       # number of overall hits
system.l2c.overall_hits::total                2705029                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           55                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           77                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  133                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1510                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1357                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2867                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            9                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           16                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              25                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73422                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          66319                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139741                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         9984                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10819                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20803                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8358                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         7002                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15360                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           55                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9984                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             81780                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           77                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10819                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             73321                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176037                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           55                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9984                       # number of overall misses
system.l2c.overall_misses::cpu0.data            81780                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           77                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10819                       # number of overall misses
system.l2c.overall_misses::cpu1.data            73321                       # number of overall misses
system.l2c.overall_misses::total               176037                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      7850500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     10507500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       18490500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1247000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1719000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2966000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       233500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       783500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1017000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9778386500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8872285500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18650672000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1336981500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1437025999                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2774007499                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1139632000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    964751000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2104383000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      7850500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1336981500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  10918018500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     10507500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1437025999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9837036500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23547552999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      7850500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1336981500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  10918018500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     10507500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1437025999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9837036500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23547552999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        34470                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6608                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        37847                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7570                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              86495                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       704118                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       704118                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1900937                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1900937                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1577                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1432                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3009                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           38                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           41                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            79                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       149391                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       147052                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296443                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       939446                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1000372                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1939818                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       289637                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       268673                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       558310                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        34470                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6608                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          939446                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          439028                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        37847                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7570                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1000372                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          415725                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2881066                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        34470                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6608                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         939446                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         439028                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        37847                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7570                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1000372                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         415725                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2881066                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001596                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000151                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002035                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001538                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.957514                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.947626                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.952808                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.236842                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.390244                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.316456                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.491475                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.450990                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.471392                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010628                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010815                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010724                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028857                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.026061                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027512                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001596                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000151                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010628                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.186275                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.002035                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010815                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.176369                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061101                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001596                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000151                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010628                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.186275                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.002035                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010815                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.176369                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061101                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 142736.363636                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136461.038961                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 139026.315789                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   825.827815                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1266.764923                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1034.530869                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 25944.444444                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 48968.750000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        40680                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133180.606630                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133781.955397                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 133465.997810                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133912.409856                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132824.290507                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133346.512474                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136352.237377                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 137782.205084                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 137004.101562                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142736.363636                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133912.409856                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133504.750550                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136461.038961                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132824.290507                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134163.970759                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 133764.793759                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142736.363636                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133912.409856                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133504.750550                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136461.038961                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132824.290507                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134163.970759                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 133764.793759                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95762                       # number of writebacks
system.l2c.writebacks::total                    95762                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           65                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           78                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          143                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             65                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             78                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                154                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            65                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            78                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               154                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           55                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           77                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             133                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1510                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1357                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2867                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            9                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           16                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           25                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73422                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        66319                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139741                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         9978                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10814                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20792                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8293                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6924                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15217                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           55                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         9978                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        81715                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           77                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10814                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        73243                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           175883                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           55                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         9978                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        81715                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           77                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10814                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        73243                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          175883                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14870                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16259                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31796                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15297                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12291                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30167                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        28550                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59384                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7300500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9737500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17160500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    102740000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     92269000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    195009000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       612500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1094500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1707000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9044166500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8209095500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  17253262000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1236832005                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1328284001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2565116006                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1048516500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    886053008                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1934569508                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      7300500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1236832005                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  10092683000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      9737500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1328284001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   9095148508                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21770108014                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      7300500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1236832005                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  10092683000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      9737500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1328284001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   9095148508                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21770108014                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     75824497                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2805333500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3106482000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5987639997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2432647000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2332845000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4765492000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     75824497                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5237980500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5439327000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10753131997                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001538                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.957514                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.947626                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.952808                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.236842                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.390244                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.316456                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.491475                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.450990                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.471392                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010719                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028632                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025771                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027255                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.186127                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.176181                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061048                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.186127                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.176181                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061048                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 129026.315789                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68039.735099                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67994.841562                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68018.486223                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68055.555556                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68406.250000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68280                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123180.606630                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123781.955397                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123465.997810                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123370.335033                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126433.920174                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127968.372039                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127132.122495                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123510.775255                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123776.078495                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123510.775255                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123776.078495                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188657.262946                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191062.303955                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188314.253271                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159027.717853                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189801.073957                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172737.857039                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173632.794113                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190519.334501                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 181077.933400                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               31796                       # Transaction distribution
system.membus.trans_dist::ReadResp              68170                       # Transaction distribution
system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131952                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8761                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4667                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             25                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137941                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137941                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36375                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468049                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       575633                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 648528                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17313692                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17477749                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19794869                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              502                       # Total snoops (count)
system.membus.snoop_fanout::samples            415341                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  415341    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              415341                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95676000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1708000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           923138375                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1006417999                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1266123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5630525                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2835578                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        46774                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            561                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          561                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             149785                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2648524                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       836080                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1939563                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          158867                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            3009                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            79                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           3088                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296443                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296443                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1940218                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       558543                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5820932                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2687552                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37507                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166977                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8712968                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    248323008                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99964405                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       289268                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              348633393                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          209286                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3152616                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027333                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.163051                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                3066446     97.27%     97.27% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  86170      2.73%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3152616                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5542088496                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           378877                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2913039562                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1329029128                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          23370914                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          95118571                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------