path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.804323                       # Number of seconds simulated
sim_ticks                                2804323403500                       # Number of ticks simulated
final_tick                               2804323403500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 105186                       # Simulator instruction rate (inst/s)
host_op_rate                                   127668                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2521360773                       # Simulator tick rate (ticks/s)
host_mem_usage                                 559780                       # Number of bytes of host memory used
host_seconds                                  1112.23                       # Real time elapsed on the host
sim_insts                                   116990114                       # Number of instructions simulated
sim_ops                                     141995948                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         4352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           690752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4989088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           687552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4838852                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11215652                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       690752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       687552                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1378304                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8426048                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8443572                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           68                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10793                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             78473                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           63                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10743                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             75608                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175764                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131657                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136038                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1552                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              246317                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1779070                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              245176                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1725497                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3999415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         246317                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         245176                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             491493                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3004663                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3010912                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3004663                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1552                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             246317                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1785316                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             245176                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1725500                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7010327                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175765                       # Number of read requests accepted
system.physmem.writeReqs                       172232                       # Number of write requests accepted
system.physmem.readBursts                      175765                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     172232                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11239872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9088                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9513088                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11215716                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10759988                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      142                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23563                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4633                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11568                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11615                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11475                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10984                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11566                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11265                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12051                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11828                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10136                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10546                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10466                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9460                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10169                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11261                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10850                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10383                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9594                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9874                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9855                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9284                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9607                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9407                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10082                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9751                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8758                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9037                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8724                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8208                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8857                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9711                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9203                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8690                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
system.physmem.totGap                    2804323239500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  175210                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 167851                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61692                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8548                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1701                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3817                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1064                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      112                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65975                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      314.556969                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.654540                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.497717                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24476     37.10%     37.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15740     23.86%     60.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6623     10.04%     71.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3719      5.64%     76.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2901      4.40%     81.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1575      2.39%     83.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1142      1.73%     85.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1107      1.68%     86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8692     13.17%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65975                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6306                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.843324                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      438.660877                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6303     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6306                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6306                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.571519                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.321112                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       39.451011                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15               32      0.51%      0.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            5917     93.83%     94.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              88      1.40%     95.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              21      0.33%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              16      0.25%     96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              33      0.52%     96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             35      0.56%     97.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            27      0.43%     97.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            13      0.21%     98.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            17      0.27%     98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             5      0.08%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            20      0.32%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            18      0.29%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223             8      0.13%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             5      0.08%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.03%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             2      0.03%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             9      0.14%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             4      0.06%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             6      0.10%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             4      0.06%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            11      0.17%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             4      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             6      0.10%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-623             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6306                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2686689750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5979621000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    878115000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15298.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34048.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.01                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.39                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.00                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.84                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     145297                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    112992                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.73                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.00                       # Row buffer hit rate for writes
system.physmem.avgGap                      8058469.58                       # Average gap between requests
system.physmem.pageHitRate                      79.65                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  264138840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  144123375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 720337800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                501901920                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           183164495280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            78122450385                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1614063177750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1876980625350                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.317704                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2685041541216                       # Time in different power states
system.physmem_0.memoryStateTime::REF     93642380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     25639471784                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  234632160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  128023500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 649513800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                461298240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           183164495280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            76868306460                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1615163304000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1876669573440                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.206785                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2686874826210                       # Time in different power states
system.physmem_1.memoryStateTime::REF     93642380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     23802212540                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           10                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             10                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          228                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              228                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          228                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          228                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          228                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             228                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26894348                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13975310                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           545296                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            16832825                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12628735                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            75.024454                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6673545                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             29900                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    59638                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               59638                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19278                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14808                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        25552                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        34086                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   541.028575                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3545.315816                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        33770     99.07%     99.07% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          252      0.74%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           35      0.10%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           20      0.06%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-147455            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        34086                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        11896                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11442.270763                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9167.474880                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7450.500727                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-8191         3982     33.47%     33.47% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5461     45.91%     79.38% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2160     18.16%     97.54% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::24576-32767          140      1.18%     98.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-40959           47      0.40%     99.11% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::40960-49151           93      0.78%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-57343            3      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::57344-65535            3      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-73727            4      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-90111            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::90112-98303            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::106496-114687            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        11896                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  76466975540                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.696036                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.478552                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3  76445440540     99.97%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7     15483000      0.02%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11      3531500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15      1916000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19       394500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23       120500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27        34000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31        54000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  76466975540                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3544     69.19%     69.19% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1578     30.81%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5122                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        59638                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        59638                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5122                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5122                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        64760                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13978309                       # DTB read hits
system.cpu0.dtb.read_misses                     51149                       # DTB read misses
system.cpu0.dtb.write_hits                   10338750                       # DTB write hits
system.cpu0.dtb.write_misses                     8489                       # DTB write misses
system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3463                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      922                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1428                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      586                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14029458                       # DTB read accesses
system.cpu0.dtb.write_accesses               10347239                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24317059                       # DTB hits
system.cpu0.dtb.misses                          59638                       # DTB misses
system.cpu0.dtb.accesses                     24376697                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     8503                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                8503                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3306                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5069                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          128                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         8375                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1173.014925                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  5467.905811                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         7973     95.20%     95.20% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          197      2.35%     97.55% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          109      1.30%     98.85% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           49      0.59%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           12      0.14%     99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           14      0.17%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            5      0.06%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            7      0.08%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            2      0.02%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            4      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::90112-98303            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         8375                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2444                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12500.308511                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9992.698413                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7939.202624                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          801     32.77%     32.77% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383          949     38.83%     71.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          632     25.86%     97.46% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           25      1.02%     98.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           24      0.98%     99.47% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            9      0.37%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            2      0.08%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-73727            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2444                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  29185295284                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.914937                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.279656                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     2486739500      8.52%      8.52% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    26695454284     91.47%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2358500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         523000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         145500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          74500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  29185295284                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1760     75.99%     75.99% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          556     24.01%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2316                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8503                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8503                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2316                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2316                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total        10819                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20234859                       # ITB inst hits
system.cpu0.itb.inst_misses                      8503                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2268                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1416                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20243362                       # ITB inst accesses
system.cpu0.itb.hits                         20234859                       # DTB hits
system.cpu0.itb.misses                           8503                       # DTB misses
system.cpu0.itb.accesses                     20243362                       # DTB accesses
system.cpu0.numCycles                       106376136                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39965142                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     103919162                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26894348                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19302280                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     61475471                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3204102                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    133084                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                4359                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              386                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       482542                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       142714                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          389                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20233629                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               371892                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3629                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         103806101                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.204244                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.303663                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                75119256     72.36%     72.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3853264      3.71%     76.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2394905      2.31%     78.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8055629      7.76%     86.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1633408      1.57%     87.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1025690      0.99%     88.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6108914      5.88%     94.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1037923      1.00%     95.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4577112      4.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           103806101                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.252823                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.976903                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                27584011                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             57734540                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15584006                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1449686                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1453608                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1869283                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               150514                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              86108463                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               484067                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1453608                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                28423517                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6508141                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      43695790                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16185317                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7539460                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              82326363                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 3052                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1072870                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                278724                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               5472953                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84763927                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            379438570                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        91864230                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6406                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             71037693                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                13726234                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1533064                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1439152                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8446360                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14835811                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11457004                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1997727                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2772041                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  79153572                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1058697                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 75784801                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            96696                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       11308863                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     24599963                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        115562                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    103806101                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.730061                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.422275                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           73542195     70.85%     70.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10050115      9.68%     80.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7748986      7.46%     87.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6432670      6.20%     94.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2352911      2.27%     96.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1476701      1.42%     97.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1498599      1.44%     99.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             479431      0.46%     99.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             224493      0.22%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      103806101                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  98458      8.93%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                516893     46.87%     55.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               487368     44.20%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2186      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             50425393     66.54%     66.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57237      0.08%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4320      0.01%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14387296     18.98%     85.61% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10908366     14.39%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              75784801                       # Type of FU issued
system.cpu0.iq.rate                          0.712423                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1102720                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014551                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         256560915                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         91566516                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     73457837                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              14204                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              7630                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6340                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              76877738                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7597                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          359549                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2204717                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2719                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54058                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1152347                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       205467                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        94593                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1453608                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5664191                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               635354                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80356167                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           128884                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14835811                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11457004                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            551529                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 43992                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               579512                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54058                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        250397                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       220538                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              470935                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             75169409                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14142783                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           555867                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       143898                       # number of nop insts executed
system.cpu0.iew.exec_refs                    24942986                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14187310                       # Number of branches executed
system.cpu0.iew.exec_stores                  10800203                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.706638                       # Inst execution rate
system.cpu0.iew.wb_sent                      74627910                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     73464177                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38231116                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 66477839                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.690608                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.575096                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       11279021                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         943135                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           396816                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    101272480                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.681216                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.570732                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     74367990     73.43%     73.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12119249     11.97%     85.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6128079      6.05%     91.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2581969      2.55%     94.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1298466      1.28%     95.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       821679      0.81%     96.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1839446      1.82%     97.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       396658      0.39%     98.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1718944      1.70%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    101272480                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            56718354                       # Number of instructions committed
system.cpu0.commit.committedOps              68988407                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      22935751                       # Number of memory references committed
system.cpu0.commit.loads                     12631094                       # Number of loads committed
system.cpu0.commit.membars                     378784                       # Number of memory barriers committed
system.cpu0.commit.branches                  13402892                       # Number of branches committed
system.cpu0.commit.fp_insts                      6286                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 60396974                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2623511                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        45992810     66.67%     66.67% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55529      0.08%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4317      0.01%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12631094     18.31%     85.06% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10304657     14.94%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         68988407                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1718944                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   167372763                       # The number of ROB reads
system.cpu0.rob.rob_writes                  163072923                       # The number of ROB writes
system.cpu0.timesIdled                         393865                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2570035                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2956119679                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   56633353                       # Number of Instructions Simulated
system.cpu0.committedOps                     68903406                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.878330                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.878330                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.532388                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.532388                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                81817364                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46775146                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16878                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13235                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                265909763                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27649979                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              189136920                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                724107                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           853909                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.982202                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42514992                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           854421                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.758833                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        105520250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.898512                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.083689                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.361130                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.638835                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189859724                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189859724                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12422539                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12908546                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25331085                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7676552                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8235772                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15912324                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178433                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183837                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       362270                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209755                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237006                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446761                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216045                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243370                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459415                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20099091                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21144318                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41243409                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20277524                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21328155                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41605679                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       408353                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       423480                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       831833                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1950457                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1746190                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3696647                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        84124                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        98955                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       183079                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13813                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14039                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27852                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           21                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           34                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           55                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2358810                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2169670                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4528480                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2442934                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2268625                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4711559                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6108609853                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6466487368                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12575097221                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85969014596                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  79541032692                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 165510047288                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    182474999                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    208223500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    390698499                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       466006                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       533501                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       999507                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  92077624449                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  86007520060                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 178085144509                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  92077624449                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  86007520060                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 178085144509                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12830892                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13332026                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26162918                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9627009                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9981962                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19608971                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       262557                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       282792                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       545349                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223568                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251045                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474613                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216066                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243404                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459470                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22457901                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23313988                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45771889                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22720458                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23596780                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46317238                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031826                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031764                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031794                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202603                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174935                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188518                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.320403                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.349921                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335710                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061784                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055922                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058684                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000097                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000120                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105033                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093063                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.098936                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107521                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096141                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.101724                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14959.140383                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15269.876660                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15117.333913                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44076.344465                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45551.190129                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44773.019249                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13210.381452                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14831.790014                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14027.664046                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22190.761905                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15691.205882                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18172.854545                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39035.625781                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39640.830200                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39325.589273                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37691.408957                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37911.739516                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37797.498558                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1124276                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       180492                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            53485                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2944                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.020398                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    61.308424                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       704443                       # number of writebacks
system.cpu0.dcache.writebacks::total           704443                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       195410                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       211050                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       406460                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1794100                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1602957                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3397057                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9538                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8888                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18426                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1989510                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1814007                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3803517                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1989510                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1814007                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3803517                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       212943                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212430                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       425373                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156357                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143233                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299590                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58111                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64761                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122872                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4275                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5151                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9426                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           21                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           34                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           55                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       369300                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       355663                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       724963                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       427411                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       420424                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       847835                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2911652660                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2946522646                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5858175306                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7110951020                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6670158760                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13781109780                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    777722500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    894500250                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1672222750                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     53569251                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82009500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    135578751                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       434494                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       482499                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       916993                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10022603680                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9616681406                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  19639285086                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10800326180                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10511181656                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  21311507836                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3107181500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2733312000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5840493500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2374455377                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2136736500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4511191877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5481636877                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4870048500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10351685377                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016596                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015934                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016259                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016241                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014349                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.221327                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.229006                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225309                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019122                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020518                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019860                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000097                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000120                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016444                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015255                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015839                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018812                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017817                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018305                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13673.389874                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13870.558047                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13771.855068                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45478.942548                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46568.589361                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45999.899129                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13383.395571                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13812.329180                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13609.469611                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12530.818947                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15921.083285                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14383.487269                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20690.190476                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14191.147059                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16672.600000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27139.462984                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27038.745683                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1944350                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.567211                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           39122099                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1944862                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.115617                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9678062250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   228.929190                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   282.638021                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.447127                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.552027                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999155                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         43155983                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        43155983                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19191895                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19930204                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       39122099                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19191895                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19930204                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        39122099                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19191895                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19930204                       # number of overall hits
system.cpu0.icache.overall_hits::total       39122099                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1041065                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1047869                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2088934                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1041065                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1047869                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2088934                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1041065                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1047869                       # number of overall misses
system.cpu0.icache.overall_misses::total      2088934                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14016266373                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14162864905                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28179131278                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14016266373                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14162864905                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28179131278                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14016266373                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14162864905                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28179131278                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20232960                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20978073                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     41211033                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20232960                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20978073                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     41211033                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20232960                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20978073                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     41211033                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051454                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.049951                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050689                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051454                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.049951                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050689                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051454                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.049951                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050689                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.873554                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.718334                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.873554                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13489.718334                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.873554                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13489.718334                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        10636                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              597                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.815745                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71345                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        72638                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       143983                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71345                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        72638                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       143983                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71345                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        72638                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       143983                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       969720                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       975231                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1944951                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       969720                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       975231                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1944951                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       969720                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       975231                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1944951                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11896534814                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12012710558                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  23909245372                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11896534814                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12012710558                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  23909245372                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11896534814                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12012710558                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  23909245372                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     52863250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     52863250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     52863250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     52863250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047195                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047195                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047928                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046488                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047195                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.980837                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27831531                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14488346                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           557776                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17618092                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               13095982                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            74.332578                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6872630                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             30030                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    58148                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58148                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20423                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13441                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        24284                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        33864                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   507.057642                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3287.460249                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        33558     99.10%     99.10% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          245      0.72%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           40      0.12%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        33864                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        11833                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12004.944308                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9742.881321                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7470.572043                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         3519     29.74%     29.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5647     47.72%     77.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2322     19.62%     97.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          174      1.47%     98.55% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           60      0.51%     99.06% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151          104      0.88%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            3      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        11833                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  89903617428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.686126                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.480378                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  89833985928     99.92%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     50516000      0.06%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5      9974500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      3130500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      1885500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1212500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       715000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      1356000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       345000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       227000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21        44000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        32500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25        52500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        22500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29        23000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31        95000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  89903617428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3585     68.60%     68.60% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1641     31.40%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5226                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58148                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58148                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5226                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5226                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        63374                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14522718                       # DTB read hits
system.cpu1.dtb.read_misses                     49745                       # DTB read misses
system.cpu1.dtb.write_hits                   10695995                       # DTB write hits
system.cpu1.dtb.write_misses                     8403                       # DTB write misses
system.cpu1.dtb.flush_tlb                         177                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3436                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      922                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1213                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      578                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14572463                       # DTB read accesses
system.cpu1.dtb.write_accesses               10704398                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25218713                       # DTB hits
system.cpu1.dtb.misses                          58148                       # DTB misses
system.cpu1.dtb.accesses                     25276861                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     7828                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7828                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2631                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         5055                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          142                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7686                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1468.839448                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6467.961047                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         7241     94.21%     94.21% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          210      2.73%     96.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575          113      1.47%     98.41% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           52      0.68%     99.09% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           17      0.22%     99.31% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           18      0.23%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343            9      0.12%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535           10      0.13%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            7      0.09%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            6      0.08%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7686                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2491                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12581.694099                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10170.903635                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7854.515527                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          763     30.63%     30.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1045     41.95%     72.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          622     24.97%     97.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           29      1.16%     98.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           22      0.88%     99.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            6      0.24%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2491                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  25478819488                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.779989                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.414945                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     5610872428     22.02%     22.02% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    19864341560     77.96%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2357000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         850000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         398500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  25478819488                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1770     75.35%     75.35% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          579     24.65%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2349                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7828                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7828                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2349                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2349                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10177                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20979938                       # ITB inst hits
system.cpu1.itb.inst_misses                      7828                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         177                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2294                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1372                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20987766                       # ITB inst accesses
system.cpu1.itb.hits                         20979938                       # DTB hits
system.cpu1.itb.misses                           7828                       # DTB misses
system.cpu1.itb.accesses                     20987766                       # DTB accesses
system.cpu1.numCycles                       108755615                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40802320                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108613899                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27831531                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19968612                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     63156516                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3276855                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    120748                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                7463                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              413                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       335058                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       133595                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          290                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20978077                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               379105                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3473                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         106194794                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.229505                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.326126                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                76382369     71.93%     71.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3967856      3.74%     75.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2509209      2.36%     78.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8248224      7.77%     85.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1616537      1.52%     87.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1210559      1.14%     88.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6288171      5.92%     94.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1186864      1.12%     95.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4785005      4.51%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           106194794                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.255909                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.998697                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27865394                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             59086639                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 16014101                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1741536                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1486862                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             2014125                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               153633                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              90617334                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               499096                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1486862                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28829421                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                4993628                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46364709                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16784538                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              7735362                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              86665296                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 1758                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1681489                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                204965                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               5046479                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           89687558                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            399294691                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        96716693                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5355                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             75738735                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13948807                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1608168                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1506785                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10100252                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15391291                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11882778                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2188376                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2888870                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  83375619                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1158159                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 79910900                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            92494                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11441232                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     25615832                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        107265                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    106194794                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.752494                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.434563                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           74167078     69.84%     69.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10703730     10.08%     79.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8178605      7.70%     87.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6800959      6.40%     94.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2513016      2.37%     96.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1570037      1.48%     97.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1528184      1.44%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             489750      0.46%     99.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             243435      0.23%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      106194794                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 110018      9.66%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                521312     45.77%     55.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               507746     44.58%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              151      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             53586361     67.06%     67.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59349      0.07%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              2      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4262      0.01%     67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14931901     18.69%     85.82% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11328871     14.18%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              79910900                       # Type of FU issued
system.cpu1.iq.rate                          0.734775                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1139082                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014254                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         267236211                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         96019084                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     77543645                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11959                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6290                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5191                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              81043378                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6453                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          351971                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2202451                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2360                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        51509                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1138977                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       192559                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       108870                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1486862                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4086013                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               663456                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           84657415                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           129656                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15391291                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11882778                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            585252                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 42277                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               608480                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         51509                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        260306                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       223242                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              483548                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             79294807                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14687603                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           558095                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       123637                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25906138                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14775343                       # Number of branches executed
system.cpu1.iew.exec_stores                  11218535                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.729110                       # Inst execution rate
system.cpu1.iew.wb_sent                      78721985                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     77548836                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 40818570                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 71550295                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.713056                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.570488                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       11482053                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1050894                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           406174                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    103612513                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.706116                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.593552                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     75208985     72.59%     72.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12628786     12.19%     84.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6551089      6.32%     91.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2721278      2.63%     93.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1429301      1.38%     95.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       940289      0.91%     96.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1888025      1.82%     97.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       437231      0.42%     98.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1807529      1.74%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    103612513                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            60426665                       # Number of instructions committed
system.cpu1.commit.committedOps              73162446                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23932641                       # Number of memory references committed
system.cpu1.commit.loads                     13188840                       # Number of loads committed
system.cpu1.commit.membars                     435550                       # Number of memory barriers committed
system.cpu1.commit.branches                  14000562                       # Number of branches committed
system.cpu1.commit.fp_insts                      5142                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 64124542                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2721670                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        49168040     67.20%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57503      0.08%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4262      0.01%     67.29% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.29% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.29% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.29% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13188840     18.03%     85.32% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10743801     14.68%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         73162446                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1807529                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   173729023                       # The number of ROB reads
system.cpu1.rob.rob_writes                  171875858                       # The number of ROB writes
system.cpu1.timesIdled                         390006                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2560821                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2437360736                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   60356761                       # Number of Instructions Simulated
system.cpu1.committedOps                     73092542                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.801880                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.801880                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.554976                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.554976                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                86251315                       # number of integer regfile reads
system.cpu1.int_regfile_writes               49415173                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    15994                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13022                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                279979129                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29562027                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              195055078                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                795609                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198975032                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36852019                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36409                       # number of replacements
system.iocache.tags.tagsinuse                0.981278                       # Cycle average of tags in use
system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234149213000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.981278                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.061330                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.061330                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
system.iocache.tags.data_accesses              328227                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide           29                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total           29                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36195                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36195                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          249                       # number of overall misses
system.iocache.overall_misses::total              249                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30962377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30962377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6648903636                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6648903636                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     30962377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     30962377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     30962377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     30962377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.999199                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124346.895582                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124346.895582                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183696.743639                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183696.743639                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124346.895582                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124346.895582                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124346.895582                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124346.895582                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22802                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3472                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.567396                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36160                       # number of writebacks
system.iocache.writebacks::total                36160                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36195                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36195                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17850377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17850377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4766725674                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4766725674                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17850377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17850377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17850377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17850377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 71688.261044                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 71688.261044                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131695.694820                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131695.694820                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 71688.261044                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 71688.261044                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 71688.261044                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 71688.261044                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104656                       # number of replacements
system.l2c.tags.tagsinuse                65129.158587                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3113742                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169901                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    18.326802                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48669.329761                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    43.033999                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000245                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4678.591805                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2387.812073                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    44.916630                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5867.753400                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3437.720673                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.742635                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000657                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.071390                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.036435                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000685                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.089535                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.052455                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993792                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           70                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65175                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           70                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          366                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3243                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9051                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52499                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001068                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994492                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 29235849                       # Number of tag accesses
system.l2c.tags.data_accesses                29235849                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        36383                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         8250                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             959469                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             268247                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36362                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7924                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             964356                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             274193                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2555184                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          704443                       # number of Writeback hits
system.l2c.Writeback_hits::total               704443                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              48                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              39                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  87                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            32                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                46                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            82853                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            73309                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156162                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         36383                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          8250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              959469                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              351100                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36362                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7924                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              964356                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              347502                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2711346                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        36383                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         8250                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             959469                       # number of overall hits
system.l2c.overall_hits::cpu0.data             351100                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36362                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7924                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             964356                       # number of overall hits
system.l2c.overall_hits::cpu1.data             347502                       # number of overall hits
system.l2c.overall_hits::total                2711346                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           68                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            10143                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             7063                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           63                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            10750                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             8134                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36222                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1453                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1281                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2734                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            7                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               9                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          72022                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          68619                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140641                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           68                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             10143                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             79085                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           63                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10750                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76753                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176863                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           68                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            10143                       # number of overall misses
system.l2c.overall_misses::cpu0.data            79085                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           63                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10750                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76753                       # number of overall misses
system.l2c.overall_misses::total               176863                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5921750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        68750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    835233999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    610760750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5497500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    894308500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    720028000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     3071819249                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       436986                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       406987                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       843973                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       141998                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       222998                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6026469540                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5704758320                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11731227860                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5921750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        68750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    835233999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6637230290                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5497500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    894308500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6424786320                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     14803047109                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5921750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        68750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    835233999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6637230290                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5497500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    894308500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6424786320                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    14803047109                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        36451                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         8251                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         969612                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         275310                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36425                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7924                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         975106                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         282327                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2591406                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       704443                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           704443                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1501                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1320                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2821                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           21                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           34                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            55                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       154875                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       141928                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296803                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        36451                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         8251                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          969612                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          430185                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7924                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          975106                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          424255                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2888209                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        36451                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         8251                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         969612                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         430185                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7924                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         975106                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         424255                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2888209                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001866                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000121                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.010461                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.025655                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001730                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.011024                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.028811                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.013978                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.968021                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.970455                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.969160                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.333333                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.058824                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.163636                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.465033                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.483478                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.473853                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001866                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000121                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010461                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.183840                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001730                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011024                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.180912                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061236                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001866                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000121                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010461                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.183840                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001730                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011024                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.180912                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061236                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87084.558824                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        68750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.488372                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 84805.346171                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   300.747419                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   317.710383                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   308.695318                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 20285.428571                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        40500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 24777.555556                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83675.398351                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83136.716070                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 83412.574285                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87084.558824                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        68750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83191.488372                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 83697.817571                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        68750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83191.488372                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 83697.817571                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95497                       # number of writebacks
system.l2c.writebacks::total                    95497                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            75                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            61                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               146                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             75                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             61                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                146                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            75                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            61                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               146                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           68                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        10139                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6988                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           63                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        10744                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         8073                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           36076                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1453                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1281                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2734                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            9                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        72022                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        68619                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140641                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           68                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        10139                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        79010                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           63                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10744                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76692                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176717                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           68                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        10139                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        79010                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           63                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10744                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76692                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176717                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5068250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        56250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    708062999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    518326750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4705500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    759667250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    614985750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2610872749                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25946451                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     22749281                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     48695732                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       173506                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        86501                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       260007                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5129956460                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4854039180                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9983995640                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5068250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        56250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    708062999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5648283210                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      4705500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    759667250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5469024930                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  12594868389                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5068250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        56250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    708062999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5648283210                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      4705500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    759667250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5469024930                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  12594868389                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     41164749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2875017500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2529278000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5445460249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2162093500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1988256000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4150349500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     41164749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5037111000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4517534000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   9595809749                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001866                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000121                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.010457                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.025382                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001730                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011018                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.028595                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.013921                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.968021                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.970455                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.969160                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.058824                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.163636                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.465033                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.483478                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.473853                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001866                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000121                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010457                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.183665                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001730                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011018                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.180769                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061186                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001866                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000121                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010457                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.183665                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001730                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011018                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.180769                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061186                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        56250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24786.571429                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 43250.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28889.666667                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71227.631279                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70738.996196                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70989.225333                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        56250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 71271.402236                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        56250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 71271.402236                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               68117                       # Transaction distribution
system.membus.trans_dist::ReadResp              68116                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::Writeback            131657                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36194                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36194                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              9                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4635                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138750                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138750                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465311                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       572879                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 681693                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17344024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17507929                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4631616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22139545                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              523                       # Total snoops (count)
system.membus.snoop_fanout::samples            347614                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  347614    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              347614                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95655500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               16812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1658000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1067095796                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1022748121                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37540981                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            2657013                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2656927                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           704443                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2822                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            55                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2876                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296803                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296803                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3891000                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2536659                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42360                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169075                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               6639094                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124504512                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99962073                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        64700                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       291504                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              224822789                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           70210                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3665576                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.009952                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.099262                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                3629096     99.00%     99.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  36480      1.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3665576                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2562503934                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           246000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2923288858                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1353662761                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          26203715                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          96601513                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3039                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------