path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.539697                       # Number of seconds simulated
sim_ticks                                2539696838000                       # Number of ticks simulated
final_tick                               2539696838000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  33216                       # Simulator instruction rate (inst/s)
host_op_rate                                    40018                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1398403355                       # Simulator tick rate (ticks/s)
host_mem_usage                                 411672                       # Number of bytes of host memory used
host_seconds                                  1816.14                       # Real time elapsed on the host
sim_insts                                    60325607                       # Number of instructions simulated
sim_ops                                      72677421                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           469568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          3933400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           314240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5155776                       # Number of bytes read from this memory
system.physmem.bytes_read::total            130985112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       469568                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       314240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          783808                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3774400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1328880                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1687192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6790472                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7337                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             61485                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4910                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             80559                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293132                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58975                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           332220                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           421798                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812993                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47687002                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              184891                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1548768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           252                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              123731                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2030075                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51575097                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         184891                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         123731                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             308623                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1486162                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             523244                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             664328                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2673733                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1486162                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47687002                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             184891                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2072011                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          252                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             123731                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2694403                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54248831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293132                       # Number of read requests accepted
system.physmem.writeReqs                       812993                       # Number of write requests accepted
system.physmem.readBursts                    15293132                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     812993                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                975241856                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   3518592                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6826496                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 130985112                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6790472                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    54978                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  706304                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4635                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              954958                       # Per bank write bursts
system.physmem.perBankRdBursts::1              950647                       # Per bank write bursts
system.physmem.perBankRdBursts::2              950811                       # Per bank write bursts
system.physmem.perBankRdBursts::3              950999                       # Per bank write bursts
system.physmem.perBankRdBursts::4              954856                       # Per bank write bursts
system.physmem.perBankRdBursts::5              951881                       # Per bank write bursts
system.physmem.perBankRdBursts::6              951736                       # Per bank write bursts
system.physmem.perBankRdBursts::7              951699                       # Per bank write bursts
system.physmem.perBankRdBursts::8              955454                       # Per bank write bursts
system.physmem.perBankRdBursts::9              951840                       # Per bank write bursts
system.physmem.perBankRdBursts::10             951452                       # Per bank write bursts
system.physmem.perBankRdBursts::11             951010                       # Per bank write bursts
system.physmem.perBankRdBursts::12             955349                       # Per bank write bursts
system.physmem.perBankRdBursts::13             951888                       # Per bank write bursts
system.physmem.perBankRdBursts::14             952124                       # Per bank write bursts
system.physmem.perBankRdBursts::15             951450                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6588                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6390                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6534                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6563                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6471                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6764                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6747                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6681                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6996                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6810                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6454                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6114                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7081                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6669                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6965                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6837                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2539695718000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      18                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138826                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154288                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  58975                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1062531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1005454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    961588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1062790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    969024                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1031345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2691523                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2602840                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3403260                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    108695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    99295                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    93778                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    90278                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    18929                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    18461                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18290                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5897                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5773                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1008721                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      973.577780                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     909.477346                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     200.561203                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22290      2.21%      2.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        20048      1.99%      4.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8821      0.87%      5.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2154      0.21%      5.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2027      0.20%      5.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1663      0.16%      5.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9185      0.91%      6.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          821      0.08%      6.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       941712     93.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1008721                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6071                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2509.988470                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    47472.970867                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535          6043     99.54%     99.54% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::65536-131071            3      0.05%     99.59% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-196607            8      0.13%     99.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143            5      0.08%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.84% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06            2      0.03%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.10%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6071                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6071                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.569428                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.390583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.344347                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1                   4      0.07%      0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   2      0.03%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   6      0.10%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   3      0.05%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   4      0.07%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6                   3      0.05%      0.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7                   1      0.02%      0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8                   3      0.05%      0.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9                   4      0.07%      0.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10                  3      0.05%      0.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::11                  3      0.05%      0.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13                  1      0.02%      0.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14                  3      0.05%      0.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                 10      0.16%      0.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2784     45.86%     46.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 49      0.81%     47.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1358     22.37%     69.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1417     23.34%     93.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                155      2.55%     95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 60      0.99%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 36      0.59%     97.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 21      0.35%     97.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 24      0.40%     98.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 17      0.28%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 23      0.38%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 14      0.23%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                 10      0.16%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 12      0.20%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                 16      0.26%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 11      0.18%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                 14      0.23%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6071                       # Writes before turning the bus around for reads
system.physmem.totQLat                   392019251500                       # Total ticks spent queuing
system.physmem.totMemAccLat              677734639000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76190770000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25726.16                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44476.16                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         384.00                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.69                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         5.74                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        14.90                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14244888                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91209                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  85.49                       # Row buffer hit rate for writes
system.physmem.avgGap                       157685.09                       # Average gap between requests
system.physmem.pageHitRate                      93.43                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2193828681000                       # Time in different power states
system.physmem.memoryStateTime::REF       84806020000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      261061225250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     55193080                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16345666                       # Transaction distribution
system.membus.trans_dist::ReadResp           16345666                       # Transaction distribution
system.membus.trans_dist::WriteReq             763357                       # Transaction distribution
system.membus.trans_dist::WriteResp            763357                       # Transaction distribution
system.membus.trans_dist::Writeback             58975                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4635                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4635                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131547                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131547                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383056                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3780                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1884913                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4271753                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34549385                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390478                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16665056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19063162                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           140173690                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              140173690                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487406000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3427500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17563315500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4754319520                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37450374673                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    64063                       # number of replacements
system.l2c.tags.tagsinuse                51393.584080                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1901876                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   129454                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    14.691520                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2528371598500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37072.406553                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     9.476763                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000251                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5409.710973                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3302.260075                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     6.209843                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2641.050651                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2952.468970                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.565680                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000145                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.082546                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.050388                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000095                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.040299                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.045051                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.784204                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65378                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          438                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3140                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5952                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55810                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997589                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18903981                       # Number of tag accesses
system.l2c.tags.data_accesses                18903981                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        27725                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7459                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             477090                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             174144                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        29829                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         8048                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             498641                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             211687                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1434623                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          606690                       # number of Writeback hits
system.l2c.Writeback_hits::total               606690                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              17                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  30                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            55364                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            57398                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112762                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         27725                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              477090                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              229508                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         29829                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          8048                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              498641                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              269085                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1547385                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        27725                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7459                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             477090                       # number of overall hits
system.l2c.overall_hits::cpu0.data             229508                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        29829                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         8048                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             498641                       # number of overall hits
system.l2c.overall_hits::cpu1.data             269085                       # number of overall hits
system.l2c.overall_hits::total                1547385                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7229                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6022                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4914                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4504                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22694                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1367                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1538                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2905                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          56297                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          76980                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133277                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7229                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             62319                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4914                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             81484                       # number of demand (read+write) misses
system.l2c.demand_misses::total                155971                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7229                       # number of overall misses
system.l2c.overall_misses::cpu0.data            62319                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4914                       # number of overall misses
system.l2c.overall_misses::cpu1.data            81484                       # number of overall misses
system.l2c.overall_misses::total               155971                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1336000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        82000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    518356500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    443449495                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       747000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    356901000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    338441743                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1659313738                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       162993                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       254989                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       417982                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4027199927                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5731646841                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9758846768                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1336000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        82000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    518356500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4470649422                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       747000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    356901000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6070088584                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11418160506                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1336000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        82000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    518356500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4470649422                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       747000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    356901000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6070088584                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11418160506                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        27739                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7460                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         484319                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         180166                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        29839                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         8048                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         503555                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         216191                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1457317                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       606690                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           606690                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1384                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1551                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2935                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111661                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       134378                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246039                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        27739                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7460                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          484319                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          291827                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        29839                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         8048                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          503555                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          350569                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1703356                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        27739                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7460                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         484319                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         291827                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        29839                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         8048                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         503555                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         350569                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1703356                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000505                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000134                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014926                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.033425                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000335                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009759                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.020833                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015572                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987717                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991618                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.989779                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.504178                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.572862                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541691                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000505                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000134                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014926                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.213548                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000335                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009759                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.232434                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.091567                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000505                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000134                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014926                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.213548                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000335                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009759                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.232434                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.091567                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95428.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71705.145940                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73638.242278                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74700                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72629.426129                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75142.482904                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73116.847537                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   119.234089                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   165.792588                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   143.883649                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71534.893991                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74456.311263                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73222.287176                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95428.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 71705.145940                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 71738.144418                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74700                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72629.426129                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74494.239164                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 73206.945560                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95428.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 71705.145940                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 71738.144418                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74700                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72629.426129                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74494.239164                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 73206.945560                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58975                       # number of writebacks
system.l2c.writebacks::total                    58975                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                68                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7222                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         5983                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4910                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4486                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22626                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1367                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1538                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2905                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        56297                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        76980                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133277                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7222                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        62280                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4910                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        81466                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           155903                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7222                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        62280                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4910                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        81466                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          155903                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1163500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        70000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    427109500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    366125745                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    294835000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    281582243                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1371510988                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13679367                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     15384538                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29063905                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3324764073                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4773094655                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8097858728                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1163500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    427109500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   3690889818                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    294835000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5054676898                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9469369716                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1163500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    427109500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   3690889818                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    294835000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5054676898                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9469369716                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6117750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83698669250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83244575500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   7714617000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   9329751845                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17044368845                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6117750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91413286250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  92574327345                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183993731345                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.033208                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020750                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015526                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987717                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991618                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.989779                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.504178                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.572862                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541691                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.213414                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.232382                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.091527                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000505                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000134                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014912                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.213414                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000335                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009751                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.232382                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.091527                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60738.855032                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60738.855032                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58696725                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2675214                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2675214                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763357                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763357                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           606690                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2935                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2937                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           246039                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          246039                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1976942                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5792286                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42218                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       136665                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7948111                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     63231360                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85355770                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       230312                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148879474                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148879474                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          192412                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4956067661                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4453658755                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4478828129                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          26774357                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          79740148                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48628247                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322168                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322168                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8176                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8176                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          520                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1028                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383056                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32660688                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1040                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390478                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123501006                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123501006                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               520000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               520000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374880000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         38124261327                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                7765284                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          5771603                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           325703                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4845901                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                3829041                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            79.016080                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 808445                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             22619                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    27181562                       # DTB read hits
system.cpu0.dtb.read_misses                     37782                       # DTB read misses
system.cpu0.dtb.write_hits                    5596065                       # DTB write hits
system.cpu0.dtb.write_misses                    10098                       # DTB write misses
system.cpu0.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                731                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5491                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      645                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   284                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      704                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                27219344                       # DTB read accesses
system.cpu0.dtb.write_accesses                5606163                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32777627                       # DTB hits
system.cpu0.dtb.misses                          47880                       # DTB misses
system.cpu0.dtb.accesses                     32825507                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     5349242                       # ITB inst hits
system.cpu0.itb.inst_misses                      7594                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                731                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2632                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     2439                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 5356836                       # ITB inst accesses
system.cpu0.itb.hits                          5349242                       # DTB hits
system.cpu0.itb.misses                           7594                       # DTB misses
system.cpu0.itb.accesses                      5356836                       # DTB accesses
system.cpu0.numCycles                       234138431                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          14733348                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      42294638                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7765284                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4637486                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    215157682                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                 899672                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    103093                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                 978                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             1882                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       100153                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1830103                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          127                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  5346345                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               204670                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3021                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         232377075                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.216391                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.156919                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               222728537     95.85%     95.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  885926      0.38%     96.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  959241      0.41%     96.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1030592      0.44%     97.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1233052      0.53%     97.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  718062      0.31%     97.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1129349      0.49%     98.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  448984      0.19%     98.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3243332      1.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           232377075                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.033165                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.180639                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12160999                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            212353937                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6177683                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1309281                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                372986                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              974074                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                78107                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              45045632                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               258698                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                372986                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                12774661                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               53419035                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      30524585                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6795741                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles            128487965                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              43632543                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1343                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents              95385189                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents             124519108                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               1934134                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           46283925                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            200651385                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        53129662                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             5272                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36330469                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 9953456                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            576590                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        492282                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  7436987                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7977179                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6240861                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1088795                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1688387                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  41277277                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1012498                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 59014531                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            58753                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        7256631                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     15830718                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        292140                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    232377075                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.253960                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       0.959343                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          212079469     91.27%     91.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            6238226      2.68%     93.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            2924438      1.26%     95.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2416467      1.04%     96.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6166815      2.65%     98.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1071194      0.46%     99.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             901941      0.39%     99.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             385048      0.17%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             193477      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      232377075                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 114630      2.27%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     3      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4666706     92.48%     94.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               264598      5.24%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            15012      0.03%      0.03% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             25515552     43.24%     43.26% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               47770      0.08%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           902      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            27508063     46.61%     89.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5927232     10.04%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              59014531                       # Type of FU issued
system.cpu0.iq.rate                          0.252050                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    5045937                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.085503                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         355498871                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         49563440                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     38260615                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11956                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6482                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5191                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              64039026                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6430                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          226085                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1459518                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2588                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        24632                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       672041                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17098280                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      3147229                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                372986                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               50915247                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1803662                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           42401043                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            79571                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7977179                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6240861                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            734817                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                139591                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1596321                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         24632                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        160350                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       132588                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              292938                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             58604130                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             27345857                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           362682                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       111268                       # number of nop insts executed
system.cpu0.iew.exec_refs                    33208867                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 5668977                       # Number of branches executed
system.cpu0.iew.exec_stores                   5863010                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.250297                       # Inst execution rate
system.cpu0.iew.wb_sent                      55434698                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     38265806                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 21645924                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 38521221                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.163432                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.561922                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        7110536                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         720358                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           248726                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    231246727                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.150700                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     0.849611                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    218753445     94.60%     94.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6297983      2.72%     97.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1708084      0.74%     98.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1059115      0.46%     98.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       644957      0.28%     98.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       581299      0.25%     99.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       449364      0.19%     99.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       245033      0.11%     99.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1507447      0.65%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    231246727                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            29059194                       # Number of instructions committed
system.cpu0.commit.committedOps              34848810                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      12086481                       # Number of memory references committed
system.cpu0.commit.loads                      6517661                       # Number of loads committed
system.cpu0.commit.membars                     192728                       # Number of memory barriers committed
system.cpu0.commit.branches                   4958536                       # Number of branches committed
system.cpu0.commit.fp_insts                      5174                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 30757342                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              472350                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        22717072     65.19%     65.19% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          44355      0.13%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     65.31% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc          902      0.00%     65.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     65.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.32% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        6517661     18.70%     84.02% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5568820     15.98%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         34848810                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1507447                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   270795640                       # The number of ROB reads
system.cpu0.rob.rob_writes                   85052492                       # The number of ROB writes
system.cpu0.timesIdled                         264396                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        1761356                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2270391996                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   28992496                       # Number of Instructions Simulated
system.cpu0.committedOps                     34782112                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              8.075829                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        8.075829                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.123826                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.123826                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                66468797                       # number of integer regfile reads
system.cpu0.int_regfile_writes               24185826                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    44758                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   41844                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                196782773                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                15711716                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              291428250                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                565781                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           988317                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.592753                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            9970376                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           988829                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.083013                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6654117250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   184.676713                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   326.916040                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.360697                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.638508                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999205                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          155                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         12025421                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        12025421                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      4823915                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5146461                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        9970376                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      4823915                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5146461                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         9970376                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      4823915                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5146461                       # number of overall hits
system.cpu0.icache.overall_hits::total        9970376                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       522311                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       543898                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1066209                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       522311                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       543898                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1066209                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       522311                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       543898                       # number of overall misses
system.cpu0.icache.overall_misses::total      1066209                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7237674573                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   7341681631                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14579356204                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7237674573                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   7341681631                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14579356204                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7237674573                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   7341681631                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14579356204                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      5346226                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5690359                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     11036585                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      5346226                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5690359                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     11036585                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      5346226                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5690359                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     11036585                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.097697                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.095582                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.096607                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.097697                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.095582                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.096607                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.097697                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.095582                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.096607                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13857.021148                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.269218                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.013448                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13857.021148                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.269218                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13674.013448                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13857.021148                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.269218                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13674.013448                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4158                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              274                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.175182                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        37549                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39824                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        77373                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        37549                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        39824                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        77373                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        37549                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        39824                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        77373                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       484762                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       504074                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       988836                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       484762                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       504074                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       988836                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       484762                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       504074                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       988836                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5888564763                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5971220456                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11859785219                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5888564763                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5971220456                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11859785219                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5888564763                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5971220456                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11859785219                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8523250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8523250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8523250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      8523250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.089596                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.089596                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090674                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.088584                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.089596                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           641884                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.993418                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19756750                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           642396                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.754784                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         42094250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   133.972457                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   378.020960                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.261665                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.738322                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         95317436                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        95317436                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5857300                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6196947                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       12054247                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3502178                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3641154                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7143332                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        35246                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        29793                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        65039                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       110182                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       133190                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       243372                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       112371                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       135291                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247662                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9359478                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      9838101                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19197579                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9394724                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      9867894                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19262618                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       295687                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       396301                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       691988                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1362259                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1719020                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3081279                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        73803                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        54706                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       128509                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6350                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6980                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13330                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1657946                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2115321                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3773267                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1731749                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2170027                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3901776                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4378228092                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5755162638                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  10133390730                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  57860586634                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  86029827577                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 143890414211                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92678240                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     94350988                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    187029228                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  62238814726                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  91784990215                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 154023804941                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  62238814726                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  91784990215                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 154023804941                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6152987                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      6593248                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12746235                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4864437                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5360174                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10224611                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       109049                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        84499                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       193548                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       116532                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       140170                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       256702                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       112373                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       135291                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247664                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11017424                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     11953422                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     22970846                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11126473                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     12037921                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     23164394                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048056                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060107                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.054290                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.280045                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.320702                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.301359                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.676787                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.647416                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.663964                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054491                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049797                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.051928                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000018                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.150484                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.176964                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.164263                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.155642                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.180266                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.168439                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14806.968490                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14522.200645                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14643.882163                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42473.998435                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50045.856114                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 46698.275038                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14594.998425                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13517.333524                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14030.699775                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37539.711623                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43390.572975                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 40819.747169                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35939.858909                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42296.704241                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 39475.306871                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       204060                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        43131                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            27157                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            778                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     7.514085                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    55.438303                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       606690                       # number of writebacks
system.cpu0.dcache.writebacks::total           606690                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       164206                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       218384                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       382590                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1249257                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1583126                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2832383                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          616                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          758                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1374                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1413463                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1801510                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3214973                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1413463                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1801510                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3214973                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       131481                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       177917                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       309398                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       113002                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       135894                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       248896                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        42994                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        32087                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        75081                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         5734                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         6222                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11956                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       244483                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       313811                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       558294                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       287477                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       345898                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       633375                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1725190273                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2222171472                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3947361745                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4787330436                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6538944348                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11326274784                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    807768256                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    644366504                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1452134760                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73471759                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72597010                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    146068769                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6512520709                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8761115820                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15273636529                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7320288965                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9405482324                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16725771289                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91407551750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90929310002                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  11972132389                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  14721058995                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26693191384                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.021369                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026985                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024274                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023230                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025353                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024343                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.394263                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.379732                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.387919                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.049205                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044389                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046575                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000018                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.022191                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026253                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024304                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025837                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028734                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.027343                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                8288231                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          6165176                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           342380                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             5156418                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                4057157                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            78.681693                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 881950                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             23449                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    28293531                       # DTB read hits
system.cpu1.dtb.read_misses                     40544                       # DTB read misses
system.cpu1.dtb.write_hits                    6190636                       # DTB write hits
system.cpu1.dtb.write_misses                    14491                       # DTB write misses
system.cpu1.dtb.flush_tlb                         506                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                708                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    5400                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      865                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   285                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      723                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                28334075                       # DTB read accesses
system.cpu1.dtb.write_accesses                6205127                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         34484167                       # DTB hits
system.cpu1.dtb.misses                          55035                       # DTB misses
system.cpu1.dtb.accesses                     34539202                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     5693555                       # ITB inst hits
system.cpu1.itb.inst_misses                      8207                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         506                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                708                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2675                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     2702                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 5701762                       # ITB inst accesses
system.cpu1.itb.hits                          5693555                       # DTB hits
system.cpu1.itb.misses                           8207                       # DTB misses
system.cpu1.itb.accesses                      5701762                       # DTB accesses
system.cpu1.numCycles                       237058963                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          15389347                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      44896719                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    8288231                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4939107                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    217242159                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 949095                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    106364                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                1987                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             1943                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        92979                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      2091650                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          112                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5690360                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               215494                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3361                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         235400962                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.228809                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.188674                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               225085908     95.62%     95.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  947634      0.40%     96.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1047135      0.44%     96.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1048515      0.45%     96.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1240998      0.53%     97.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  829745      0.35%     97.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1296822      0.55%     98.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  452969      0.19%     98.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 3451236      1.47%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           235400962                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.034963                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.189391                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                12590716                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            214453384                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  6500032                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1465156                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                389454                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1047596                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                86470                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              48240012                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               288766                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                389454                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                13272686                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               54002992                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      31282477                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  7201814                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles            129249426                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              46761611                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 1258                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents              95572539                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents             124561907                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               2450017                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           49620172                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            215588900                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        57377506                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             4944                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             39615169                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                10004995                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            609511                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        515718                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  8221045                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             8459299                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6818667                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1033426                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1557443                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  44314605                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1045489                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 62743783                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            61525                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        7205140                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     16025571                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        281591                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    235400962                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.266540                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.981476                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          213793871     90.82%     90.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            6637383      2.82%     93.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3199231      1.36%     95.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2579548      1.10%     96.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6422119      2.73%     98.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1152982      0.49%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1001630      0.43%     99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             407456      0.17%     99.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             206742      0.09%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      235400962                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 146491      2.81%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     1      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      2.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4788852     91.80%     94.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               281237      5.39%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            13506      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             27516436     43.86%     43.88% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46370      0.07%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1209      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            28654021     45.67%     89.62% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6512241     10.38%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              62743783                       # Type of FU issued
system.cpu1.iq.rate                          0.264676                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    5216581                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.083141                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         366155152                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         52582376                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     41291326                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11482                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6074                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5054                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              67940659                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6199                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          226253                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      1460814                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2639                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        24306                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       652998                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     17101900                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3881798                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                389454                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               50160792                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              3093797                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           45494090                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            85835                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              8459299                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6818667                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            741438                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                149727                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2862513                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         24306                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        166054                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       139765                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              305819                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             62318890                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             28486625                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           369994                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       133996                       # number of nop insts executed
system.cpu1.iew.exec_refs                    34929125                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 6064585                       # Number of branches executed
system.cpu1.iew.exec_stores                   6442500                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.262884                       # Inst execution rate
system.cpu1.iew.wb_sent                      58464614                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     41296380                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 23329556                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 41830645                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.174203                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.557714                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        7169441                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         763898                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           257160                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    234250313                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.162130                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     0.884909                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    220821840     94.27%     94.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6746509      2.88%     97.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1771690      0.76%     97.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1085849      0.46%     98.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       731494      0.31%     98.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       648369      0.28%     98.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       505518      0.22%     99.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       281725      0.12%     99.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1657319      0.71%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    234250313                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            31416794                       # Number of instructions committed
system.cpu1.commit.committedOps              37978992                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13164154                       # Number of memory references committed
system.cpu1.commit.loads                      6998485                       # Number of loads committed
system.cpu1.commit.membars                     211048                       # Number of memory barriers committed
system.cpu1.commit.branches                   5351716                       # Number of branches committed
system.cpu1.commit.fp_insts                      5038                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 33506635                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              519749                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        24770094     65.22%     65.22% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          43535      0.11%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         1209      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.34% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        6998485     18.43%     83.77% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       6165669     16.23%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         37978992                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1657319                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   276790751                       # The number of ROB reads
system.cpu1.rob.rob_writes                   91451122                       # The number of ROB writes
system.cpu1.timesIdled                         270857                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1658001                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2279071980                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   31333111                       # Number of Instructions Simulated
system.cpu1.committedOps                     37895309                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              7.565765                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        7.565765                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.132174                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.132174                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                71132794                       # number of integer regfile reads
system.cpu1.int_regfile_writes               26016814                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    44316                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   42056                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                209312794                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                17049814                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              299103919                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                609097                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1732377463327                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83365                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------