path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.823500                       # Number of seconds simulated
sim_ticks                                2823500156000                       # Number of ticks simulated
final_tick                               2823500156000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 104004                       # Simulator instruction rate (inst/s)
host_op_rate                                   126232                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2512003120                       # Simulator tick rate (ticks/s)
host_mem_usage                                 633188                       # Number of bytes of host memory used
host_seconds                                  1124.00                       # Real time elapsed on the host
sim_insts                                   116900784                       # Number of instructions simulated
sim_ops                                     141885276                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         3904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           658624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5296736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           714240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4509448                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11188968                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       658624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       714240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1372864                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8441728                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8459252                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           61                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10291                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             83280                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           78                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             11160                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             70462                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175348                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131902                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136283                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1383                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              233265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1875947                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              252963                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1597113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3962801                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         233265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         252963                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             486228                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2989810                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2996016                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2989810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1383                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             233265                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1882150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             252963                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1597116                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6958817                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175349                       # Number of read requests accepted
system.physmem.writeReqs                       136283                       # Number of write requests accepted
system.physmem.readBursts                      175349                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     136283                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11214592                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8471552                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11189032                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8459252                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          49584                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11393                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10987                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11434                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11274                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11014                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10539                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11403                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11330                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11251                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11289                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10499                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10072                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10665                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11522                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10554                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10002                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8625                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8280                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8885                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8791                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7852                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7876                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8450                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8527                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8486                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8687                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7873                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7718                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8233                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8873                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7886                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7326                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
system.physmem.totGap                    2823499978000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174793                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 131902                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    107531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1718                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     8094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8577                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8370                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65648                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      299.873263                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.206399                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.323909                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24801     37.78%     37.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16133     24.58%     62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6704     10.21%     72.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3735      5.69%     78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2850      4.34%     82.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1672      2.55%     85.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1116      1.70%     86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1095      1.67%     88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7542     11.49%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65648                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.286122                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      483.294559                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6663     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.860165                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.266089                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.031195                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 4      0.06%      0.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                5      0.08%      0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              10      0.15%      0.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5719     85.81%     86.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             154      2.31%     88.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              55      0.83%     89.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             202      3.03%     92.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              36      0.54%     93.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             143      2.15%     95.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              45      0.68%     95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.14%     95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              15      0.23%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              23      0.35%     96.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.09%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             162      2.43%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.08%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              18      0.27%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.26%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2742857501                       # Total ticks spent queuing
system.physmem.totMemAccLat                6028382501                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    876140000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15653.08                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34403.08                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.46                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        13.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144250                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97697                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.79                       # Row buffer hit rate for writes
system.physmem.avgGap                      9060366.00                       # Average gap between requests
system.physmem.pageHitRate                      78.65                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  255936240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  139647750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 697117200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                436013280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80003561535                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1623919600500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1889868955065                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.336286                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2701419954000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94282760000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27794238500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  240362640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  131150250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 669653400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                421731360                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79168489875                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1624652119500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1889700585585                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.276655                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2702647601500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94282760000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26569784000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          249                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             249                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26581187                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13736110                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           501433                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            16012084                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12431439                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            77.637858                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6636300                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             27516                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    56625                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               56625                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17270                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13837                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        25518                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        31107                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   865.432218                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  5323.916597                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383        30633     98.48%     98.48% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767          331      1.06%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151           76      0.24%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535           30      0.10%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919           18      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        31107                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        12481                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13577.197340                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10994.614021                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9335.319316                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         9132     73.17%     73.17% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3098     24.82%     97.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          222      1.78%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.06%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919            4      0.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455           14      0.11%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        12481                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  91900460244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.603534                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.511861                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  91817471744     99.91%     99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     56263000      0.06%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     12793000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      5164500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2519500      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1396500      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13      1020000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      2514500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       435000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       355500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21        97000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        44500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25       171000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        35500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        18000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31       161000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  91900460244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3454     69.05%     69.05% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1548     30.95%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5002                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56625                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56625                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5002                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5002                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        61627                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13967095                       # DTB read hits
system.cpu0.dtb.read_misses                     47255                       # DTB read misses
system.cpu0.dtb.write_hits                   10501947                       # DTB write hits
system.cpu0.dtb.write_misses                     9370                       # DTB write misses
system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3287                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1257                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      595                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14014350                       # DTB read accesses
system.cpu0.dtb.write_accesses               10511317                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24469042                       # DTB hits
system.cpu0.dtb.misses                          56625                       # DTB misses
system.cpu0.dtb.accesses                     24525667                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     7362                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7362                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2261                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4952                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          149                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         7213                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1612.505199                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  6472.144246                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6729     93.29%     93.29% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          210      2.91%     96.20% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          172      2.38%     98.59% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           48      0.67%     99.25% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           20      0.28%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           11      0.15%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.11%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            3      0.04%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::90112-98303            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         7213                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2374                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13966.512216                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11737.528521                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  8158.100835                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         1734     73.04%     73.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          597     25.15%     98.19% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           40      1.68%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2374                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  23180714008                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.929856                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.256422                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1630643500      7.03%      7.03% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    21546495508     92.95%     99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2812000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         517500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         174500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          71000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  23180714008                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1663     74.74%     74.74% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          562     25.26%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2225                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7362                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7362                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2225                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2225                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         9587                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20128372                       # ITB inst hits
system.cpu0.itb.inst_misses                      7362                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2149                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1237                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20135734                       # ITB inst accesses
system.cpu0.itb.hits                         20128372                       # DTB hits
system.cpu0.itb.misses                           7362                       # DTB misses
system.cpu0.itb.accesses                     20135734                       # DTB accesses
system.cpu0.numCycles                       111789846                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39393717                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     103942274                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26581187                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19067739                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     67197572                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3104883                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    120313                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                4808                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              429                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       187538                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       119721                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          669                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20127335                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               349524                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3480                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         108577171                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.150570                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.270138                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                80014629     73.69%     73.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3810733      3.51%     77.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2393612      2.20%     79.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 7999548      7.37%     86.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1536045      1.41%     88.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1088578      1.00%     89.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6047569      5.57%     94.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1035127      0.95%     95.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4651330      4.28%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           108577171                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.237778                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.929801                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26873328                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             63362554                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15407826                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1524257                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1408897                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1872466                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               145547                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              86353471                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               470061                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1408897                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27727925                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6705409                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      45853663                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16073761                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10807193                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              82639232                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 2272                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1128991                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                256935                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8662593                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84875469                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            381763695                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        92641306                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             5587                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72346979                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12528482                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1562352                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1465023                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8851459                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14739399                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11667463                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          2112364                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2804310                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  79594677                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1116242                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 76600031                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            88073                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10385869                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23123923                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        102217                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    108577171                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.705489                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.406693                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           77873399     71.72%     71.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10449451      9.62%     81.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7708887      7.10%     88.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6446636      5.94%     94.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2344597      2.16%     96.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1520287      1.40%     97.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1484500      1.37%     99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             489237      0.45%     99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             260177      0.24%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      108577171                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 112335      9.77%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                528670     45.98%     55.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               508787     44.25%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass              225      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             51038212     66.63%     66.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57114      0.07%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.70% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4060      0.01%     66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14356873     18.74%     85.45% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           11143544     14.55%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              76600031                       # Type of FU issued
system.cpu0.iq.rate                          0.685215                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1149793                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.015010                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         263002604                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         91143035                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     74349830                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              12495                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6612                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5504                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              77742883                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6716                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          356237                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1997626                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2287                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        54048                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1072719                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       202075                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       121659                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1408897                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5279939                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1209588                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80840958                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           118727                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14739399                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11667463                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            570481                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 45640                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1151814                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         54048                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        221570                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       202811                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              424381                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             76042804                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14136234                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           500738                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       130039                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25177582                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14081958                       # Number of branches executed
system.cpu0.iew.exec_stores                  11041348                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.680230                       # Inst execution rate
system.cpu0.iew.wb_sent                      75486871                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     74355334                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38977390                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 68370260                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.665135                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.570093                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       10422774                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1014025                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           357851                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    106178823                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.663049                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.560671                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     78820889     74.23%     74.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12387005     11.67%     85.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6099262      5.74%     91.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2661518      2.51%     94.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1365099      1.29%     95.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       835592      0.79%     96.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1729906      1.63%     97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       422537      0.40%     98.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1857015      1.75%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    106178823                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            58051307                       # Number of instructions committed
system.cpu0.commit.committedOps              70401754                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23336517                       # Number of memory references committed
system.cpu0.commit.loads                     12741773                       # Number of loads committed
system.cpu0.commit.membars                     415885                       # Number of memory barriers committed
system.cpu0.commit.branches                  13388774                       # Number of branches committed
system.cpu0.commit.fp_insts                      5482                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61799925                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2627242                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        47005628     66.77%     66.77% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55549      0.08%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4060      0.01%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12741773     18.10%     84.95% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10594744     15.05%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70401754                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1857015                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   172799952                       # The number of ROB reads
system.cpu0.rob.rob_writes                  164051440                       # The number of ROB writes
system.cpu0.timesIdled                         381792                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3212675                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2095454483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   57974599                       # Number of Instructions Simulated
system.cpu0.committedOps                     70325046                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.928256                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.928256                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.518603                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.518603                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                83013564                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47348236                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16364                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13356                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                268593239                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27791636                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              149451268                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                777954                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           855224                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.968896                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42357273                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           855736                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.498061                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   250.010146                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   261.958750                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.488301                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.511638                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189272310                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189272310                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12310382                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12874546                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25184928                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7941393                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      7958196                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15899589                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       183968                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180294                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       364262                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229947                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216143                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446090                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236320                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       222981                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459301                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20251775                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20832742                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41084517                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20435743                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21013036                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41448779                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       435921                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       404886                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       840807                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1879167                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1817887                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3697054                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117369                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66831                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       184200                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13653                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14181                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27834                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           33                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           38                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           71                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2315088                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2222773                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4537861                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2432457                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2289604                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4722061                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7255753500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7425105000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14680858500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137676029415                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114829611127                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252505640542                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    218997000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    196633500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    415630500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       943000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1495500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      2438500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 144931782915                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 122254716127                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267186499042                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 144931782915                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 122254716127                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267186499042                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12746303                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13279432                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26025735                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9820560                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9776083                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19596643                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       301337                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       247125                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       548462                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243600                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230324                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       473924                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236353                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223019                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459372                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22566863                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23055515                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45622378                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22868200                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23302640                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46170840                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034200                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030490                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032307                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191350                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185952                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188658                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389494                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.270434                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335848                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056047                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061570                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058731                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000170                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000155                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102588                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096410                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099466                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106369                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098255                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102274                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16644.652357                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18338.754612                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17460.438008                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73264.392901                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63166.528572                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68299.148604                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16040.210943                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13865.982653                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14932.474671                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28575.757576                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 39355.263158                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 34345.070423                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62603.142047                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55000.990262                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58879.392525                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59582.464527                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53395.572390                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56582.602182                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1675298                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       341272                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            52888                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           3016                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.676335                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   113.153846                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       704987                       # number of writebacks
system.cpu0.dcache.writebacks::total           704987                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       227007                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       186874                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       413881                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1727391                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1670069                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3397460                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8885                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9612                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18497                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954398                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1856943                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3811341                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954398                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1856943                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3811341                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       208914                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       218012                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426926                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151776                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       147818                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299594                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74095                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48646                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122741                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4768                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4569                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9337                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           33                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           38                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           71                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       360690                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       365830                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       726520                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       434785                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       414476                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       849261                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14744                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16385                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15212                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12376                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29956                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28761                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3330300500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3396411500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6726712000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11231056881                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9824685455                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21055742336                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1111837000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    752623000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1864460000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96489000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61648000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    158137000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       910000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1457500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2367500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14561357381                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13221096955                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  27782454336                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15673194381                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  13973719955                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29646914336                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2960669500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3341308500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301978000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2589197924                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2495038452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084236376                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5549867424                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5836346952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11386214376                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016390                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016417                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016404                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015455                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015120                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015288                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.245887                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.196848                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223791                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019573                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019837                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019701                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000170                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000155                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015983                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015867                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015925                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019013                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017787                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018394                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15941.011612                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.011706                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15756.154462                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73997.581179                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66464.743502                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.921300                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15005.560429                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15471.426222                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15190.197245                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20236.786913                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13492.667980                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16936.596337                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27575.757576                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 38355.263158                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33345.070423                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40370.837509                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36140.002064                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38240.453581                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36048.148811                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33714.183584                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34909.073107                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200805.039338                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203924.839792                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.171448                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170207.594268                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201602.977699                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184291.589677                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185267.306182                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202925.731094                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193916.827767                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1936787                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.471074                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38830098                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1937299                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.043420                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11154875500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   205.082456                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.388618                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400552                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598415                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998967                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42853283                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42853283                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19119269                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19710829                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38830098                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19119269                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19710829                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38830098                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19119269                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19710829                       # number of overall hits
system.cpu0.icache.overall_hits::total       38830098                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1007396                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1078417                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2085813                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1007396                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1078417                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2085813                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1007396                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1078417                       # number of overall misses
system.cpu0.icache.overall_misses::total      2085813                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14294314981                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15434234486                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  29728549467                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14294314981                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  15434234486                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  29728549467                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14294314981                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  15434234486                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  29728549467                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126665                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20789246                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40915911                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20126665                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20789246                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40915911                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20126665                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20789246                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40915911                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050053                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051874                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050978                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050053                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.051874                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050978                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050053                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051874                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050978                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14189.370398                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.935444                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.739563                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14252.739563                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14252.739563                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        19244                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              808                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.816832                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1936787                       # number of writebacks
system.cpu0.icache.writebacks::total          1936787                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71558                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76882                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       148440                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        71558                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        76882                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       148440                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        71558                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        76882                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       148440                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       935838                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1001535                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1937373                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       935838                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1001535                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1937373                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       935838                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1001535                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1937373                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12537948486                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13509677989                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  26047626475                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12537948486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13509677989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  26047626475                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12537948486                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13509677989                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  26047626475                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86506500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     86506500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047350                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047350                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047350                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.817531                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27828831                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14541667                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           548498                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17325081                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               13118302                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            75.718561                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6848129                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29493                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    57586                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               57586                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19035                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13643                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        24908                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        32678                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   702.995899                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  4885.704946                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32257     98.71%     98.71% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          309      0.95%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           56      0.17%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           25      0.08%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        32678                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        13208                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14797.811932                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12463.368567                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  8508.122633                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        12903     97.69%     97.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535          300      2.27%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        13208                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  91471142744                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.733221                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.463957                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1  91384673244     99.91%     99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3     60550000      0.07%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5     13658500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7      4816000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9      2368000      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11      1256000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13       753000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15      2182000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       292000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19       158000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21        50500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23        28500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25       277000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27        11000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29         7500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31        61500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  91471142744                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3746     68.55%     68.55% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1719     31.45%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5465                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        57586                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        57586                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5465                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5465                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        63051                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14412138                       # DTB read hits
system.cpu1.dtb.read_misses                     49815                       # DTB read misses
system.cpu1.dtb.write_hits                   10474078                       # DTB write hits
system.cpu1.dtb.write_misses                     7771                       # DTB write misses
system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3611                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1282                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      647                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14461953                       # DTB read accesses
system.cpu1.dtb.write_accesses               10481849                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24886216                       # DTB hits
system.cpu1.dtb.misses                          57586                       # DTB misses
system.cpu1.dtb.accesses                     24943802                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     7940                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7940                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2768                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4984                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          188                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7752                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1436.661507                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6120.056353                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         7301     94.18%     94.18% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          193      2.49%     96.67% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575          153      1.97%     98.65% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           37      0.48%     99.12% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           27      0.35%     99.47% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           16      0.21%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535            4      0.05%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7752                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2623                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 14933.282501                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12692.719494                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8120.359954                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          585     22.30%     22.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1248     47.58%     69.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          629     23.98%     93.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767          104      3.96%     97.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           23      0.88%     98.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151           26      0.99%     99.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.15%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535            3      0.11%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2623                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  31327211100                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.898331                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.302824                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     3189472000     10.18%     10.18% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    28134324100     89.81%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2583000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         637000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         160000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  31327211100                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1850     75.98%     75.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          585     24.02%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2435                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7940                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7940                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2435                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2435                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10375                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20791300                       # ITB inst hits
system.cpu1.itb.inst_misses                      7940                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2403                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1472                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20799240                       # ITB inst accesses
system.cpu1.itb.hits                         20791300                       # DTB hits
system.cpu1.itb.misses                           7940                       # DTB misses
system.cpu1.itb.accesses                     20799240                       # DTB accesses
system.cpu1.numCycles                       114309908                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          41263279                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     107226594                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27828831                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19966431                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     67413560                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3261213                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    132884                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                6791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              371                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       251452                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       126014                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          455                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20789251                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               378310                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3605                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         110825375                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.163723                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.274017                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                81246984     73.31%     73.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3970774      3.58%     76.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2468449      2.23%     79.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8233318      7.43%     86.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1681631      1.52%     88.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1117562      1.01%     89.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1162226      1.05%     95.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4622933      4.17%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           110825375                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.243451                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.938034                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                28317279                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             63485741                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15848519                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1697419                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1476110                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1966949                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               156570                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              88997857                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               507653                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1476110                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                29247785                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                7012026                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46712417                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16603449                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              9773269                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              85151296                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 3883                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1655595                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                301575                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               7069337                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           88292342                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            391615779                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94636441                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             6205                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             74317970                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13974372                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1570590                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1473246                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  9761371                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15285949                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11554817                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2153118                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2760852                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  81958519                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1096065                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78473689                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91016                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11494354                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     25135429                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        116024                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    110825375                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.708084                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.398689                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           79269169     71.53%     71.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10544902      9.51%     81.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8143493      7.35%     88.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6684211      6.03%     94.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2457263      2.22%     96.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1495236      1.35%     97.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1542850      1.39%     99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             479172      0.43%     99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             209079      0.19%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      110825375                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 101177      9.01%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                523345     46.61%     55.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               498385     44.38%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             2112      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52572793     66.99%     67.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59372      0.08%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4520      0.01%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14812673     18.88%     85.95% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11022213     14.05%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78473689                       # Type of FU issued
system.cpu1.iq.rate                          0.686499                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1122913                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014309                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         268972635                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         94593002                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     76135780                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14047                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7316                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6000                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79586882                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7608                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          356462                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2228793                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2378                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        52565                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1113544                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       209799                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        80325                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1476110                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5644573                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1066657                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           83187752                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           132087                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15285949                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11554817                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            564046                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44633                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1008979                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         52565                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        252953                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       220957                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              473910                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77870409                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14572543                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           545823                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       133168                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25490059                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14772585                       # Number of branches executed
system.cpu1.iew.exec_stores                  10917516                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.681222                       # Inst execution rate
system.cpu1.iew.wb_sent                      77325591                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     76141780                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39859971                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69277952                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.666100                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.575363                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       11469730                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         980041                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           393964                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    108246213                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.661810                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.544617                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     80231551     74.12%     74.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12503324     11.55%     85.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6520168      6.02%     91.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2652912      2.45%     94.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1399925      1.29%     95.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       915869      0.85%     96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1908410      1.76%     98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       405906      0.37%     98.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1708148      1.58%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    108246213                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            59004382                       # Number of instructions committed
system.cpu1.commit.committedOps              71638427                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23498429                       # Number of memory references committed
system.cpu1.commit.loads                     13057156                       # Number of loads committed
system.cpu1.commit.membars                     398159                       # Number of memory barriers committed
system.cpu1.commit.branches                  13983983                       # Number of branches committed
system.cpu1.commit.fp_insts                      5946                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62620951                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2707521                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        48077932     67.11%     67.11% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57547      0.08%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4519      0.01%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13057156     18.23%     85.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10441273     14.57%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71638427                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1708148                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   176890222                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168799668                       # The number of ROB writes
system.cpu1.timesIdled                         412724                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        3484533                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3325413921                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   58926185                       # Number of Instructions Simulated
system.cpu1.committedOps                     71560230                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.939883                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.939883                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.515495                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.515495                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84497448                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48483083                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    17003                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13376                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                275324862                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29228214                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              152523655                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                741987                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             49500500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                88000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               613500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6444000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            38204000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              128000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186303033                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36413                       # number of replacements
system.iocache.tags.tagsinuse                1.069629                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         236545551000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.069629                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.066852                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.066852                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
system.iocache.tags.data_accesses              328023                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          223                       # number of overall misses
system.iocache.overall_misses::total              223                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28112876                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28112876                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4718729157                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4718729157                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28112876                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28112876                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28112876                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28112876                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 126066.708520                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126066.708520                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130265.270456                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130265.270456                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126066.708520                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126066.708520                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           790                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   84                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.404762                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16962876                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16962876                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907529157                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2907529157                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16962876                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16962876                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16962876                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16962876                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76066.708520                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76066.708520                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80265.270456                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80265.270456                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104414                       # number of replacements
system.l2c.tags.tagsinuse                65108.520896                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5146190                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169727                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.320397                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48973.831139                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    38.132682                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000314                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4850.431967                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2918.348251                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    60.276481                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5708.347671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2559.152390                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.747281                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000582                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.044530                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000920                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.087102                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.039050                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993477                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           86                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3229                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8985                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52657                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001312                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995285                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45483372                       # Number of tag accesses
system.l2c.tags.data_accesses                45483372                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        34342                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7392                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36712                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         8266                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  86712                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       704987                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          704987                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1896241                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1896241                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              48                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  95                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            26                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            74781                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            81906                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156687                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        926050                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        990210                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1916260                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       279476                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       264100                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           543576                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         34342                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7392                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              926050                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              354257                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36712                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          8266                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              990210                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              346006                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2703235                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        34342                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7392                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             926050                       # number of overall hits
system.l2c.overall_hits::cpu0.data             354257                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36712                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         8266                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             990210                       # number of overall hits
system.l2c.overall_hits::cpu1.data             346006                       # number of overall hits
system.l2c.overall_hits::total                2703235                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           61                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           78                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  140                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1429                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1308                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2737                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            7                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           14                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              21                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          75535                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          64577                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140112                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         9644                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        11165                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20809                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8284                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         7107                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15391                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           61                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9644                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             83819                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           78                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             11165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             71684                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176452                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           61                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9644                       # number of overall misses
system.l2c.overall_misses::cpu0.data            83819                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           78                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            11165                       # number of overall misses
system.l2c.overall_misses::cpu1.data            71684                       # number of overall misses
system.l2c.overall_misses::total               176452                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      8304000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     10561500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       18998000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1634000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1961500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      3595500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       244500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       644500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       889000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  10089227500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8623421000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18712648500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1290345500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1482454999                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2772800499                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1118973000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    985050000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2104023000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      8304000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1290345500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  11208200500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     10561500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1482454999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9608471000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23608469999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      8304000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1290345500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  11208200500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     10561500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1482454999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9608471000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23608469999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        34403                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7393                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36790                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         8266                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              86852                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       704987                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       704987                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1896241                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1896241                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1477                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1355                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2832                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           33                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           38                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            71                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       150316                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       146483                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296799                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       935694                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1001375                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1937069                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       287760                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       271207                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       558967                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        34403                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7393                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          935694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          438076                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36790                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         8266                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1001375                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          417690                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2879687                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        34403                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7393                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         935694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         438076                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36790                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         8266                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1001375                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         417690                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2879687                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001773                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002120                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001612                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967502                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965314                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.966455                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.212121                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.368421                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.295775                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.502508                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.440850                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472077                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010307                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011150                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010743                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028788                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.026205                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027535                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001773                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010307                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.191334                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.002120                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011150                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.171620                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061275                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001773                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010307                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.191334                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.002120                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011150                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.171620                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061275                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 136131.147541                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 135403.846154                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total       135700                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1143.456963                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1499.617737                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1313.664596                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 34928.571429                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 46035.714286                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 42333.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133570.232343                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133537.033309                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 133554.931055                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133797.749896                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132776.981549                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133250.060022                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 135076.412361                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138602.785986                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 136704.762524                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136131.147541                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133797.749896                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133719.091137                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135403.846154                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132776.981549                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134039.269572                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 133795.423112                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136131.147541                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133797.749896                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133719.091137                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135403.846154                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132776.981549                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134039.269572                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 133795.423112                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95712                       # number of writebacks
system.l2c.writebacks::total                    95712                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           65                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           80                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          145                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             65                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             80                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                157                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            65                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            80                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               157                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           61                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           78                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             140                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1429                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1308                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2737                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           14                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           21                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        75535                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        64577                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140112                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         9637                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        11160                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20797                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8219                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         7027                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15246                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           61                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         9637                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        83754                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           78                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        11160                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        71604                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176295                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           61                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         9637                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        83754                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           78                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        11160                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        71604                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176295                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14744                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16385                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31797                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15212                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12376                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        29956                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        28761                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59385                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7694000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9781500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     17598000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    101176000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     92589498                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    193765498                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       498000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       992000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1490000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9333877500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   7977651000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  17311528500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1193475000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1370290499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2563765499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1028914000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    905231000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1934145000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      7694000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1193475000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  10362791500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      9781500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1370290499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   8882882000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21827036999                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      7694000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1193475000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  10362791500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      9781500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1370290499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   8882882000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21827036999                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2776351500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3136471000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5988830497                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2412145000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2352634000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4764779000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5188496500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5489105000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10753609497                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.967502                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.965314                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.966455                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.212121                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.368421                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.295775                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.502508                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.440850                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472077                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010736                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028562                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025910                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027275                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.191186                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.171429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061220                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.191186                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.171429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061220                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total       125700                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70801.959412                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70787.077982                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70794.847643                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71142.857143                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70952.380952                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123570.232343                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123537.033309                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123554.931055                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123275.736837                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.249057                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128821.830084                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126862.455726                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188303.818502                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191423.314007                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188345.771519                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158568.564291                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190096.477052                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172712.012469                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173203.915743                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190852.369528                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 181082.924931                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
system.membus.trans_dist::ReadResp              68202                       # Transaction distribution
system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       131902                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8715                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             21                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4647                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138223                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138223                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36406                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473420                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       581002                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108889                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108889                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 689891                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17331100                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17495093                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19812213                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              495                       # Total snoops (count)
system.membus.snoop_fanout::samples            415719                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  415719    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              415719                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95454500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1728500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           923427409                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1018310336                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64109029                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5625045                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2831932                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        48184                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            419                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             147963                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2644441                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       836893                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1896241                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          151625                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2832                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            71                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2903                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296799                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296799                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1937373                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       559190                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5772018                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2682598                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        40560                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162458                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8657634                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    245374528                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100080181                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62636                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284772                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              345802117                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          207035                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3148875                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027211                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.162698                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                3063191     97.28%     97.28% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  85684      2.72%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3148875                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5537375493                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           269876                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2909027051                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1330509019                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          24943913                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          91705109                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------