path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.823216                       # Number of seconds simulated
sim_ticks                                2823215630500                       # Number of ticks simulated
final_tick                               2823215630500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 103983                       # Simulator instruction rate (inst/s)
host_op_rate                                   126208                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2510129357                       # Simulator tick rate (ticks/s)
host_mem_usage                                 634500                       # Number of bytes of host memory used
host_seconds                                  1124.73                       # Real time elapsed on the host
sim_insts                                   116952239                       # Number of instructions simulated
sim_ops                                     141949733                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         3840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           675712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5138656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           695680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4658888                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11177960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       675712                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       695680                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1371392                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8449664                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8467188                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           60                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10558                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             80810                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           65                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10870                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             72797                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175176                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          132026                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136407                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1360                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              239341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1820143                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              246414                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1650206                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3959301                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         239341                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         246414                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             485755                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2992922                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2999129                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2992922                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             239341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1826347                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1473                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             246414                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1650209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6958430                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175177                       # Number of read requests accepted
system.physmem.writeReqs                       136407                       # Number of write requests accepted
system.physmem.readBursts                      175177                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     136407                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11201984                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8480320                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11178024                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8467188                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40863                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11773                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10998                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11169                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10855                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11706                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11087                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11923                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11611                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10970                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11831                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10190                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9677                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10224                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10941                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10213                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9863                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8674                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8377                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8725                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8463                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8546                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8273                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8696                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8627                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8420                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9181                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7887                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7530                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7884                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8402                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7675                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7145                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    2823215466500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174621                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 132026                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    103839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62706                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1745                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2048                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4769                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     8079                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       23                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65918                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.586729                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.315744                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.746281                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          25059     38.02%     38.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16073     24.38%     62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6703     10.17%     72.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3821      5.80%     78.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2972      4.51%     82.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1599      2.43%     85.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1035      1.57%     86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1073      1.63%     88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7583     11.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65918                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6682                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.191410                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      482.907115                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6680     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6682                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6682                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.830141                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.245831                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.832578                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 5      0.07%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                6      0.09%      0.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               9      0.13%      0.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5722     85.63%     86.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             190      2.84%     89.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              49      0.73%     89.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             177      2.65%     92.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              24      0.36%     92.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             142      2.13%     94.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              60      0.90%     95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.12%     95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              19      0.28%     96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              22      0.33%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               9      0.13%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             156      2.33%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.09%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               8      0.12%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              20      0.30%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               2      0.03%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.04%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.16%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6682                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2754544250                       # Total ticks spent queuing
system.physmem.totMemAccLat                6036375500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    875155000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15737.47                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34487.47                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.81                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     143966                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97651                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.69                       # Row buffer hit rate for writes
system.physmem.avgGap                      9060848.65                       # Average gap between requests
system.physmem.pageHitRate                      78.56                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  261734760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  142811625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 710751600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                443108880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           184398261840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80170181370                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1623600588000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1889727438075                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.354462                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2700891551000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     94273140000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     28044170250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  236605320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  129100125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 654482400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                415523520                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           184398261840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79085731860                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1624551859500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1889471564565                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.263829                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2702486818500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     94273140000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26455661500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              249                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          249                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          249                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             249                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               26494710                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13632658                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           507079                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            16292260                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12421928                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            76.244352                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6636932                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             27006                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    55575                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               55575                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17227                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13739                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore        24609                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples        30966                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean   596.880450                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev  3694.116884                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191        30106     97.22%     97.22% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383          526      1.70%     98.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575          216      0.70%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767           59      0.19%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.05%     99.86% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151           19      0.06%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343            8      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::90112-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        30966                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        13159                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13974.808116                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11468.359848                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  9225.442290                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         9399     71.43%     71.43% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3482     26.46%     97.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151          252      1.92%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.06%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455           15      0.11%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        13159                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  78337685356                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.743824                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.461899                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1  78259560856     99.90%     99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3     54393500      0.07%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5     11721500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7      4062000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9      2302000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11      1574000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13       883500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15      2122500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       542000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19       148500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21        83000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23        91000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25        86000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27        15500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29        21000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31        78500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  78337685356                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3804     69.37%     69.37% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1680     30.63%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5484                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        55575                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        55575                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5484                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5484                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        61059                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    13854800                       # DTB read hits
system.cpu0.dtb.read_misses                     47874                       # DTB read misses
system.cpu0.dtb.write_hits                   10355704                       # DTB write hits
system.cpu0.dtb.write_misses                     7701                       # DTB write misses
system.cpu0.dtb.flush_tlb                         184                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     458                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3595                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      904                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1404                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      604                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                13902674                       # DTB read accesses
system.cpu0.dtb.write_accesses               10363405                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24210504                       # DTB hits
system.cpu0.dtb.misses                          55575                       # DTB misses
system.cpu0.dtb.accesses                     24266079                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     7385                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                7385                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2112                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5086                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore          187                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples         7198                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1405.946096                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  5932.758848                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191         6773     94.10%     94.10% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383          190      2.64%     96.74% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575          140      1.94%     98.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767           47      0.65%     99.33% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959           11      0.15%     99.49% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.22%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343            7      0.10%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.06%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         7198                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2651                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 14423.425123                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 12051.974959                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  8640.644527                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         1863     70.28%     70.28% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          733     27.65%     97.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           46      1.74%     99.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            4      0.15%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-81919            4      0.15%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2651                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples  35368734396                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.609046                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.488267                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    13831462500     39.11%     39.11% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    21534286896     60.89%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2        2356000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         358500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         226000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          44500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total  35368734396                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1897     76.99%     76.99% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          567     23.01%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2464                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7385                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7385                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2464                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2464                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         9849                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    20114587                       # ITB inst hits
system.cpu0.itb.inst_misses                      7385                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         184                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     458                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2409                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1479                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20121972                       # ITB inst accesses
system.cpu0.itb.hits                         20114587                       # DTB hits
system.cpu0.itb.misses                           7385                       # DTB misses
system.cpu0.itb.accesses                     20121972                       # DTB accesses
system.cpu0.numCycles                       110325192                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          39212585                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     103212139                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   26494710                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19058860                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     65985336                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3113233                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    120421                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                6405                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              451                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       171105                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       126190                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          599                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20113194                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               349758                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3372                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         107179671                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.158056                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.272689                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                78729483     73.46%     73.46% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3807123      3.55%     77.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2383498      2.22%     79.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8002443      7.47%     86.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1574194      1.47%     88.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1068807      1.00%     89.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 5993116      5.59%     94.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1028903      0.96%     95.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4592104      4.28%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           107179671                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.240151                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.935526                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26754853                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             62165032                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15379945                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1465673                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1413940                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1877729                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               144724                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              85569568                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               471665                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1413940                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27587165                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                6832428                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      44962784                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16009333                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10373762                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              81846595                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 4353                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1036687                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                217532                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               8369836                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           84011397                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            377628674                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        91338127                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6488                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             71240050                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                12771347                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1555221                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1457428                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8538957                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            14623040                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11507305                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1985956                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2777400                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  78787811                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1106001                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 75754836                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            87181                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10581035                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     23286965                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        104667                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    107179671                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.706802                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.408587                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           76952421     71.80%     71.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10093269      9.42%     81.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7647177      7.13%     88.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6479607      6.05%     94.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2319282      2.16%     96.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1495618      1.40%     97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1437164      1.34%     99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             490874      0.46%     99.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             264259      0.25%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      107179671                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 115831     10.14%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     2      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                518494     45.41%     55.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               507518     44.45%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass              661      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             50460858     66.61%     66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56393      0.07%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   2      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4124      0.01%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14247837     18.81%     85.50% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10984955     14.50%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              75754836                       # Type of FU issued
system.cpu0.iq.rate                          0.686650                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1141845                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.015073                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         259903837                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         90518348                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     73472782                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              14532                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              7678                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         6317                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              76888224                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7796                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          347025                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2039138                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2398                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        52342                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1081901                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       214750                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       120180                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1413940                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5391499                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1208860                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           80024251                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           117807                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             14623040                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11507305                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            566411                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44037                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1152589                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         52342                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        226715                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       204902                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              431617                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             75186689                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14022863                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           512703                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       130439                       # number of nop insts executed
system.cpu0.iew.exec_refs                    24907066                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                13969302                       # Number of branches executed
system.cpu0.iew.exec_stores                  10884203                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.681501                       # Inst execution rate
system.cpu0.iew.wb_sent                      74615293                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     73479099                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 38405173                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 66942375                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.666023                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.573705                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       10599640                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1001334                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           364365                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    104754954                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.662419                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.562446                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     77896212     74.36%     74.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12060503     11.51%     85.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6064743      5.79%     91.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2632493      2.51%     94.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1283946      1.23%     95.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       809122      0.77%     96.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1758606      1.68%     97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       423456      0.40%     98.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1825873      1.74%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    104754954                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            57128680                       # Number of instructions committed
system.cpu0.commit.committedOps              69391674                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23009306                       # Number of memory references committed
system.cpu0.commit.loads                     12583902                       # Number of loads committed
system.cpu0.commit.membars                     411216                       # Number of memory barriers committed
system.cpu0.commit.branches                  13247589                       # Number of branches committed
system.cpu0.commit.fp_insts                      6270                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 60931939                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2625183                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        46323475     66.76%     66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          54770      0.08%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4123      0.01%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12583902     18.13%     84.98% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10425404     15.02%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         69391674                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1825873                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   170570043                       # The number of ROB reads
system.cpu0.rob.rob_writes                  162411378                       # The number of ROB writes
system.cpu0.timesIdled                         376879                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3145521                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3401736013                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   57049783                       # Number of Instructions Simulated
system.cpu0.committedOps                     69312777                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.933841                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.933841                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.517106                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.517106                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                81821198                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46866866                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    17105                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13418                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                265587152                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                27327021                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              147986326                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                766351                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           853611                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.969012                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42370591                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           854123                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.607130                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   245.218931                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   266.750082                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.478943                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.520996                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189281396                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189281396                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12194786                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12990656                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25185442                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7797154                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8115139                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15912293                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       180462                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183787                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       364249                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       226816                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       219266                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446082                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       233369                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       225947                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459316                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     19991940                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21105795                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41097735                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20172402                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21289582                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41461984                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       443820                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       393552                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       837372                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1867983                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1822110                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3690093                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       116689                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        67398                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       184087                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13736                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14086                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27822                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           22                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           37                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           59                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2311803                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2215662                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4527465                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2428492                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2283060                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4711552                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7869813000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6681390000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14551203000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133422309506                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 119214285196                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252636594702                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    223256500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    190032500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    413289000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       642500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1203500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1846000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 141292122506                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 125895675196                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267187797702                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 141292122506                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 125895675196                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267187797702                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     12638606                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13384208                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26022814                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9665137                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9937249                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19602386                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       297151                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       251185                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       548336                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       240552                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       233352                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       473904                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       233391                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       225984                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459375                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22303743                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23321457                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45625200                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     22600894                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23572642                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46173536                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.035116                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.029404                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032178                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.193270                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.183362                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188247                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.392693                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.268320                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335719                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.057102                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.060364                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058708                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000094                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000164                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000128                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103651                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.095005                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099232                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107451                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096852                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.102040                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17731.992700                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16977.146603                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17377.226609                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71425.869243                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 65426.502898                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68463.476314                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16253.385265                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13490.877467                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14854.755230                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 29204.545455                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 32527.027027                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31288.135593                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61117.717429                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56820.794506                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 59014.878680                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 58181.012129                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 55143.393164                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56709.083907                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1668942                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       344724                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            52797                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2974                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.610546                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   115.912576                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       704529                       # number of writebacks
system.cpu0.dcache.writebacks::total           704529                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       234419                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       177315                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       411734                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1718052                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1672745                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3390797                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8852                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9685                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18537                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1952471                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1850060                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3802531                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1952471                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1850060                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3802531                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       209401                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216237                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       425638                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149931                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149365                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299296                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74210                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48624                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       122834                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4884                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4401                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           22                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           37                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           59                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       359332                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       365602                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       724934                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       433542                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       414226                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       847768                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14882                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16247                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15129                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12459                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30011                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28706                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3375153500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3319848000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6695001500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10890989929                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10174119354                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21065109283                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1087064000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    772421000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1859485000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96297500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58981000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    155278500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       620500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1166500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1787000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14266143429                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13493967354                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  27760110783                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15353207429                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14266388354                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29619595783                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2817683000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3126439500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5944122500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2431141924                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2360887452                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4792029376                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5248824924                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5487326952                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10736151876                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016568                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016156                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016356                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015513                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015031                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015268                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.249738                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.193578                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224012                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.020303                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018860                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019593                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000094                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000164                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000128                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016111                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015677                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015889                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019183                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017572                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018360                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.134584                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15352.821210                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15729.332202                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72640.013933                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 68115.819328                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70382.194493                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14648.484032                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15885.591477                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15138.194637                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19716.932842                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13401.726880                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16723.586430                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28204.545455                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 31527.027027                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30288.135593                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39701.845171                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36908.899169                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38293.293987                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35413.425756                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34441.074085                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34938.327211                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189334.968418                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192431.802794                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190951.283369                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160694.158504                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189492.531664                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173699.774395                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174896.702009                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191156.098098                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182845.715483                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1936695                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.472430                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           38860636                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1937207                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.060136                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11042568500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   296.854540                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   214.617890                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.579794                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.419176                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998970                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          162                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42883011                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42883011                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19112796                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19747840                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       38860636                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19112796                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19747840                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        38860636                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19112796                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19747840                       # number of overall hits
system.cpu0.icache.overall_hits::total       38860636                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       999725                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1085355                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2085080                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       999725                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1085355                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2085080                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       999725                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1085355                       # number of overall misses
system.cpu0.icache.overall_misses::total      2085080                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14134312480                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15390349487                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  29524661967                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14134312480                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  15390349487                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  29524661967                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14134312480                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  15390349487                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  29524661967                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20112521                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20833195                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     40945716                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20112521                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20833195                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     40945716                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20112521                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20833195                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     40945716                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.049707                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052097                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050923                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.049707                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052097                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050923                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.049707                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052097                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050923                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14138.200485                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14180.014361                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14159.966029                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14138.200485                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14180.014361                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14159.966029                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14138.200485                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14180.014361                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14159.966029                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        20835                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              782                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.643223                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70586                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        77198                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       147784                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        70586                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        77198                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       147784                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        70586                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        77198                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       147784                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       929139                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1008157                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1937296                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       929139                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1008157                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1937296                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       929139                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1008157                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1937296                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12404793984                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13457356489                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  25862150473                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12404793984                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13457356489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  25862150473                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12404793984                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13457356489                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  25862150473                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86442500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86442500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86442500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     86442500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047314                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047314                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047314                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13349.612281                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13349.612281                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13349.612281                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129404.940120                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129404.940120                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27956882                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14656819                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           538960                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17404345                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               13151851                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            75.566481                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6863409                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29253                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    58688                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               58688                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18912                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13793                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore        25983                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        32705                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean   608.026296                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev  3710.555117                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383        32390     99.04%     99.04% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767          251      0.77%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151           38      0.12%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535           12      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        32705                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        12474                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12069.344236                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9799.859677                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7714.985856                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         4605     36.92%     36.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5236     41.98%     78.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2264     18.15%     97.04% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767          177      1.42%     98.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           81      0.65%     99.11% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151          107      0.86%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        12474                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  91615628244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.688499                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.485401                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3  91592721244     99.97%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7     15376000      0.02%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11      3652500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15      2610000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19       561000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23       145500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27       138500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31       418000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35         5500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  91615628244                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3400     68.01%     68.01% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1599     31.99%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         4999                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58688                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58688                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         4999                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         4999                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        63687                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14526505                       # DTB read hits
system.cpu1.dtb.read_misses                     49054                       # DTB read misses
system.cpu1.dtb.write_hits                   10631798                       # DTB write hits
system.cpu1.dtb.write_misses                     9634                       # DTB write misses
system.cpu1.dtb.flush_tlb                         178                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     459                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3274                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      667                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1336                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      600                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14575559                       # DTB read accesses
system.cpu1.dtb.write_accesses               10641432                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         25158303                       # DTB hits
system.cpu1.dtb.misses                          58688                       # DTB misses
system.cpu1.dtb.accesses                     25216991                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     7824                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                7824                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2815                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4844                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore          165                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples         7659                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1312.247030                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  5391.308444                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191         7206     94.09%     94.09% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383          209      2.73%     96.81% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575          155      2.02%     98.84% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767           49      0.64%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959           13      0.17%     99.65% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151           13      0.17%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343            4      0.05%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         7659                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2378                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12869.007569                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10590.567886                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  8075.239006                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          829     34.86%     34.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383          979     41.17%     76.03% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          513     21.57%     97.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           16      0.67%     98.28% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959           11      0.46%     98.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151           27      1.14%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2378                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  31482348100                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.924096                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.265389                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     2393427520      7.60%      7.60% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1    29085771080     92.39%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2        2580000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3         481500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          88000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  31482348100                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1649     74.51%     74.51% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          564     25.49%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2213                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7824                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7824                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2213                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2213                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        10037                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    20834938                       # ITB inst hits
system.cpu1.itb.inst_misses                      7824                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         178                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     459                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2128                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1257                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20842762                       # ITB inst accesses
system.cpu1.itb.hits                         20834938                       # DTB hits
system.cpu1.itb.misses                           7824                       # DTB misses
system.cpu1.itb.accesses                     20842762                       # DTB accesses
system.cpu1.numCycles                       114249199                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          41440028                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     108062066                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27956882                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          20015260                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     67364504                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3251122                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    125092                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                4580                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              348                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       238931                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       130362                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20833198                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               375306                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3528                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         110929848                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.171009                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.281658                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                81198239     73.20%     73.20% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3985157      3.59%     76.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2477511      2.23%     79.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8258795      7.45%     86.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1633809      1.47%     87.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1136557      1.02%     88.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6389922      5.76%     94.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1173130      1.06%     95.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4676728      4.22%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           110929848                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.244701                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.945845                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                28438107                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             63381229                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15870082                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1769017                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1471120                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1958077                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               156563                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              89815738                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               503200                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1471120                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                29385148                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                6578856                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      46582606                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16681881                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             10229932                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              85972606                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 3235                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1759145                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                332326                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               7382577                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           89179456                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            395930491                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        95980229                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5368                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             75492279                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13687169                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1580321                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1483697                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10084798                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15398688                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11726928                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2180756                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2876636                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  82789954                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1104868                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 79357586                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91701                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       11257862                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     24898946                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        112169                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    110929848                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.715385                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.405643                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           79077492     71.29%     71.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10621201      9.57%     80.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8213587      7.40%     88.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6738763      6.07%     94.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2479052      2.23%     96.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1519430      1.37%     97.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1589812      1.43%     99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             483396      0.44%     99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             207115      0.19%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      110929848                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  95512      8.42%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     5      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                536739     47.33%     55.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               501765     44.25%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             1676      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             53175622     67.01%     67.01% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               60064      0.08%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4456      0.01%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14922442     18.80%     85.90% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11193322     14.10%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              79357586                       # Type of FU issued
system.cpu1.iq.rate                          0.694601                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1134021                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014290                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         270859048                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         95198962                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     77052102                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11694                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6328                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5212                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              80483666                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6265                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          368068                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2171413                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2447                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        53780                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1110791                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       197752                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        83861                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1471120                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5242635                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1056196                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           84025940                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           131684                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15398688                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11726928                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            568087                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44365                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               998937                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         53780                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        246243                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       216797                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              463040                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             78768106                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14688147                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           530926                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       131118                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25774139                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14898432                       # Number of branches executed
system.cpu1.iew.exec_stores                  11085992                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.689441                       # Inst execution rate
system.cpu1.iew.wb_sent                      78239059                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     77057314                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 40452895                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 70755105                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.674467                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.571731                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       11247994                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         992699                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           384482                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    108382892                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.670890                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.556432                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     80053687     73.86%     73.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12617943     11.64%     85.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6573081      6.06%     91.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2685794      2.48%     94.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1383289      1.28%     95.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       946585      0.87%     96.20% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1968943      1.82%     98.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       416822      0.38%     98.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1736748      1.60%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    108382892                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            59978464                       # Number of instructions committed
system.cpu1.commit.committedOps              72712964                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23843412                       # Number of memory references committed
system.cpu1.commit.loads                     13227275                       # Number of loads committed
system.cpu1.commit.membars                     402801                       # Number of memory barriers committed
system.cpu1.commit.branches                  14144728                       # Number of branches committed
system.cpu1.commit.fp_insts                      5158                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 63547368                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2716364                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        48806787     67.12%     67.12% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          58309      0.08%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4456      0.01%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       13227275     18.19%     85.40% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10616137     14.60%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         72712964                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1736748                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                   177811075                       # The number of ROB reads
system.cpu1.rob.rob_writes                  170472987                       # The number of ROB writes
system.cpu1.timesIdled                         411472                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        3319351                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2020087270                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   59902456                       # Number of Instructions Simulated
system.cpu1.committedOps                     72636956                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.907254                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.907254                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.524314                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.524314                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                85743042                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48986759                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16090                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13161                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                278464634                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                29701060                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              152671939                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                753578                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186358814                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36423                       # number of replacements
system.iocache.tags.tagsinuse                1.069707                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         236268040000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.069707                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.066857                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.066857                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
system.iocache.tags.data_accesses              328113                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          233                       # number of overall misses
system.iocache.overall_misses::total              233                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28976877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28976877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4697901937                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4697901937                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28976877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28976877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28976877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28976877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124364.278970                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124364.278970                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129690.314074                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129690.314074                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124364.278970                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124364.278970                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124364.278970                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124364.278970                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17326877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17326877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886701937                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2886701937                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17326877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17326877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17326877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17326877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74364.278970                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74364.278970                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79690.314074                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79690.314074                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74364.278970                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74364.278970                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74364.278970                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74364.278970                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104486                       # number of replacements
system.l2c.tags.tagsinuse                65102.270180                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5137781                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169691                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    30.277275                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              74417430500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48932.992978                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    44.632841                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000308                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5110.689574                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3054.335380                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    49.005856                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5438.208710                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2472.404533                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.746658                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000681                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.077983                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.046605                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000748                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.082980                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.037726                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993382                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65113                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           92                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          349                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3230                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8952                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52567                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.993546                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 45423392                       # Number of tag accesses
system.l2c.tags.data_accesses                45423392                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        33657                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         7428                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        33997                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7416                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  82498                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          704529                       # number of Writeback hits
system.l2c.Writeback_hits::total               704529                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              46                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              43                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  89                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            17                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            27                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                44                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            75544                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            80883                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156427                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        919122                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        997106                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1916228                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       280073                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       262362                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           542435                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         33657                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          7428                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              919122                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              355617                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         33997                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7416                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              997106                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              343245                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2697588                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        33657                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         7428                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             919122                       # number of overall hits
system.l2c.overall_hits::cpu0.data             355617                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        33997                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7416                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             997106                       # number of overall hits
system.l2c.overall_hits::cpu1.data             343245                       # number of overall hits
system.l2c.overall_hits::total                2697588                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           60                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           65                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  126                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1353                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1475                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2828                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            5                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           10                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              15                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73008                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          66984                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139992                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         9909                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10879                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           20788                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8402                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         6880                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          15282                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker           60                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9909                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             81410                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           65                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10879                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             73864                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176188                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           60                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9909                       # number of overall misses
system.l2c.overall_misses::cpu0.data            81410                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           65                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10879                       # number of overall misses
system.l2c.overall_misses::cpu1.data            73864                       # number of overall misses
system.l2c.overall_misses::total               176188                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      8148000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       132500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      8671500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       16952000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1131000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1697000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2828000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       321500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       486000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       807500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9751098000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8968779000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  18719877000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1326214000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1439991500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2766205500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1135776500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    951425500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2087202000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      8148000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1326214000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  10886874500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      8671500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1439991500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9920204500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23590236500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      8148000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1326214000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  10886874500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      8671500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1439991500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9920204500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23590236500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        33717                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         7429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        34062                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7416                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              82624                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       704529                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           704529                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1399                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1518                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2917                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           22                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           37                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            59                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       148552                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       147867                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296419                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       929031                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1007985                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1937016                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       288475                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       269242                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       557717                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        33717                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          929031                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          437027                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        34062                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7416                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1007985                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          417109                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2873776                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        33717                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         929031                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         437027                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        34062                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7416                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1007985                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         417109                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2873776                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001780                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.001525                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967119                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.971673                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.969489                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.227273                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.270270                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.254237                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.491464                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.453002                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472277                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010666                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010793                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010732                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029126                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.025553                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.027401                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001780                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010666                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.186281                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010793                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.177086                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061309                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001780                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010666                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.186281                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010793                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.177086                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061309                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       135800                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 134539.682540                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   835.920177                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1150.508475                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total         1000                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        64300                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        48600                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 53833.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133562.047995                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133894.347904                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 133721.048346                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133839.337976                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132364.325765                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133067.418703                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 135179.302547                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138288.590116                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 136579.112682                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135800                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133839.337976                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133728.958359                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132364.325765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 134303.645890                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 133892.413218                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       135800                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133839.337976                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133728.958359                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132364.325765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 134303.645890                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 133892.413218                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95836                       # number of writebacks
system.l2c.writebacks::total                    95836                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            8                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           74                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           70                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          144                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             70                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                158                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            74                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            70                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               158                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           60                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           65                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             126                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1353                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1475                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2828                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           10                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           15                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73008                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        66984                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139992                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         9901                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10873                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        20774                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8328                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6810                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        15138                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           60                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         9901                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        81336                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           65                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10873                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        73794                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176030                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           60                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         9901                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        81336                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           65                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10873                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        73794                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176030                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14882                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16247                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        31797                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15129                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12459                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30011                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        28706                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        59385                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7548000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8021500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     15692000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     95744499                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    104404500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    200148999                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       352000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       710500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1062500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9021018000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8298939000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  17319957000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1226577500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1330570000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2557147500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1043994500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    875170000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1919164500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      7548000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1226577500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  10065012500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      8021500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1330570000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   9174109000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21811961000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      7548000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1226577500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  10065012500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      8021500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1330570000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   9174109000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21811961000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     75943997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2631657000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2923348500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5630949497                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2255045500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2217542500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4472588000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     75943997                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4886702500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5140891000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10103537497                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001780                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.001525                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.967119                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.971673                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.969489                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.227273                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.270270                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.254237                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.491464                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.453002                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472277                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010657                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010787                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010725                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028869                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025293                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027143                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001780                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010657                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.186112                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.176918                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061254                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001780                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010657                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.186112                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.176918                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061254                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       125800                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 124539.682540                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70764.596452                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.711864                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70774.044908                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70400                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71050                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123562.047995                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123894.347904                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123721.048346                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123884.203616                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123093.650717                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125359.570125                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128512.481645                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126777.942925                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125800                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123884.203616                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123746.096439                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.527414                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123910.475487                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125800                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123884.203616                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123746.096439                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.527414                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123910.475487                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176834.901223                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179931.587370                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 177090.590213                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149054.497984                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177987.198009                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162120.777149                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162830.378861                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179087.682018                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 170136.187539                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
system.membus.trans_dist::ReadResp              68067                       # Transaction distribution
system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
system.membus.trans_dist::Writeback            132026                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8663                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             15                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4641                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138194                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138194                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         36271                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473134                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       580716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108899                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108899                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 689615                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17328028                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17492021                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19809141                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              503                       # Total snoops (count)
system.membus.snoop_fanout::samples            415635                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  415635    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              415635                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95974000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1718000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           923083346                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1016456858                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64493372                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5623278                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2831878                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        48082                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            557                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          557                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             147787                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2643011                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           836563                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2046694                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2917                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            59                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2976                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296419                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296419                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1937296                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       557950                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5772132                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2677725                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        39632                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       158982                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8648471                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124011712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99951221                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        59380                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       271116                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              224293429                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          211232                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          5937467                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.022790                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.149234                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5802151     97.72%     97.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 135316      2.28%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            5937467                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3598371995                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           378877                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2908371640                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1327935857                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          24806959                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          91622154                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------