path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.550456                       # Number of seconds simulated
sim_ticks                                2550455693500                       # Number of ticks simulated
final_tick                               2550455693500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  59744                       # Simulator instruction rate (inst/s)
host_op_rate                                    76873                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2526372396                       # Simulator tick rate (ticks/s)
host_mem_usage                                 427472                       # Number of bytes of host memory used
host_seconds                                  1009.53                       # Real time elapsed on the host
sim_insts                                    60313472                       # Number of instructions simulated
sim_ops                                      77606209                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           504320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5079000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           295488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4015064                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131007536                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       504320                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       295488                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          799808                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3786368                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1520720                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1495380                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6802468                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7880                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             79395                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4617                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             62741                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293498                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59162                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           380180                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           373845                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813187                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47485839                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           853                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              197737                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1991409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              115857                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1574254                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51366325                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         197737                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         115857                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             313594                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1484585                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             596254                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             586319                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2667158                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1484585                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47485839                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          853                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             197737                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2587663                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             115857                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2160572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54033483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293498                       # Number of read requests accepted
system.physmem.writeReqs                       813187                       # Number of write requests accepted
system.physmem.readBursts                    15293498                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     813187                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                978241024                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    542848                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6911808                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131007536                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6802468                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     8482                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  705190                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4696                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              955869                       # Per bank write bursts
system.physmem.perBankRdBursts::1              955539                       # Per bank write bursts
system.physmem.perBankRdBursts::2              954667                       # Per bank write bursts
system.physmem.perBankRdBursts::3              954789                       # Per bank write bursts
system.physmem.perBankRdBursts::4              955759                       # Per bank write bursts
system.physmem.perBankRdBursts::5              955951                       # Per bank write bursts
system.physmem.perBankRdBursts::6              954859                       # Per bank write bursts
system.physmem.perBankRdBursts::7              954668                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956272                       # Per bank write bursts
system.physmem.perBankRdBursts::9              955769                       # Per bank write bursts
system.physmem.perBankRdBursts::10             954516                       # Per bank write bursts
system.physmem.perBankRdBursts::11             954114                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956222                       # Per bank write bursts
system.physmem.perBankRdBursts::13             955973                       # Per bank write bursts
system.physmem.perBankRdBursts::14             955087                       # Per bank write bursts
system.physmem.perBankRdBursts::15             954962                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6687                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6466                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6605                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6628                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6579                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6834                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6823                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6763                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7134                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6882                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6543                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6191                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7147                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6760                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7044                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6911                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2550454486000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      44                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154638                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754025                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  59162                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1173632                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1113468                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1067801                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3688063                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2661485                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2656312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2669345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     52900                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59933                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     20414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    20379                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    20336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20242                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20201                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4835                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5055                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        86865                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11341.188281                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1014.168764                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16824.493217                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          23628     27.20%     27.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14156     16.30%     43.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         2700      3.11%     46.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2166      2.49%     49.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1318      1.52%     50.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1170      1.35%     51.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          896      1.03%     52.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519          913      1.05%     54.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          566      0.65%     54.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          606      0.70%     55.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          521      0.60%     55.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          631      0.73%     56.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          271      0.31%     57.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          267      0.31%     57.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          154      0.18%     57.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          590      0.68%     58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          110      0.13%     58.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          147      0.17%     58.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223           73      0.08%     58.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          151      0.17%     58.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351           55      0.06%     58.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415          532      0.61%     59.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479           32      0.04%     59.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          226      0.26%     59.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           18      0.02%     59.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671          114      0.13%     59.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           25      0.03%     59.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799          112      0.13%     60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           26      0.03%     60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           51      0.06%     60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           19      0.02%     60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          424      0.49%     60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119           10      0.01%     60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           29      0.03%     60.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           12      0.01%     60.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311           47      0.05%     60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375           15      0.02%     60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           23      0.03%     60.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503           12      0.01%     60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567          153      0.18%     60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631           13      0.01%     60.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           25      0.03%     61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759            8      0.01%     61.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823           30      0.03%     61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887           14      0.02%     61.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           22      0.03%     61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015            8      0.01%     61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          344      0.40%     61.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143            8      0.01%     61.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           12      0.01%     61.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            9      0.01%     61.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335          150      0.17%     61.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399           12      0.01%     61.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463            8      0.01%     61.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527           14      0.02%     61.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591          136      0.16%     61.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655           11      0.01%     61.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           13      0.01%     61.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783           10      0.01%     61.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847           83      0.10%     62.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911            9      0.01%     62.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           12      0.01%     62.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039           10      0.01%     62.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          470      0.54%     62.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            7      0.01%     62.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           13      0.01%     62.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295            8      0.01%     62.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359           83      0.10%     62.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423           13      0.01%     62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           10      0.01%     62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551           11      0.01%     62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615           20      0.02%     62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679           11      0.01%     62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743            7      0.01%     62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807            8      0.01%     62.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871          151      0.17%     63.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            7      0.01%     63.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           13      0.01%     63.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063           10      0.01%     63.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          397      0.46%     63.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            3      0.00%     63.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           13      0.01%     63.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            7      0.01%     63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383           18      0.02%     63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447           13      0.01%     63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511            9      0.01%     63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575           10      0.01%     63.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639           76      0.09%     63.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            6      0.01%     63.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767           11      0.01%     63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            5      0.01%     63.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895          208      0.24%     63.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            5      0.01%     63.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023           13      0.01%     63.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087            7      0.01%     63.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          368      0.42%     64.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            6      0.01%     64.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279            3      0.00%     64.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343            4      0.00%     64.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407           73      0.08%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471            2      0.00%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535            7      0.01%     64.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            5      0.01%     64.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663          137      0.16%     64.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727           10      0.01%     64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791           24      0.03%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855            2      0.00%     64.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           60      0.07%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983            5      0.01%     64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047            5      0.01%     64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111            7      0.01%     64.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          270      0.31%     65.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239            5      0.01%     65.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303           10      0.01%     65.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367            9      0.01%     65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431          215      0.25%     65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495            8      0.01%     65.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559           21      0.02%     65.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            7      0.01%     65.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687            8      0.01%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815            2      0.00%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           69      0.08%     65.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007            4      0.00%     65.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071            6      0.01%     65.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          602      0.69%     66.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8391            1      0.00%     66.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           67      0.08%     66.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8647            1      0.00%     66.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711            2      0.00%     66.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967          203      0.23%     66.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          262      0.30%     66.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9287            1      0.00%     66.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           56      0.06%     66.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735          129      0.15%     67.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9799            1      0.00%     67.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991           65      0.07%     67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055            1      0.00%     67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          354      0.41%     67.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10375            1      0.00%     67.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503          132      0.15%     67.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759           66      0.08%     67.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015            2      0.00%     67.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          377      0.43%     68.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527          143      0.16%     68.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783            1      0.00%     68.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039           65      0.07%     68.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          444      0.51%     68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551           65      0.07%     69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679            1      0.00%     69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807          120      0.14%     69.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063          129      0.15%     69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          321      0.37%     69.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575            4      0.00%     69.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13703            1      0.00%     69.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831          137      0.16%     69.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959            1      0.00%     69.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087            5      0.01%     69.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14151            1      0.00%     69.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215            1      0.00%     69.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          386      0.44%     70.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599           64      0.07%     70.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           71      0.08%     70.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           56      0.06%     70.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          386      0.44%     70.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623          121      0.14%     71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15687            1      0.00%     71.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879            5      0.01%     71.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135          125      0.14%     71.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          641      0.74%     72.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16455            1      0.00%     72.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647          125      0.14%     72.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16839            1      0.00%     72.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903            7      0.01%     72.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159          120      0.14%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17223            1      0.00%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          386      0.44%     72.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479            1      0.00%     72.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           54      0.06%     72.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17735            2      0.00%     72.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17863            1      0.00%     72.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           71      0.08%     72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17984-17991            1      0.00%     72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18112-18119            1      0.00%     72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183           65      0.07%     72.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18375            1      0.00%     72.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          384      0.44%     73.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695            5      0.01%     73.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951          132      0.15%     73.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207            6      0.01%     73.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            1      0.00%     73.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          322      0.37%     73.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719          129      0.15%     74.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975          120      0.14%     74.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231           65      0.07%     74.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          442      0.51%     74.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743           64      0.07%     74.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999            1      0.00%     74.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21120-21127            1      0.00%     74.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255          144      0.17%     75.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          377      0.43%     75.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023           65      0.07%     75.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279          131      0.15%     75.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          354      0.41%     76.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791           66      0.08%     76.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919            1      0.00%     76.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047          128      0.15%     76.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           55      0.06%     76.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          261      0.30%     76.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23616-23623            1      0.00%     76.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815          203      0.23%     76.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071            2      0.00%     76.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24256-24263            1      0.00%     76.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           67      0.08%     77.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          495      0.57%     77.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839           66      0.08%     77.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095            2      0.00%     77.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351          204      0.23%     77.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          262      0.30%     78.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           56      0.06%     78.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119          129      0.15%     78.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375           67      0.08%     78.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          355      0.41%     78.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26752-26759            1      0.00%     78.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887          131      0.15%     79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951            1      0.00%     79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27072-27079            1      0.00%     79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143           64      0.07%     79.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27328-27335            2      0.00%     79.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399            3      0.00%     79.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            1      0.00%     79.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          377      0.43%     79.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847            1      0.00%     79.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911          143      0.16%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423           65      0.07%     79.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          441      0.51%     80.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935           65      0.07%     80.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191          119      0.14%     80.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447          128      0.15%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            1      0.00%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          321      0.37%     81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959            6      0.01%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215          134      0.15%     81.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471            4      0.00%     81.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          385      0.44%     81.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983           66      0.08%     81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           71      0.08%     81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31296-31303            2      0.00%     81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           54      0.06%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          385      0.44%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007          120      0.14%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263            4      0.00%     82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519          124      0.14%     82.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          640      0.74%     83.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903            1      0.00%     83.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031          124      0.14%     83.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287            4      0.00%     83.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543          121      0.14%     83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          386      0.44%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           54      0.06%     84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34119            1      0.00%     84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           71      0.08%     84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567           66      0.08%     84.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          384      0.44%     84.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35008-35015            1      0.00%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079            4      0.00%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335          134      0.15%     84.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591            5      0.01%     84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35776-35783            1      0.00%     84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          321      0.37%     85.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103          128      0.15%     85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36224-36231            2      0.00%     85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359          120      0.14%     85.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615           65      0.07%     85.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          441      0.51%     86.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127           64      0.07%     86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383            1      0.00%     86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639          143      0.16%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37760-37767            1      0.00%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37824-37831            1      0.00%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          377      0.43%     86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151            1      0.00%     86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38208-38215            1      0.00%     86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407           64      0.07%     86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38464-38471            1      0.00%     86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663          130      0.15%     87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          355      0.41%     87.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175           66      0.08%     87.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431          128      0.15%     87.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           55      0.06%     87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          261      0.30%     88.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199          203      0.23%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455            1      0.00%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40640-40647            1      0.00%     88.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           66      0.08%     88.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          496      0.57%     88.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223           67      0.08%     89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41280-41287            1      0.00%     89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479            2      0.00%     89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735          203      0.23%     89.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41920-41927            1      0.00%     89.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          260      0.30%     89.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           55      0.06%     89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42304-42311            1      0.00%     89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503          128      0.15%     89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759           67      0.08%     89.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42880-42887            1      0.00%     89.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          353      0.41%     90.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271          131      0.15%     90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527           65      0.07%     90.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          379      0.44%     90.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295          143      0.16%     91.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44352-44359            1      0.00%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423            2      0.00%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807           67      0.08%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44864-44871            1      0.00%     91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          443      0.51%     91.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319           67      0.08%     91.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45440-45447            1      0.00%     91.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575          122      0.14%     91.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45639            1      0.00%     91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703            1      0.00%     91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831          130      0.15%     92.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46016-46023            1      0.00%     92.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          322      0.37%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343            4      0.00%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599          131      0.15%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855            5      0.01%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983            1      0.00%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          384      0.44%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367           64      0.07%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           72      0.08%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47808-47815            1      0.00%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           54      0.06%     93.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          385      0.44%     93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391          121      0.14%     93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48576-48583            1      0.00%     93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647            5      0.01%     93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48832-48839            1      0.00%     93.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903          123      0.14%     93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            2      0.00%     93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            1      0.00%     93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5211      6.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49536-49543            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49856-49863            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50112-50119            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50695            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51008-51015            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51648-51655            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51712-51719            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          86865                       # Bytes accessed per row activation
system.physmem.totQLat                   369784547000                       # Total ticks spent queuing
system.physmem.totMemAccLat              463560559500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76425080000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 17350932500                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24192.62                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1135.16                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30327.78                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         383.56                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.71                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.37                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         1.05                       # Average write queue length when enqueuing
system.physmem.readRowHits                   15213014                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93134                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  86.24                       # Row buffer hit rate for writes
system.physmem.avgGap                       158347.57                       # Average gap between requests
system.physmem.pageHitRate                      99.44                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               2.65                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     54973753                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16346163                       # Transaction distribution
system.membus.trans_dist::ReadResp           16346166                       # Transaction distribution
system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
system.membus.trans_dist::Writeback             59162                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4696                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4696                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131412                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131412                       # Transaction distribution
system.membus.trans_dist::LoadLockedReq             3                       # Transaction distribution
system.membus.trans_dist::StoreCondReq              3                       # Transaction distribution
system.membus.trans_dist::StoreCondResp             3                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383052                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3790                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4272814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34550446                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390470                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16699476                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19097594                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           140208122                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              140208122                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487391000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3584500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17566049500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4736056592                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        34187486731                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    64408                       # number of replacements
system.l2c.tags.tagsinuse                51449.796153                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1905827                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   129798                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    14.683023                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2540137710500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36969.006628                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    22.725284                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000371                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4879.693838                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3326.753767                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.863300                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3332.963946                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2906.789020                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.564102                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000347                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074458                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.050762                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000181                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.050857                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.044354                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.785062                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           22                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65368                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3071                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6835                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55083                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000336                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997437                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18939251                       # Number of tag accesses
system.l2c.tags.data_accesses                18939251                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        33125                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6695                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             507433                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             188763                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        31491                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7375                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             463939                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             198427                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1437248                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          607832                       # number of Writeback hits
system.l2c.Writeback_hits::total               607832                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              21                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  41                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             4                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            60764                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52147                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112911                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         33125                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6695                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              507433                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              249527                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         31491                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7375                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              463939                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              250574                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1550159                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        33125                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6695                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             507433                       # number of overall hits
system.l2c.overall_hits::cpu0.data             249527                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        31491                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7375                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             463939                       # number of overall hits
system.l2c.overall_hits::cpu1.data             250574                       # number of overall hits
system.l2c.overall_hits::total                1550159                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           34                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7770                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6307                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           13                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4624                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4437                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23187                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1611                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1300                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2911                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73970                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          59227                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133197                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           34                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7770                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             80277                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4624                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             63664                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156384                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           34                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7770                       # number of overall misses
system.l2c.overall_misses::cpu0.data            80277                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           13                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4624                       # number of overall misses
system.l2c.overall_misses::cpu1.data            63664                       # number of overall misses
system.l2c.overall_misses::total               156384                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2634500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    564954250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    469111750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1020750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    346930750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    344094500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1728904500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       163993                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       349985                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       513978                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5540139123                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4380452342                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9920591465                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2634500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    564954250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6009250873                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1020750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    346930750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4724546842                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11649495965                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2634500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    564954250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6009250873                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1020750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    346930750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4724546842                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11649495965                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        33159                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6697                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         515203                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         195070                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        31504                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7375                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         468563                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         202864                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1460435                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       607832                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           607832                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1632                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1320                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2952                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       134734                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       111374                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246108                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        33159                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6697                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          515203                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          329804                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        31504                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7375                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          468563                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          314238                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1706543                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        33159                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6697                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         515203                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         329804                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        31504                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7375                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         468563                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         314238                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1706543                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015081                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.032332                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009868                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.021872                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015877                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987132                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.984848                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.986111                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.549008                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.531785                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541214                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015081                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.243408                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009868                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.202598                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.091638                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015081                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.243408                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009868                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.202598                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.091638                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72709.684685                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74379.538608                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75028.276384                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77551.160694                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74563.526976                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   101.795779                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   269.219231                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   176.564067                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74897.108598                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73960.395462                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74480.592393                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72709.684685                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74856.445470                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75028.276384                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74210.650320                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74492.889074                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72709.684685                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74856.445470                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75028.276384                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74210.650320                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74492.889074                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59162                       # number of writebacks
system.l2c.writebacks::total                    59162                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            43                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            21                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             43                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             21                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 79                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            43                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            21                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                79                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7762                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6264                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4617                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4416                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23108                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1611                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1300                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2911                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73970                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        59227                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133197                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           34                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7762                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        80234                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4617                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        63643                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156305                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           34                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7762                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        80234                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4617                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        63643                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156305                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    466747500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    387626500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    288513000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    287574500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1433665250                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16111611                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13003299                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29114910                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4617307377                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3642005658                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8259313035                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    466747500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5004933877                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    288513000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3929580158                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9692978285                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    466747500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5004933877                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    288513000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3929580158                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9692978285                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6162749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83808220000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83134870250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166949252999                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8942555713                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8433790000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17376345713                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       102500                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total       102500                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        60000                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        60000                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6162749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92750775713                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91568660250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184325598712                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.032112                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021768                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015823                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987132                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.984848                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.986111                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.549008                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.531785                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541214                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.243278                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.202531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.091592                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.243278                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.202531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.091592                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61881.625160                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65121.037138                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62041.944348                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.537692                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.686706                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62421.351588                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61492.320361                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62008.251199                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62379.214261                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61744.106312                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62013.232366                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62379.214261                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61744.106312                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62013.232366                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58427801                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2677013                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2677015                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763365                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763365                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           607832                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2952                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2962                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           246108                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          246108                       # Transaction distribution
system.toL2Bus.trans_dist::LoadLockedReq            3                       # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq             3                       # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp            3                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1968942                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5796822                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37990                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       150646                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7954400                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62968576                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85534266                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56288                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       258652                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148817782                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148817782                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          199736                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4962135725                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4435783766                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4484209498                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          23967895                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          86426354                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48423111                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322165                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322165                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8177                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8177                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7932                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          522                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383052                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32660684                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1044                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390470                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123500998                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123500998                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3971000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               522000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374875000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         41493951269                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu0.branchPred.lookups                7524637                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          6008547                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           377377                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4829480                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                3929632                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            81.367601                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 723615                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             39097                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25732063                       # DTB read hits
system.cpu0.dtb.read_misses                     40060                       # DTB read misses
system.cpu0.dtb.write_hits                    6173955                       # DTB write hits
system.cpu0.dtb.write_misses                    10391                       # DTB write misses
system.cpu0.dtb.flush_tlb                         514                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5654                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1384                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   265                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      665                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25772123                       # DTB read accesses
system.cpu0.dtb.write_accesses                6184346                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31906018                       # DTB hits
system.cpu0.dtb.misses                          50451                       # DTB misses
system.cpu0.dtb.accesses                     31956469                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     5897367                       # ITB inst hits
system.cpu0.itb.inst_misses                      7084                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         514                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2660                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1482                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 5904451                       # ITB inst accesses
system.cpu0.itb.hits                          5897367                       # DTB hits
system.cpu0.itb.misses                           7084                       # DTB misses
system.cpu0.itb.accesses                      5904451                       # DTB accesses
system.cpu0.numCycles                       242280954                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          15560897                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      45618983                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7524637                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4653247                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10311307                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2438027                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     82681                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              50295736                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1713                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             2004                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        47904                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1479659                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          328                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  5895435                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               368728                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2960                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          79463748                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.723138                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.071375                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                69159455     87.03%     87.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  678650      0.85%     87.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  874708      1.10%     88.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1176149      1.48%     90.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1117399      1.41%     91.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  558232      0.70%     92.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1283192      1.61%     94.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  380865      0.48%     94.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4235098      5.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            79463748                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031057                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.188290                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16659746                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             51317609                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9233971                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               657554                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1592691                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1005769                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                91409                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              54704033                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               304298                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1592691                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17554490                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               20340792                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27693159                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  8932278                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3348216                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              52126479                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  377                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                497478                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2175969                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             155                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           53794326                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            241736924                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       220533984                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             5031                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             39400219                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14394106                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            593139                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        541531                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6973197                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10037020                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            7000202                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1050357                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1288163                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  48430994                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1028168                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 62176930                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            89712                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9957065                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     24599714                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        276838                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     79463748                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.782457                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.501316                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           56925517     71.64%     71.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7350450      9.25%     80.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3522799      4.43%     85.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2913274      3.67%     88.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6168473      7.76%     96.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1495817      1.88%     98.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             789992      0.99%     99.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             231277      0.29%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              66149      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       79463748                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  30568      0.69%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     2      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4194749     94.30%     94.98% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               223174      5.02%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            15922      0.03%      0.03% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29222200     47.00%     47.02% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               47810      0.08%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  7      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              5      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1242      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26409099     42.47%     89.58% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6480639     10.42%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              62176930                       # Type of FU issued
system.cpu0.iq.rate                          0.256632                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4448493                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.071546                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         208394864                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         59425365                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     43388237                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11204                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6101                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5139                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              66603600                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   5901                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          313863                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2132926                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3897                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        15826                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       851086                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17067174                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       347980                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1592691                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               15703960                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               239689                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           49567887                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           107700                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10037020                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             7000202                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            730031                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 54998                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4795                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         15826                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        184371                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       145167                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              329538                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             61108768                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26079506                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1068162                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       108725                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32501673                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 5985971                       # Number of branches executed
system.cpu0.iew.exec_stores                   6422167                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.252223                       # Inst execution rate
system.cpu0.iew.wb_sent                      60615706                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     43393376                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 23422073                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 43067972                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.179104                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.543840                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        9785974                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         751330                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           287324                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     77871057                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.504327                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.472133                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     63445664     81.48%     81.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7408180      9.51%     90.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1965702      2.52%     93.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1101219      1.41%     94.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       850042      1.09%     96.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       579839      0.74%     96.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       741280      0.95%     97.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       350840      0.45%     98.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1428291      1.83%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     77871057                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            30068673                       # Number of instructions committed
system.cpu0.commit.committedOps              39272492                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14053210                       # Number of memory references committed
system.cpu0.commit.loads                      7904094                       # Number of loads committed
system.cpu0.commit.membars                     209520                       # Number of memory barriers committed
system.cpu0.commit.branches                   5180571                       # Number of branches committed
system.cpu0.commit.fp_insts                      5103                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 34976585                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              508087                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1428291                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   124525442                       # The number of ROB reads
system.cpu0.rob.rob_writes                   99752707                       # The number of ROB writes
system.cpu0.timesIdled                         907289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      162817206                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2250738250                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   29995072                       # Number of Instructions Simulated
system.cpu0.committedOps                     39198891                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             29995072                       # Number of Instructions Simulated
system.cpu0.cpi                              8.077359                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        8.077359                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.123803                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.123803                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               277602258                       # number of integer regfile reads
system.cpu0.int_regfile_writes               44085175                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    44877                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   42488                       # number of floating regfile writes
system.cpu0.misc_regfile_reads              138395505                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                582325                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           984398                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.534546                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           10515921                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           984910                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.677037                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7008829000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   316.868268                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   194.666278                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.618883                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.380208                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999091                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         12566693                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        12566693                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      5337223                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5178698                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       10515921                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5337223                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5178698                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        10515921                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5337223                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5178698                       # number of overall hits
system.cpu0.icache.overall_hits::total       10515921                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       558087                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       507747                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1065834                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       558087                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       507747                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1065834                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       558087                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       507747                       # number of overall misses
system.cpu0.icache.overall_misses::total      1065834                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7713442509                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6842687514                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14556130023                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7713442509                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6842687514                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14556130023                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7713442509                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6842687514                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14556130023                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      5895310                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5686445                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     11581755                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      5895310                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5686445                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     11581755                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      5895310                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5686445                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     11581755                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.094666                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.089291                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092027                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.094666                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.089291                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092027                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.094666                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.089291                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092027                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.218751                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.569067                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.032918                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.218751                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.569067                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13657.032918                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.218751                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.569067                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13657.032918                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         7516                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              400                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.790000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42303                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38592                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        80895                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        42303                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        38592                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        80895                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        42303                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        38592                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        80895                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       515784                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       469155                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       984939                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       515784                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       469155                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       984939                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       515784                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       469155                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       984939                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6271733613                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5566076348                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11837809961                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6271733613                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5566076348                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11837809961                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6271733613                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5566076348                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11837809961                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8638250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8638250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8638250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      8638250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085042                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.085042                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.085042                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12018.825492                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12018.825492                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12018.825492                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           643530                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.993287                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           21531295                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           644042                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            33.431508                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         43200250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   257.568714                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   254.424573                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.503064                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.496923                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          190                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        101651746                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       101651746                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      7028815                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6747590                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13776405                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3755876                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3505333                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7261209                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116971                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       125973                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       242944                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119744                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       127881                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247625                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10784691                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10252923                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21037614                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10784691                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10252923                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21037614                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       339393                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       409028                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       748421                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1648570                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1313214                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2961784                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7529                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5999                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13528                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1987963                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1722242                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3710205                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1987963                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1722242                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3710205                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5452544877                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5973510192                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11426055069                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85021863209                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64469772613                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 149491635822                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    108104498                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79946495                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    188050993                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        78000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        52000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       130000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  90474408086                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  70443282805                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 160917690891                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  90474408086                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  70443282805                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 160917690891                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7368208                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      7156618                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14524826                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5404446                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      4818547                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10222993                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124500                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       131972                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       256472                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119750                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       127885                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247635                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12772654                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     11975165                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24747819                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12772654                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     11975165                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24747819                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.046062                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057154                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051527                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.305040                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.272533                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.289718                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060474                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045457                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052746                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000050                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000031                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000040                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.155642                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.143818                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149920                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.155642                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.143818                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149920                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16065.578480                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14604.159598                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15266.881968                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51573.098630                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49093.120095                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50473.510500                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14358.413866                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13326.636939                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13900.871747                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45511.112675                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40902.081592                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43371.644125                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45511.112675                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40902.081592                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43371.644125                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        36158                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        27990                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3441                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            289                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.507992                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    96.851211                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       607832                       # number of writebacks
system.cpu0.dcache.writebacks::total           607832                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       151038                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       211492                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       362530                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1512262                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1200569                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2712831                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          756                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          622                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1378                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1663300                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1412061                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3075361                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1663300                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1412061                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3075361                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188355                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       197536                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       385891                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       136308                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       112645                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       248953                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6773                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5377                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12150                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       324663                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       310181                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       634844                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       324663                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       310181                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       634844                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2624519460                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2624606109                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5249125569                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6430877605                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5124459707                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11555337312                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     85490752                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61868005                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147358757                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        66000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        44000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       110000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9055397065                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7749065816                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  16804462881                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9055397065                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7749065816                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16804462881                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91527132501                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90809770250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336902751                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13691854278                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13083150967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26775005245                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       141500                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       141500                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        96000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        96000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025563                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027602                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026568                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025221                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023377                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024352                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.054402                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.040743                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047374                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000050                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000031                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025419                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025902                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025653                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025419                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025902                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025653                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                7303181                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5881126                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           346154                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4653929                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3750959                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            80.597684                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 679679                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             34597                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25488049                       # DTB read hits
system.cpu1.dtb.read_misses                     36227                       # DTB read misses
system.cpu1.dtb.write_hits                    5538132                       # DTB write hits
system.cpu1.dtb.write_misses                     8320                       # DTB write misses
system.cpu1.dtb.flush_tlb                         512                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    5495                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1338                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   228                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      677                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25524276                       # DTB read accesses
system.cpu1.dtb.write_accesses                5546452                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         31026181                       # DTB hits
system.cpu1.dtb.misses                          44547                       # DTB misses
system.cpu1.dtb.accesses                     31070728                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     5688452                       # ITB inst hits
system.cpu1.itb.inst_misses                      7006                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         512                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2704                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1448                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 5695458                       # ITB inst accesses
system.cpu1.itb.hits                          5688452                       # DTB hits
system.cpu1.itb.misses                           7006                       # DTB misses
system.cpu1.itb.accesses                      5695458                       # DTB accesses
system.cpu1.numCycles                       236990378                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          14445279                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      45031495                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    7303181                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4430638                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      9912685                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2288075                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     85272                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              49385810                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                1038                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             1883                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        43903                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1235955                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5686448                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               352687                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3068                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          76688585                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.724367                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.076407                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                66784675     87.09%     87.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  633491      0.83%     87.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  843387      1.10%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1127901      1.47%     90.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  993338      1.30%     91.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  549443      0.72%     92.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1277588      1.67%     94.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  369483      0.48%     94.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4109279      5.36%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            76688585                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.030816                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.190014                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                15549027                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             50133952                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  8864377                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               645129                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1493916                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              964413                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                85194                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              52934695                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               283965                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1493916                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                16391230                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               19303163                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      27652687                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8622958                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3222506                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              50466149                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  174                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                593171                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              1994496                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             690                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           52886950                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            233487672                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       213429055                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5328                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             39332432                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13554518                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            579559                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        536966                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6477487                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9753455                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6333018                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           895982                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1122035                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  46958561                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             957421                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 60864798                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            86364                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        9232524                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     23424717                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        226140                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     76688585                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.793662                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.504660                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           54509370     71.08%     71.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            7300848      9.52%     80.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3460717      4.51%     85.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2863086      3.73%     88.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6124123      7.99%     96.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1373475      1.79%     98.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             772006      1.01%     99.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             222325      0.29%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              62635      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       76688585                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  28981      0.66%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     4      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4176523     94.96%     95.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               192832      4.38%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            12596      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             28808168     47.33%     47.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               45770      0.08%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           867      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.43% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            26145062     42.96%     90.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            5852305      9.62%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              60864798                       # Type of FU issued
system.cpu1.iq.rate                          0.256824                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4398340                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.072264                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         202935847                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         57156855                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     42177968                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11410                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6319                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5146                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              65244557                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   5985                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          312441                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2001655                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2943                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        15220                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       749307                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     17042804                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       332523                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1493916                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               14868856                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               223350                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           48029034                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            96518                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9753455                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6333018                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            681732                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 49156                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 5134                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         15220                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        168778                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       134493                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              303271                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             59837987                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25827716                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1026811                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       113052                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31629861                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5852394                       # Number of branches executed
system.cpu1.iew.exec_stores                   5802145                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.252491                       # Inst execution rate
system.cpu1.iew.wb_sent                      59370669                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     42183114                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 23501476                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 42733790                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.177995                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.549951                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        9169088                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         731281                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           262316                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     75194669                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.511793                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.483255                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     60941986     81.05%     81.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      7448338      9.91%     90.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1921902      2.56%     93.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1064941      1.42%     94.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       820613      1.09%     96.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       497482      0.66%     96.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       699016      0.93%     97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       369953      0.49%     98.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1430438      1.90%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     75194669                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            30395180                       # Number of instructions committed
system.cpu1.commit.committedOps              38484098                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13335511                       # Number of memory references committed
system.cpu1.commit.loads                      7751800                       # Number of loads committed
system.cpu1.commit.membars                     194141                       # Number of memory barriers committed
system.cpu1.commit.branches                   5126394                       # Number of branches committed
system.cpu1.commit.fp_insts                      5109                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 34219487                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              483277                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1430438                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   120543738                       # The number of ROB reads
system.cpu1.rob.rob_writes                   96843723                       # The number of ROB writes
system.cpu1.timesIdled                         866392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      160301793                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2319061347                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   30318400                       # Number of Instructions Simulated
system.cpu1.committedOps                     38407318                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             30318400                       # Number of Instructions Simulated
system.cpu1.cpi                              7.816718                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        7.816718                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.127931                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.127931                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               271568545                       # number of integer regfile reads
system.cpu1.int_regfile_writes               43555908                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    45194                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   42320                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              132647791                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                591619                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1518507680269                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83057                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------