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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.627154 # Number of seconds simulated
sim_ticks 2627154206500 # Number of ticks simulated
final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 361221 # Simulator instruction rate (inst/s)
host_op_rate 459651 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15759970234 # Simulator tick rate (ticks/s)
host_mem_usage 398468 # Number of bytes of host memory used
host_seconds 166.70 # Real time elapsed on the host
sim_insts 60214798 # Number of instructions simulated
sim_ops 76622863 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory
system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory
system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15690962 # Total number of read requests seen
system.physmem.writeReqs 811777 # Total number of write requests seen
system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1004221568 # Total number of bytes read from memory
system.physmem.bytesWritten 51953728 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 980142 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 980447 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 986846 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 980559 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 980589 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 980289 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 980613 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 980424 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 979732 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 979654 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 980193 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 980214 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 980246 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 49129 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50872 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51113 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51073 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51327 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51427 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51034 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50441 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 50412 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 50841 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50704 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50889 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 50829 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2627149788000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6680 # Categorize read packet sizes
system.physmem.readPktSize::3 15532032 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 152250 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754038 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 57739 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1134037 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 977508 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1022657 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3835405 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2876027 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2874808 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2829459 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 16845 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 15768 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 28680 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 41555 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 28532 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 2442 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 2410 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2396 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2375 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 35474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35436 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35415 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35397 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35318 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4415 4 0.01% 57.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4543 4 0.01% 57.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation
system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests
system.physmem.totBusLat 78454680000 # Total cycles spent in databus access
system.physmem.totBankLat 16268271250 # Total cycles spent in bank access
system.physmem.avgQLat 19390.48 # Average queueing delay per request
system.physmem.avgBankLat 1036.79 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25427.28 # Average memory access latency
system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 1.26 # Average write queue length over time
system.physmem.readRowHits 15666209 # Number of row buffer hits during reads
system.physmem.writeRowHits 798397 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes
system.physmem.avgGap 159194.77 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54483503 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16743616 # Transaction distribution
system.membus.trans_dist::ReadResp 16743616 # Transaction distribution
system.membus.trans_dist::WriteReq 763392 # Transaction distribution
system.membus.trans_dist::WriteResp 763392 # Transaction distribution
system.membus.trans_dist::Writeback 57739 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 131423 # Transaction distribution
system.membus.trans_dist::ReadExResp 131423 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 143136565 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.l2c.replacements 62136 # number of replacements
system.l2c.tagsinuse 51567.664706 # Cycle average of tags in use
system.l2c.total_refs 1698783 # Total number of references to valid blocks.
system.l2c.sampled_refs 127519 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.321803 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2572304327500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 38171.110682 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000688 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2904.028598 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3024.624697 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 4116.712903 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 3351.186952 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.582445 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.044312 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.046152 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.062816 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.051135 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.786860 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 9922 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3595 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 419412 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 179877 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 9880 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3503 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 425184 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 190638 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1242011 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596576 # number of Writeback hits
system.l2c.Writeback_hits::total 596576 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56638 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 57846 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114484 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9922 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3595 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 419412 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 236515 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 9880 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3503 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 425184 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 248484 # number of demand (read+write) hits
system.l2c.demand_hits::total 1356495 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9922 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3595 # number of overall hits
system.l2c.overall_hits::cpu0.inst 419412 # number of overall hits
system.l2c.overall_hits::cpu0.data 236515 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 9880 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3503 # number of overall hits
system.l2c.overall_hits::cpu1.inst 425184 # number of overall hits
system.l2c.overall_hits::cpu1.data 248484 # number of overall hits
system.l2c.overall_hits::total 1356495 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 4155 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5331 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6437 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4901 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20827 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1388 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1493 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 72239 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 60819 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133058 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 4155 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 77570 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6437 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 65720 # number of demand (read+write) misses
system.l2c.demand_misses::total 153885 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 4155 # number of overall misses
system.l2c.overall_misses::cpu0.data 77570 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6437 # number of overall misses
system.l2c.overall_misses::cpu1.data 65720 # number of overall misses
system.l2c.overall_misses::total 153885 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 285734000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 367265500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 455264500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 352426500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1460902000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 251000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 204500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4643677500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3883247000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8526924500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 285734000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5010943000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 89000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 455264500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4235673500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9987826500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 285734000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5010943000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 89000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 455264500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4235673500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9987826500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9922 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3597 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 423567 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 185208 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 9881 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 3503 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 431621 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 195539 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1262838 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596576 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596576 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1402 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1505 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2907 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 128877 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 118665 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247542 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9922 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3597 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 423567 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 314085 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 9881 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 3503 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 431621 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 314204 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1510380 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9922 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3597 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 423567 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 314085 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 9881 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 3503 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 431621 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 314204 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1510380 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000556 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.009810 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028784 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014914 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025064 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016492 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990014 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992027 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991056 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.560527 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.512527 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.537517 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000556 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.009810 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.246971 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.014914 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.209163 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.101885 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000556 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.009810 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.246971 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.014914 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.209163 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.101885 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68768.712395 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 68892.421684 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70726.192326 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 71909.100184 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 70144.619964 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 180.835735 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 136.972539 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 158.104825 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 64282.139841 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63849.241191 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 64084.267763 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 68768.712395 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 64598.981565 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 70726.192326 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 64450.296713 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 64904.483868 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 68768.712395 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 64598.981565 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 70726.192326 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 64450.296713 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 64904.483868 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 57739 # number of writebacks
system.l2c.writebacks::total 57739 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 4155 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 5331 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6437 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4901 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 20827 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1388 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1493 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2881 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 72239 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 60819 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133058 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 4155 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 77570 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6437 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 65720 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153885 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 4155 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 77570 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6437 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 65720 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153885 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233588500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 301025250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 374548500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291235750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1200571750 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13881388 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14932493 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3735280780 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3118346355 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 6853627135 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 233588500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4036306030 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 374548500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3409582105 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8054198885 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 233588500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4036306030 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 374548500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3409582105 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8054198885 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 339371500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83784654250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82893132500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167017158250 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8360925069 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8338711051 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16699636120 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 339371500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92145579319 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91231843551 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183716794370 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028784 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025064 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990014 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992027 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.560527 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512527 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537517 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101885 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101885 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 56466.938661 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59423.740053 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 57644.968070 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.669792 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51707.260344 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51272.568687 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 51508.568707 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 52848676 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 138672017 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48206783 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution
system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
system.iobus.trans_dist::WriteResp 8167 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 126646653 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7331530 # DTB read hits
system.cpu0.dtb.read_misses 6749 # DTB read misses
system.cpu0.dtb.write_hits 5629181 # DTB write hits
system.cpu0.dtb.write_misses 1838 # DTB write misses
system.cpu0.dtb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7338279 # DTB read accesses
system.cpu0.dtb.write_accesses 5631019 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 12960711 # DTB hits
system.cpu0.dtb.misses 8587 # DTB misses
system.cpu0.dtb.accesses 12969298 # DTB accesses
system.cpu0.itb.inst_hits 29905877 # ITB inst hits
system.cpu0.itb.inst_misses 3541 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2713 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 29909418 # ITB inst accesses
system.cpu0.itb.hits 29905877 # DTB hits
system.cpu0.itb.misses 3541 # DTB misses
system.cpu0.itb.accesses 29909418 # DTB accesses
system.cpu0.numCycles 2625614654 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 29354437 # Number of instructions committed
system.cpu0.committedOps 37594269 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 33819709 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4399 # Number of float alu accesses
system.cpu0.num_func_calls 1050996 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3901744 # number of instructions that are conditional controls
system.cpu0.num_int_insts 33819709 # number of integer instructions
system.cpu0.num_fp_insts 4399 # number of float instructions
system.cpu0.num_int_register_reads 193860060 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written
system.cpu0.num_mem_refs 13528220 # number of memory refs
system.cpu0.num_load_insts 7652095 # Number of load instructions
system.cpu0.num_store_insts 5876125 # Number of store instructions
system.cpu0.num_idle_cycles 3959269974.685009 # Number of idle cycles
system.cpu0.num_busy_cycles -1333655320.685009 # Number of busy cycles
system.cpu0.not_idle_fraction -0.507940 # Percentage of non-idle cycles
system.cpu0.idle_fraction 1.507940 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83030 # number of quiesce instructions executed
system.cpu0.icache.replacements 856296 # number of replacements
system.cpu0.icache.tagsinuse 510.881527 # Cycle average of tags in use
system.cpu0.icache.total_refs 60652091 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 856808 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 70.788428 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 19951126000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 211.269662 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 299.611865 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.412636 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.585179 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.997815 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29481581 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 31170510 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60652091 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29481581 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 31170510 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60652091 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29481581 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 31170510 # number of overall hits
system.cpu0.icache.overall_hits::total 60652091 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 424296 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 432512 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856808 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 424296 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 432512 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856808 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 424296 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 432512 # number of overall misses
system.cpu0.icache.overall_misses::total 856808 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5770416000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6023307000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11793723000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5770416000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6023307000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11793723000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5770416000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6023307000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11793723000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29905877 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 31603022 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61508899 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 29905877 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 31603022 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61508899 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 29905877 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 31603022 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61508899 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013686 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013686 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013686 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.977374 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13926.334992 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13764.720918 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13764.720918 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13764.720918 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 424296 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 432512 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856808 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 424296 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 432512 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856808 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 424296 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 432512 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856808 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4921824000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5158283000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10080107000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4921824000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5158283000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10080107000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4921824000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5158283000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10080107000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 429084500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 429084500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.720918 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 627777 # number of replacements
system.cpu0.dcache.tagsinuse 511.879644 # Cycle average of tags in use
system.cpu0.dcache.total_refs 23662359 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 628289 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 37.661584 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 650252000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 250.372579 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 261.507065 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.489009 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.510756 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999765 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6433193 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6766702 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13199895 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4991648 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4983805 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9975453 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117595 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 118707 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123506 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 124296 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247802 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11424841 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 11750507 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23175348 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11424841 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 11750507 # number of overall hits
system.cpu0.dcache.overall_hits::total 23175348 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 179297 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 189949 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 369246 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 130279 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 120170 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250449 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5911 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5590 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11501 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 309576 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 310119 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 619695 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 309576 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 310119 # number of overall misses
system.cpu0.dcache.overall_misses::total 619695 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2654380500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2776699500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5431080000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5632662000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4856154500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10488816500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 79686500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 80814000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 160500500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8287042500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 7632854000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 15919896500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8287042500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 7632854000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 15919896500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6612490 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6956651 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13569141 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5121927 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5103975 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10225902 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123506 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124297 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247803 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123506 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 124296 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247802 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11734417 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12060626 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23795043 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11734417 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12060626 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23795043 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027115 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027305 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.027212 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025436 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023544 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047860 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044973 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046412 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026382 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025713 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026382 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025713 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14804.377653 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14618.131709 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14708.568272 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43235.379455 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40410.705667 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41880.049431 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13481.052275 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14456.887299 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13955.351709 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25689.890188 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 25689.890188 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 596576 # number of writebacks
system.cpu0.dcache.writebacks::total 596576 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 179297 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 189949 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 369246 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130279 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 120170 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250449 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5911 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11501 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 309576 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 310119 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 619695 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 309576 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 310119 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619695 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295786500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2396801500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4692588000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372104000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4615814500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9987918500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67864500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69634000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137498500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7667890500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7012616000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 14680506500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7667890500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7012616000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 14680506500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527278500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90544684500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182071963000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13203337000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13032051000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235388000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104730615500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103576735500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208307351000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027115 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027305 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025436 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023544 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047860 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044973 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7669515 # DTB read hits
system.cpu1.dtb.read_misses 7262 # DTB read misses
system.cpu1.dtb.write_hits 5604176 # DTB write hits
system.cpu1.dtb.write_misses 1826 # DTB write misses
system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7676777 # DTB read accesses
system.cpu1.dtb.write_accesses 5606002 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 13273691 # DTB hits
system.cpu1.dtb.misses 9088 # DTB misses
system.cpu1.dtb.accesses 13282779 # DTB accesses
system.cpu1.itb.inst_hits 31603022 # ITB inst hits
system.cpu1.itb.inst_misses 3724 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses
system.cpu1.itb.hits 31603022 # DTB hits
system.cpu1.itb.misses 3724 # DTB misses
system.cpu1.itb.accesses 31606746 # DTB accesses
system.cpu1.numCycles 2628693759 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 30860361 # Number of instructions committed
system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses
system.cpu1.num_func_calls 1089512 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls
system.cpu1.num_int_insts 35068610 # number of integer instructions
system.cpu1.num_fp_insts 5870 # number of float instructions
system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read
system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written
system.cpu1.num_mem_refs 13873832 # number of memory refs
system.cpu1.num_load_insts 8013211 # Number of load instructions
system.cpu1.num_store_insts 5860621 # Number of store instructions
system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles
system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles
system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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