path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.626162                       # Number of seconds simulated
sim_ticks                                2626161554000                       # Number of ticks simulated
final_tick                               2626161554000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 476066                       # Simulator instruction rate (inst/s)
host_op_rate                                   568569                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            20761634862                       # Simulator tick rate (ticks/s)
host_mem_usage                                 472496                       # Number of bytes of host memory used
host_seconds                                   126.49                       # Real time elapsed on the host
sim_insts                                    60218144                       # Number of instructions simulated
sim_ops                                      71918894                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           306888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4490328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           399040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4560448                       # Number of bytes read from this memory
system.physmem.bytes_read::total            134013152                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       306888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       399040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          705928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3677952                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1536620                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1479452                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6694024                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             11007                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             70187                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6235                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             71257                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15690721                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57468                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           384155                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           369863                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811486                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47314780                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              116858                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1709845                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              151948                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1736545                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51030049                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         116858                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         151948                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             268806                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1400505                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             585120                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             563351                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2548976                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1400505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47314780                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             116858                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2294965                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             151948                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2299897                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53579025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15690721                       # Number of read requests accepted
system.physmem.writeReqs                       811486                       # Number of write requests accepted
system.physmem.readBursts                    15690721                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     811486                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM               1004205504                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       640                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6711360                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 134013152                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6694024                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       10                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  706602                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4522                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              980414                       # Per bank write bursts
system.physmem.perBankRdBursts::1              980046                       # Per bank write bursts
system.physmem.perBankRdBursts::2              979991                       # Per bank write bursts
system.physmem.perBankRdBursts::3              980262                       # Per bank write bursts
system.physmem.perBankRdBursts::4              986671                       # Per bank write bursts
system.physmem.perBankRdBursts::5              980424                       # Per bank write bursts
system.physmem.perBankRdBursts::6              980568                       # Per bank write bursts
system.physmem.perBankRdBursts::7              980428                       # Per bank write bursts
system.physmem.perBankRdBursts::8              980784                       # Per bank write bursts
system.physmem.perBankRdBursts::9              980432                       # Per bank write bursts
system.physmem.perBankRdBursts::10             979731                       # Per bank write bursts
system.physmem.perBankRdBursts::11             979594                       # Per bank write bursts
system.physmem.perBankRdBursts::12             980346                       # Per bank write bursts
system.physmem.perBankRdBursts::13             980257                       # Per bank write bursts
system.physmem.perBankRdBursts::14             980396                       # Per bank write bursts
system.physmem.perBankRdBursts::15             980367                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6649                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6328                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6318                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6427                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6389                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6673                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6856                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6766                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7040                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6684                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6144                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6041                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6664                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6480                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6708                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6698                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2626157242500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6644                       # Read request sizes (log2)
system.physmem.readPktSize::3                15532042                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  152035                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  57468                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1139192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    982322                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    987642                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1099516                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    997956                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1065450                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2766854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2672571                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3490866                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    121692                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   109210                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   101989                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    98650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    19380                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    18786                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18596                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1040256                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      971.796235                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     905.926694                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     203.945376                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22813      2.19%      2.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22914      2.20%      4.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8969      0.86%      5.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2415      0.23%      5.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2270      0.22%      5.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1819      0.17%      5.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9086      0.87%      6.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          877      0.08%      6.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       969093     93.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1040256                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5997                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2616.425880                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    48628.845120                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535          5973     99.60%     99.60% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-196607            7      0.12%     99.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143            4      0.07%     99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::393216-458751            2      0.03%     99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.12%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5997                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5997                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.486243                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.330739                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.155795                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1                   3      0.05%      0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   3      0.05%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   4      0.07%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   5      0.08%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   8      0.13%      0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6                   1      0.02%      0.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7                   4      0.07%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9                   6      0.10%      0.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10                  3      0.05%      0.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::11                  2      0.03%      0.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12                  3      0.05%      0.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13                  2      0.03%      0.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                 11      0.18%      0.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2055     34.27%     35.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 30      0.50%     35.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3613     60.25%     95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 37      0.62%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 21      0.35%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 16      0.27%     97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 14      0.23%     97.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 18      0.30%     97.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 13      0.22%     97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 29      0.48%     98.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 18      0.30%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 15      0.25%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  9      0.15%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 11      0.18%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                 15      0.25%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 16      0.27%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                 11      0.18%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5997                       # Writes before turning the bus around for reads
system.physmem.totQLat                   404022182250                       # Total ticks spent queuing
system.physmem.totMemAccLat              698223013500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  78453555000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25749.13                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44499.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         382.39                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.03                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.57                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        16.75                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14667428                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     87892                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  83.80                       # Row buffer hit rate for writes
system.physmem.avgGap                       159139.76                       # Average gap between requests
system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2253794386750                       # Time in different power states
system.physmem.memoryStateTime::REF       87693060000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      284666999500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     54492260                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16743274                       # Transaction distribution
system.membus.trans_dist::ReadResp           16743274                       # Transaction distribution
system.membus.trans_dist::WriteReq             763389                       # Transaction distribution
system.membus.trans_dist::WriteResp            763389                       # Transaction distribution
system.membus.trans_dist::Writeback             57468                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4522                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4522                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131560                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131560                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383096                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3860                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1891926                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4278894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               35342958                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390558                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16450920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     18849222                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           143105478                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              143105478                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1225841000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3816000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         18171677500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4988493167                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        38432312250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    61927                       # number of replacements
system.l2c.tags.tagsinuse                50918.981702                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1698761                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   127310                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.343500                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2574018004500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37920.667518                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000701                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2858.981429                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3190.441154                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000187                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4136.744409                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2812.146305                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.578623                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.043625                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.048682                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.063122                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.042910                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.776962                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2167                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6500                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56664                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17277278                       # Number of tag accesses
system.l2c.tags.data_accesses                17277278                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         9702                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3502                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             462087                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             188003                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         9966                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3602                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             382555                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             182697                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1242114                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          596521                       # number of Writeback hits
system.l2c.Writeback_hits::total               596521                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              15                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              11                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            60509                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53980                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               114489                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          9702                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              462087                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              248512                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          9966                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3602                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              382555                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              236677                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1356603                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         9702                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3502                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             462087                       # number of overall hits
system.l2c.overall_hits::cpu0.data             248512                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         9966                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3602                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             382555                       # number of overall hits
system.l2c.overall_hits::cpu1.data             236677                       # number of overall hits
system.l2c.overall_hits::total                1356603                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             4381                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             5534                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6235                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4322                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                20475                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1413                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1464                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2877                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          65455                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          67750                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133205                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              4381                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             70989                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6235                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             72072                       # number of demand (read+write) misses
system.l2c.demand_misses::total                153680                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             4381                       # number of overall misses
system.l2c.overall_misses::cpu0.data            70989                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6235                       # number of overall misses
system.l2c.overall_misses::cpu1.data            72072                       # number of overall misses
system.l2c.overall_misses::total               153680                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    310394250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    412660750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        89250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    435283750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    322856500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1481434000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       232490                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       232990                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4532234420                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4730173185                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9262407605                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    310394250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4944895170                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        89250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    435283750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   5053029685                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     10743841605                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    310394250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4944895170                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        89250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    435283750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   5053029685                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    10743841605                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9702                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3504                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         466468                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         193537                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         9967                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         3602                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         388790                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         187019                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1262589                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       596521                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           596521                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1428                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1475                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2903                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       125964                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       121730                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247694                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9702                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3504                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          466468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          319501                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9967                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         3602                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          388790                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          308749                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1510283                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9702                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3504                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         466468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         319501                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9967                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         3602                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         388790                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         308749                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1510283                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.009392                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.028594                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000100                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.016037                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.023110                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016217                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989496                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992542                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991044                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.519633                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.556560                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.537780                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.009392                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.222187                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000100                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.016037                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.233432                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.101756                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.009392                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.222187                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000100                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.016037                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.233432                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.101756                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70850.091303                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74568.259848                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69812.951083                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74700.717261                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 72353.308913                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   164.536447                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   159.146175                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   161.793535                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69241.989458                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69818.054391                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69534.984460                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 70850.091303                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69657.202806                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 69812.951083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 70110.856990                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69910.473744                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 70850.091303                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69657.202806                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 69812.951083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 70110.856990                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69910.473744                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               57468                       # number of writebacks
system.l2c.writebacks::total                    57468                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         4381                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         5534                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6235                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4322                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           20475                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1413                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1464                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2877                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        65455                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        67750                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133205                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         4381                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        70989                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6235                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        72072                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           153680                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         4381                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        70989                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6235                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        72072                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          153680                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    254926750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    343694250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    356241750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    268891500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1223955500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14131413                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14641964                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     28773377                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3694483580                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3862282315                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7556765895                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    254926750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4038177830                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    356241750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4131173815                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   8780721395                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    254926750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4038177830                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    356241750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4131173815                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   8780721395                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    349507750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83968607250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82715661500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167033776500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8327021074                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8376108487                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16703129561                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    349507750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92295628324                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91091769987                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183736906061                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.028594                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.023110                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016217                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989496                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992542                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991044                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.519633                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.556560                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.537780                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.222187                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.233432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.101756                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009392                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.222187                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000100                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.016037                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.233432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.101756                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62105.936032                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62214.599722                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 59778.046398                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.341530                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.173792                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56443.107173                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57007.857048                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56730.347172                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56884.557185                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57320.094003                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57136.396376                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58189.169139                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56884.557185                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57135.805934                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57320.094003                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57136.396376                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    52868072                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2471434                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2471434                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763389                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763389                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           596521                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2903                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2903                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           247694                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          247694                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725408                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753877                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20010                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        49988                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7549283                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54763036                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83799850                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        78676                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          138669986                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             138669986                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          170112                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4808749000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3866196743                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4420580083                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          12904000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          30319250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48225066                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16715396                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16715396                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8184                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8184                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          536                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383096                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                33447160                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15896                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2088                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            126646814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               126646814                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3979000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               536000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               528000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15532032000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374912000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         39164946750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     6652404                       # DTB read hits
system.cpu0.dtb.read_misses                      6867                       # DTB read misses
system.cpu0.dtb.write_hits                    5702862                       # DTB write hits
system.cpu0.dtb.write_misses                     1758                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2489                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                727                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    6327                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   129                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      214                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 6659271                       # DTB read accesses
system.cpu0.dtb.write_accesses                5704620                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12355266                       # DTB hits
system.cpu0.dtb.misses                           8625                       # DTB misses
system.cpu0.dtb.accesses                     12363891                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    30639417                       # ITB inst hits
system.cpu0.itb.inst_misses                      3605                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2489                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                727                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     33                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2770                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                30643022                       # ITB inst accesses
system.cpu0.itb.hits                         30639417                       # DTB hits
system.cpu0.itb.misses                           3605                       # DTB misses
system.cpu0.itb.accesses                     30643022                       # DTB accesses
system.cpu0.numCycles                      2625139831                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   30062808                       # Number of instructions committed
system.cpu0.committedOps                     36081752                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             32258130                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5851                       # Number of float alu accesses
system.cpu0.num_func_calls                    1105626                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3807715                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    32258130                       # number of integer instructions
system.cpu0.num_fp_insts                         5851                       # number of float instructions
system.cpu0.num_int_register_reads           58404320                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          21560333                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4184                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1670                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           129650201                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           14353458                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     12793226                       # number of memory refs
system.cpu0.num_load_insts                    6826552                       # Number of load instructions
system.cpu0.num_store_insts                   5966674                       # Number of store instructions
system.cpu0.num_idle_cycles              2291568668.895058                       # Number of idle cycles
system.cpu0.num_busy_cycles              333571162.104942                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.127068                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.872932                       # Percentage of idle cycles
system.cpu0.Branches                          5192489                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                12678      0.03%      0.03% # Class of executed instruction
system.cpu0.op_class::IntAlu                 23764768     64.90%     64.94% # Class of executed instruction
system.cpu0.op_class::IntMult                   45316      0.12%     65.06% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              1041      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.06% # Class of executed instruction
system.cpu0.op_class::MemRead                 6826552     18.64%     83.71% # Class of executed instruction
system.cpu0.op_class::MemWrite                5966674     16.29%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  36617029                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83036                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           856376                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.872089                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           60655440                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           856888                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            70.785727                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      19833794250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   155.467241                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   355.404848                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.303647                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.694150                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997797                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          268                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         62369216                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        62369216                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     30172107                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     30483333                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       60655440                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     30172107                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     30483333                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        60655440                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     30172107                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     30483333                       # number of overall hits
system.cpu0.icache.overall_hits::total       60655440                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       467310                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       389578                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       856888                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       467310                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       389578                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        856888                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       467310                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       389578                       # number of overall misses
system.cpu0.icache.overall_misses::total       856888                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6355213744                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   5449642249                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11804855993                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   6355213744                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   5449642249                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11804855993                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   6355213744                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   5449642249                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11804855993                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     30639417                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     30872911                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     61512328                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     30639417                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     30872911                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     61512328                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     30639417                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     30872911                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     61512328                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015252                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.012619                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.013930                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015252                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.012619                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.013930                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015252                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.012619                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.013930                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.567191                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.578023                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.428183                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.567191                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.578023                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13776.428183                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.567191                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.578023                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13776.428183                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       467310                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       389578                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       856888                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       467310                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       389578                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       856888                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       467310                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       389578                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       856888                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5418947256                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   4668092751                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10087040007                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5418947256                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   4668092751                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10087040007                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5418947256                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   4668092751                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10087040007                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    440846250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    440846250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    440846250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    440846250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015252                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012619                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013930                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015252                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.012619                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.013930                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015252                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.012619                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.013930                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.713464                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.713464                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.043860                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11982.434201                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.713464                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           627738                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.876206                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           21798920                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           628250                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            34.697843                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        668864250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   154.066297                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   357.809909                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.300911                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.698847                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999758                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         90464778                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        90464778                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5681092                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      5575113                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11256205                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5059212                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      4912213                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9971425                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        43677                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        40519                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        84196                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       123460                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       112914                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       236374                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       129861                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       117956                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247817                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10740304                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10487326                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21227630                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10783981                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10527845                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21311826                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       148158                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       147905                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       296063                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       129911                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       125509                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       255420                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        52745                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        47443                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       100188                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6399                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5045                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11444                       # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data       278069                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       273414                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        551483                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       330814                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       320857                       # number of overall misses
system.cpu0.dcache.overall_misses::total       651671                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2069842250                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2010175249                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4080017499                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5698764993                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5806816529                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  11505581522                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     85596250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     73843500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    159439750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   7768607243                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   7816991778                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  15585599021                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   7768607243                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   7816991778                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  15585599021                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5829250                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      5723018                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     11552268                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5189123                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5037722                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10226845                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        96422                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        87962                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       184384                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       129859                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       117959                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       247818                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       129861                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       117956                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247817                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11018373                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     10760740                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21779113                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11114795                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     10848702                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21963497                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025416                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.025844                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.025628                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025035                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024914                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.024975                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.547022                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.539358                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.543366                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.049277                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.042769                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046179                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025237                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025408                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.025322                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029763                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029576                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029671                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13970.506149                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.989142                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.909803                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43866.685600                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 46266.136524                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45045.734563                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.504141                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14636.967294                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13932.169696                       # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27937.696194                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28590.312778                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 28261.250158                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23483.308575                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24362.852542                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23916.361202                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       596521                       # number of writebacks
system.cpu0.dcache.writebacks::total           596521                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          239                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          285                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          524                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         2519                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         2304                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total         4823                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data         2758                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         2589                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total         5347                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data         2758                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         2589                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total         5347                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       147919                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       147620                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       295539                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       127392                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       123205                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       250597                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        39219                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        34354                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        73573                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6399                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5045                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11444                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       275311                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       270825                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       546136                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       314530                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       305179                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       619709                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1770558000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1711285000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3481843000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5304830507                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5433667721                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10738498228                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    656374250                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    573183000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1229557250                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72793750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63702500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136496250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7075388507                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7144952721                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  14220341228                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7731762757                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7718135721                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  15449898478                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91728534250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90349964750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078499000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13171576426                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13067690513                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26239266939                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104900110676                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103417655263                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317765939                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025375                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025794                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.025583                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024550                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024456                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024504                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.406743                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.390555                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.399021                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.049277                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.042769                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046179                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024987                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025168                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025076                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028298                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028130                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028215                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.780758                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.501016                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11781.331736                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41641.786823                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44102.655907                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42851.663140                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16736.129172                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16684.607324                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16712.071684                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.800906                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12626.858276                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11927.319993                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25699.621544                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26382.175652                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26038.095324                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24581.956433                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.520386                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24930.892529                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     6516178                       # DTB read hits
system.cpu1.dtb.read_misses                      7066                       # DTB read misses
system.cpu1.dtb.write_hits                    5531450                       # DTB write hits
system.cpu1.dtb.write_misses                     1844                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2489                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                712                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    6501                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   152                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      238                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 6523244                       # DTB read accesses
system.cpu1.dtb.write_accesses                5533294                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         12047628                       # DTB hits
system.cpu1.dtb.misses                           8910                       # DTB misses
system.cpu1.dtb.accesses                     12056538                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    30872911                       # ITB inst hits
system.cpu1.itb.inst_misses                      3673                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2489                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                712                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2794                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                30876584                       # ITB inst accesses
system.cpu1.itb.hits                         30872911                       # DTB hits
system.cpu1.itb.misses                           3673                       # DTB misses
system.cpu1.itb.accesses                     30876584                       # DTB accesses
system.cpu1.numCycles                      2627183277                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   30155336                       # Number of instructions committed
system.cpu1.committedOps                     35837142                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             32021976                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  4418                       # Number of float alu accesses
system.cpu1.num_func_calls                    1035067                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3744201                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    32021976                       # number of integer instructions
system.cpu1.num_fp_insts                         4418                       # number of float instructions
system.cpu1.num_int_register_reads           57765753                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          21325005                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                3309                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1110                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           128250854                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           14653287                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     12466012                       # number of memory refs
system.cpu1.num_load_insts                    6694911                       # Number of load instructions
system.cpu1.num_store_insts                   5771101                       # Number of store instructions
system.cpu1.num_idle_cycles              2287259017.662607                       # Number of idle cycles
system.cpu1.num_busy_cycles              339924259.337393                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.129387                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.870613                       # Percentage of idle cycles
system.cpu1.Branches                          5118153                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                15840      0.04%      0.04% # Class of executed instruction
system.cpu1.op_class::IntAlu                 23832212     65.55%     65.59% # Class of executed instruction
system.cpu1.op_class::IntMult                   42672      0.12%     65.71% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              1070      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.71% # Class of executed instruction
system.cpu1.op_class::MemRead                 6694911     18.41%     84.13% # Class of executed instruction
system.cpu1.op_class::MemWrite                5771101     15.87%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  36357806                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1781125703750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------