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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.630640 # Number of seconds simulated
sim_ticks 2630640106500 # Number of ticks simulated
final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 544255 # Simulator instruction rate (inst/s)
host_op_rate 692557 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23778611565 # Simulator tick rate (ticks/s)
host_mem_usage 394548 # Number of bytes of host memory used
host_seconds 110.63 # Real time elapsed on the host
sim_insts 60211209 # Number of instructions simulated
sim_ops 76617916 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory
system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory
system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 1004216768 # Total number of bytes read from memory
system.physmem.bytesWritten 51949056 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2630635687000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6680 # Categorize read packet sizes
system.physmem.readPktSize::3 15532032 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 152175 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754038 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 57666 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation
system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests
system.physmem.totBusLat 78454290000 # Total cycles spent in databus access
system.physmem.totBankLat 16228107500 # Total cycles spent in bank access
system.physmem.avgQLat 19121.93 # Average queueing delay per request
system.physmem.avgBankLat 1034.24 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25156.17 # Average memory access latency
system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 1.25 # Average write queue length over time
system.physmem.readRowHits 15666199 # Number of row buffer hits during reads
system.physmem.writeRowHits 93719 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes
system.physmem.avgGap 159407.43 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54407704 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16743613 # Transaction distribution
system.membus.trans_dist::ReadResp 16743613 # Transaction distribution
system.membus.trans_dist::WriteReq 763392 # Transaction distribution
system.membus.trans_dist::WriteResp 763392 # Transaction distribution
system.membus.trans_dist::Writeback 57666 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution
system.membus.trans_dist::ReadExReq 131350 # Transaction distribution
system.membus.trans_dist::ReadExResp 131350 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 143127089 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.l2c.tags.replacements 62061 # number of replacements
system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use
system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits
system.l2c.Writeback_hits::total 596358 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits
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system.l2c.overall_hits::cpu1.data 239916 # number of overall hits
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system.l2c.UpgradeReq_misses::cpu0.data 1446 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1435 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses
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system.l2c.overall_misses::cpu1.inst 6154 # number of overall misses
system.l2c.overall_misses::cpu1.data 67880 # number of overall misses
system.l2c.overall_misses::total 153816 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 307218750 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::cpu1.data 347894250 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::total 8517839109 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu1.inst 431930250 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.inst 431930250 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu1.dtb.walker 9920 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 3623 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 413983 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 189985 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1262694 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596358 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596358 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1464 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2907 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.010063 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028223 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014865 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025539 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987705 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994456 # miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 162.362369 # average UpgradeReq miss latency
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system.l2c.demand_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency
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system.l2c.ReadReq_mshr_miss_latency::cpu1.data 286200750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1192468500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14461446 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14352435 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3602203602 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3248593789 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 6850797391 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 251180750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3902887102 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 354229750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3534794539 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8043265891 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 251180750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3902887102 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 354229750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3534794539 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8043265891 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 322980250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84062460250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82598359000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166983799500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8379652001 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8320086501 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16699738502 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 322980250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92442112251 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90918445501 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183683538002 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028223 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025539 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016493 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987705 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994456 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.539451 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534992 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537329 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101852 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101852 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 55909.910747 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58986.139736 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 57261.392557 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.696864 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51487.266155 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51542.073190 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 51513.240678 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 52764048 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 138632553 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48142902 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution
system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
system.iobus.trans_dist::WriteResp 8167 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 126646649 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7542817 # DTB read hits
system.cpu0.dtb.read_misses 7082 # DTB read misses
system.cpu0.dtb.write_hits 5717425 # DTB write hits
system.cpu0.dtb.write_misses 1778 # DTB write misses
system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7549899 # DTB read accesses
system.cpu0.dtb.write_accesses 5719203 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 13260242 # DTB hits
system.cpu0.dtb.misses 8860 # DTB misses
system.cpu0.dtb.accesses 13269102 # DTB accesses
system.cpu0.itb.inst_hits 30610477 # ITB inst hits
system.cpu0.itb.inst_misses 3712 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses
system.cpu0.itb.hits 30610477 # DTB hits
system.cpu0.itb.misses 3712 # DTB misses
system.cpu0.itb.accesses 30614189 # DTB accesses
system.cpu0.numCycles 2629428479 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 30009354 # Number of instructions committed
system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses
system.cpu0.num_func_calls 1080838 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34511671 # number of integer instructions
system.cpu0.num_fp_insts 5157 # number of float instructions
system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written
system.cpu0.num_mem_refs 13842126 # number of memory refs
system.cpu0.num_load_insts 7871888 # Number of load instructions
system.cpu0.num_store_insts 5970238 # Number of store instructions
system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles
system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles
system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 856130 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.884273 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60648659 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 856642 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 70.798139 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 19947189250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.188035 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.696238 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410524 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587297 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 30168630 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 30480029 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60648659 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30168630 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 30480029 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60648659 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30168630 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 30480029 # number of overall hits
system.cpu0.icache.overall_hits::total 60648659 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 441847 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 414795 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856642 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 441847 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 414795 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856642 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 441847 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 414795 # number of overall misses
system.cpu0.icache.overall_misses::total 856642 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6019417250 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5775014750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11794432000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6019417250 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 5775014750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11794432000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6019417250 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 5775014750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11794432000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610477 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894824 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61505301 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30610477 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 30894824 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61505301 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30610477 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 30894824 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61505301 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014435 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013426 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014435 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013426 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014435 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013426 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13623.306823 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13922.575610 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13768.215894 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13768.215894 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13768.215894 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 441847 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 414795 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856642 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 441847 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 414795 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856642 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 441847 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 414795 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856642 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5133544750 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4942408250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075953000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5133544750 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4942408250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10075953000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5133544750 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4942408250 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10075953000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 414413750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 414413750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11762.151517 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 627532 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.881676 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23660522 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 628044 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.673351 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 640880250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.734555 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.147121 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.356903 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642865 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999769 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6634061 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6564802 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13198863 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5075609 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4899184 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9974793 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120623 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 115578 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236201 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126785 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120973 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247758 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11709670 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 11463986 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23173656 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11709670 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 11463986 # number of overall hits
system.cpu0.dcache.overall_hits::total 23173656 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 184394 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 184588 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 368982 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 131157 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 119254 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250411 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6161 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5397 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11558 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 315551 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 303842 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 315551 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 303842 # number of overall misses
system.cpu0.dcache.overall_misses::total 619393 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725468500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705402500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5430871000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5537493548 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5008087224 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10545580772 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82157000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77679750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 159836750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13567845 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206766 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5018438 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10225204 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126784 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120975 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126785 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120973 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048594 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044613 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046650 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026241 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025820 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026241 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025820 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14780.678872 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks
system.cpu0.dcache.writebacks::total 596358 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7456887 # DTB read hits
system.cpu1.dtb.read_misses 7096 # DTB read misses
system.cpu1.dtb.write_hits 5515190 # DTB write hits
system.cpu1.dtb.write_misses 1853 # DTB write misses
system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7463983 # DTB read accesses
system.cpu1.dtb.write_accesses 5517043 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 12972077 # DTB hits
system.cpu1.dtb.misses 8949 # DTB misses
system.cpu1.dtb.accesses 12981026 # DTB accesses
system.cpu1.itb.inst_hits 30894824 # ITB inst hits
system.cpu1.itb.inst_misses 3669 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses
system.cpu1.itb.hits 30894824 # DTB hits
system.cpu1.itb.misses 3669 # DTB misses
system.cpu1.itb.accesses 30898493 # DTB accesses
system.cpu1.numCycles 2631851734 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 30201855 # Number of instructions committed
system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses
system.cpu1.num_func_calls 1059508 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls
system.cpu1.num_int_insts 34372038 # number of integer instructions
system.cpu1.num_fp_insts 5112 # number of float instructions
system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read
system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written
system.cpu1.num_mem_refs 13557754 # number of memory refs
system.cpu1.num_load_insts 7792008 # Number of load instructions
system.cpu1.num_store_insts 5765746 # Number of store instructions
system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles
system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles
system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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