blob: b41d3a6bf5b347ac56ae2041fd64a337d181282a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.629734 # Number of seconds simulated
sim_ticks 2629733911500 # Number of ticks simulated
final_tick 2629733911500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 461706 # Simulator instruction rate (inst/s)
host_op_rate 587514 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20164609948 # Simulator tick rate (ticks/s)
host_mem_usage 422284 # Number of bytes of host memory used
host_seconds 130.41 # Real time elapsed on the host
sim_insts 60212552 # Number of instructions simulated
sim_ops 76619667 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 300040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4644312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 404420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4416276 # Number of bytes read from this memory
system.physmem.bytes_read::total 134021496 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 300040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 404420 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3689920 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1526984 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1489296 # Number of bytes written to this memory
system.physmem.bytes_written::total 6706200 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 10900 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 72603 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6335 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 69039 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690912 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57655 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 381746 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 372324 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811725 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47250505 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 114095 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1766077 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 153787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1679362 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50963900 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 114095 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 153787 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 267883 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1403153 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 580661 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 566330 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2550144 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1403153 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47250505 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 114095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2346738 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 153787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2245692 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53514044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15690912 # Number of read requests accepted
system.physmem.writeReqs 811725 # Number of write requests accepted
system.physmem.readBursts 15690912 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 811725 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1004216512 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue
system.physmem.bytesWritten 6837440 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 134021496 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6706200 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 704890 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 980392 # Per bank write bursts
system.physmem.perBankRdBursts::1 980205 # Per bank write bursts
system.physmem.perBankRdBursts::2 980222 # Per bank write bursts
system.physmem.perBankRdBursts::3 980431 # Per bank write bursts
system.physmem.perBankRdBursts::4 986950 # Per bank write bursts
system.physmem.perBankRdBursts::5 980708 # Per bank write bursts
system.physmem.perBankRdBursts::6 980610 # Per bank write bursts
system.physmem.perBankRdBursts::7 980424 # Per bank write bursts
system.physmem.perBankRdBursts::8 980615 # Per bank write bursts
system.physmem.perBankRdBursts::9 980431 # Per bank write bursts
system.physmem.perBankRdBursts::10 979815 # Per bank write bursts
system.physmem.perBankRdBursts::11 979558 # Per bank write bursts
system.physmem.perBankRdBursts::12 980153 # Per bank write bursts
system.physmem.perBankRdBursts::13 980093 # Per bank write bursts
system.physmem.perBankRdBursts::14 980167 # Per bank write bursts
system.physmem.perBankRdBursts::15 980109 # Per bank write bursts
system.physmem.perBankWrBursts::0 6735 # Per bank write bursts
system.physmem.perBankWrBursts::1 6596 # Per bank write bursts
system.physmem.perBankWrBursts::2 6612 # Per bank write bursts
system.physmem.perBankWrBursts::3 6671 # Per bank write bursts
system.physmem.perBankWrBursts::4 6747 # Per bank write bursts
system.physmem.perBankWrBursts::5 7052 # Per bank write bursts
system.physmem.perBankWrBursts::6 7031 # Per bank write bursts
system.physmem.perBankWrBursts::7 6880 # Per bank write bursts
system.physmem.perBankWrBursts::8 6999 # Per bank write bursts
system.physmem.perBankWrBursts::9 6828 # Per bank write bursts
system.physmem.perBankWrBursts::10 6320 # Per bank write bursts
system.physmem.perBankWrBursts::11 6125 # Per bank write bursts
system.physmem.perBankWrBursts::12 6609 # Per bank write bursts
system.physmem.perBankWrBursts::13 6397 # Per bank write bursts
system.physmem.perBankWrBursts::14 6618 # Per bank write bursts
system.physmem.perBankWrBursts::15 6615 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2629729480000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6718 # Read request sizes (log2)
system.physmem.readPktSize::3 15532032 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 152162 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754070 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 57655 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1274921 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1118631 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1118848 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3789956 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2706257 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2705513 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2723130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 52826 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 57874 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 20456 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 5032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4917 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4877 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4860 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 90412 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 11182.734327 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 1029.544171 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 16746.961445 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 23519 26.01% 26.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 14711 16.27% 42.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 2935 3.25% 45.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 2119 2.34% 47.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 1367 1.51% 49.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 1185 1.31% 50.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 943 1.04% 51.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 1073 1.19% 52.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 614 0.68% 53.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 515 0.57% 54.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 541 0.60% 54.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 575 0.64% 55.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 297 0.33% 55.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 299 0.33% 56.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 230 0.25% 56.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 594 0.66% 56.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 170 0.19% 57.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 148 0.16% 57.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 128 0.14% 57.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 277 0.31% 57.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 134 0.15% 57.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 229 0.25% 60.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 52 0.06% 60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 35 0.04% 60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 49 0.05% 60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 107 0.12% 61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 29 0.03% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 27 0.03% 61.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 349 0.39% 61.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 23 0.03% 61.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 21 0.02% 61.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 26 0.03% 61.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 89 0.10% 61.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 16 0.02% 61.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 22 0.02% 61.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 22 0.02% 61.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 90 0.10% 61.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 13 0.01% 61.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 21 0.02% 61.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 65 0.07% 61.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 15 0.02% 62.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015 14 0.02% 62.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079 339 0.37% 62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 16 0.02% 62.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 12 0.01% 62.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 10 0.01% 62.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 148 0.16% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 16 0.02% 62.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 11 0.01% 62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 13 0.01% 62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 37 0.04% 62.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 139 0.15% 63.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 14 0.02% 63.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 9 0.01% 63.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 13 0.01% 63.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 357 0.39% 63.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 6 0.01% 63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 7 0.01% 63.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 77 0.09% 63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 8 0.01% 63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 79 0.09% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 9 0.01% 63.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 6 0.01% 63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 18 0.02% 63.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 10 0.01% 63.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 276 0.31% 64.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255 9 0.01% 64.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 76 0.08% 64.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 164 0.18% 64.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 301 0.33% 64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 456 0.50% 65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 69 0.08% 65.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 268 0.30% 65.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199 512 0.57% 66.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 67 0.07% 66.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 266 0.29% 67.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 72 0.08% 67.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 456 0.50% 67.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 301 0.33% 68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 64 0.07% 68.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 271 0.30% 68.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 341 0.38% 69.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 322 0.36% 70.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 126 0.14% 70.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 74 0.08% 71.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 66 0.07% 71.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 390 0.43% 72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 127 0.14% 73.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 68 0.08% 73.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 58 0.06% 73.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 323 0.36% 74.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 345 0.38% 75.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 68 0.08% 75.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 71 0.08% 75.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 5 0.01% 75.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 267 0.30% 75.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 302 0.33% 75.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 456 0.50% 76.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 69 0.08% 76.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 131 0.14% 77.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 514 0.57% 77.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 67 0.07% 78.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 262 0.29% 78.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 69 0.08% 78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 455 0.50% 79.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 301 0.33% 79.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 64 0.07% 79.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847 1 0.00% 80.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 341 0.38% 80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 132 0.15% 80.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 67 0.07% 82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 72 0.08% 83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 386 0.43% 84.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 125 0.14% 84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 321 0.36% 84.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 131 0.14% 85.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 340 0.38% 86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 64 0.07% 86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 301 0.33% 87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 455 0.50% 87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 69 0.08% 87.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 262 0.29% 88.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 67 0.07% 88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 66 0.07% 88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 514 0.57% 89.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 129 0.14% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 69 0.08% 89.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 456 0.50% 90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 302 0.33% 90.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 267 0.30% 91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 5 0.01% 91.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 68 0.08% 91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 341 0.38% 91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 129 0.14% 91.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 131 0.14% 92.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 321 0.36% 92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343 57 0.06% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 74 0.08% 92.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 69 0.08% 92.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 320 0.35% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 72 0.08% 93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 142 0.16% 93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 391 0.43% 93.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 73 0.08% 94.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647 1 0.00% 94.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 5357 5.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90412 # Bytes accessed per row activation
system.physmem.totQLat 377428295750 # Total ticks spent queuing
system.physmem.totMemAccLat 474604408250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 78454415000 # Total ticks spent in databus transfers
system.physmem.totBankLat 18721697500 # Total ticks spent accessing banks
system.physmem.avgQLat 24053.99 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1193.16 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30247.14 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.00 # Data bus utilization in percentage
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing
system.physmem.readRowHits 15616374 # Number of row buffer hits during reads
system.physmem.writeRowHits 90932 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes
system.physmem.avgGap 159352.08 # Average gap between requests
system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54425977 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16743649 # Transaction distribution
system.membus.trans_dist::ReadResp 16743649 # Transaction distribution
system.membus.trans_dist::WriteReq 763424 # Transaction distribution
system.membus.trans_dist::WriteResp 763424 # Transaction distribution
system.membus.trans_dist::Writeback 57655 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 131340 # Transaction distribution
system.membus.trans_dist::ReadExResp 131340 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892587 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4279449 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 35343513 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471440 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 18869581 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 143125837 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 143125837 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1225677000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3756500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 18171612500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4990561725 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 35076949500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 62045 # number of replacements
system.l2c.tags.tagsinuse 51605.891965 # Cycle average of tags in use
system.l2c.tags.total_refs 1699472 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127428 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.336723 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2574797983500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 38210.959857 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2799.685375 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3087.560110 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4221.092196 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3286.593539 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.583053 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.042720 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.047112 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.064409 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.050149 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17277894 # Number of tag accesses
system.l2c.tags.data_accesses 17277894 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9810 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 412170 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 183158 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 10090 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 432364 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 187312 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1242106 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596455 # number of Writeback hits
system.l2c.Writeback_hits::total 596455 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57198 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 57329 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114527 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9810 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 412170 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 240356 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 10090 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3595 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 432364 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 244641 # number of demand (read+write) hits
system.l2c.demand_hits::total 1356633 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9810 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits
system.l2c.overall_hits::cpu0.inst 412170 # number of overall hits
system.l2c.overall_hits::cpu0.data 240356 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 10090 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3595 # number of overall hits
system.l2c.overall_hits::cpu1.inst 432364 # number of overall hits
system.l2c.overall_hits::cpu1.data 244641 # number of overall hits
system.l2c.overall_hits::total 1356633 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 4274 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5319 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6318 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4908 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20822 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1344 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1536 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2880 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 68023 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 64953 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 4274 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 73342 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6318 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 69861 # number of demand (read+write) misses
system.l2c.demand_misses::total 153798 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 4274 # number of overall misses
system.l2c.overall_misses::cpu0.data 73342 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6318 # number of overall misses
system.l2c.overall_misses::cpu1.data 69861 # number of overall misses
system.l2c.overall_misses::total 153798 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 306924500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 393478000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 451089750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 373371500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1525102500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 232990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 231990 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 464980 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4852191723 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4623461391 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9475653114 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 306924500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5245669723 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 451089750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4996832891 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11000755614 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 306924500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5245669723 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 451089750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4996832891 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11000755614 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9810 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3609 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 416444 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 188477 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 10091 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 3595 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 438682 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 192220 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1262928 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596455 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596455 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1357 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1549 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2906 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 125221 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 122282 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247503 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9810 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3609 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 416444 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 313698 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 10091 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 3595 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 438682 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 314502 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1510431 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9810 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3609 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 416444 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 313698 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 10091 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 3595 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 438682 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 314502 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1510431 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000554 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.010263 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028221 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014402 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025533 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016487 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990420 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991607 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991053 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.543224 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.531174 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.537270 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000554 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.010263 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.233798 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.014402 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.222132 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.101824 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000554 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.010263 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.233798 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.014402 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.222132 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.101824 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71812.002808 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73975.935326 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71397.554606 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76074.062755 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73244.765152 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 173.355655 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 151.035156 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 161.451389 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71331.633756 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71181.645051 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 71258.370789 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 71812.002808 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 71523.407093 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71397.554606 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71525.355935 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71527.299536 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 71812.002808 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 71523.407093 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71397.554606 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71525.355935 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71527.299536 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 57655 # number of writebacks
system.l2c.writebacks::total 57655 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 4274 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 5319 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6318 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4908 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 20822 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1344 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1536 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2880 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 68023 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 64953 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 132976 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 4274 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 73342 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6318 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 69861 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153798 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 4274 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 73342 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6318 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 69861 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153798 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 252789500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327242500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370964750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312158000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1263356000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13441344 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15361536 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28802880 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3980747277 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3790800609 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7771547886 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 252789500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4307989777 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 370964750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4102958609 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 9034903886 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 252789500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4307989777 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 370964750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4102958609 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 9034903886 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344358750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83697263750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82980883500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167023348500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8440281008 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8259993501 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16700274509 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344358750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92137544758 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91240877001 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183723623009 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028221 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025533 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990420 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991607 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991053 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543224 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.531174 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537270 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101824 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101824 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61523.312653 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63601.874491 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60674.094708 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58520.607397 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58362.209736 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58443.237020 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 52790764 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2471959 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2471959 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 596455 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 247503 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 247503 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725165 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753809 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50570 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7549803 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754656 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83792621 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79604 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 138655697 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 138655697 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4808655500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3865656500 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4421145525 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 30669250 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48159493 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution
system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
system.iobus.trans_dist::WriteResp 8167 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 126646653 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42582472500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7421892 # DTB read hits
system.cpu0.dtb.read_misses 6825 # DTB read misses
system.cpu0.dtb.write_hits 5624028 # DTB write hits
system.cpu0.dtb.write_misses 1832 # DTB write misses
system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6408 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7428717 # DTB read accesses
system.cpu0.dtb.write_accesses 5625860 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 13045920 # DTB hits
system.cpu0.dtb.misses 8657 # DTB misses
system.cpu0.dtb.accesses 13054577 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 30611798 # ITB inst hits
system.cpu0.itb.inst_misses 3559 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 30615357 # ITB inst accesses
system.cpu0.itb.hits 30611798 # DTB hits
system.cpu0.itb.misses 3559 # DTB misses
system.cpu0.itb.accesses 30615357 # DTB accesses
system.cpu0.numCycles 2628262709 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 29989968 # Number of instructions committed
system.cpu0.committedOps 38153430 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34435324 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses
system.cpu0.num_func_calls 1060090 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3967783 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34435324 # number of integer instructions
system.cpu0.num_fp_insts 4807 # number of float instructions
system.cpu0.num_int_register_reads 199674548 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37122022 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3633 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1176 # number of times the floating registers were written
system.cpu0.num_mem_refs 13619078 # number of memory refs
system.cpu0.num_load_insts 7744657 # Number of load instructions
system.cpu0.num_store_insts 5874421 # Number of store instructions
system.cpu0.num_idle_cycles 2288628005.429596 # Number of idle cycles
system.cpu0.num_busy_cycles 339634703.570404 # Number of busy cycles
system.cpu0.not_idle_fraction 0.129224 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.870776 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 856230 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.852804 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60649877 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 70.791297 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 20177865250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.225698 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.627106 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424269 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573490 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997759 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 62363363 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 62363363 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 30194610 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 30455267 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60649877 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30194610 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 30455267 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60649877 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30194610 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 30455267 # number of overall hits
system.cpu0.icache.overall_hits::total 60649877 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 417188 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 439555 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856743 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 417188 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 439555 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856743 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 417188 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 439555 # number of overall misses
system.cpu0.icache.overall_misses::total 856743 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5699086500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6114552750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11813639250 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5699086500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6114552750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11813639250 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5699086500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6114552750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11813639250 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30611798 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894822 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61506620 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30611798 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 30894822 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61506620 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30611798 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 30894822 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61506620 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013628 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014227 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013628 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014227 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013628 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014227 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13660.715313 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.779652 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13789.011699 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13789.011699 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13789.011699 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417188 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439555 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856743 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 417188 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 439555 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856743 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 417188 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 439555 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856743 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4863118500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5232991250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10096109750 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4863118500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5232991250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10096109750 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4863118500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5232991250 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10096109750 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435943750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435943750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11784.292081 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11784.292081 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11656.899288 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11905.202421 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11784.292081 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 627688 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.877185 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23660968 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 628200 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.664706 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 664900250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.764796 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.112389 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360869 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638891 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 97784872 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 97784872 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6520567 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6678544 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13199111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4990810 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4984176 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9974986 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118420 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117773 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236193 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124411 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123361 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247772 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11511377 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 11662720 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23174097 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11511377 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 11662720 # number of overall hits
system.cpu0.dcache.overall_hits::total 23174097 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 182487 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 186630 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 369117 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 126578 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 123831 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250409 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5590 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11580 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 309065 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 310461 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 619526 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 309065 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 310461 # number of overall misses
system.cpu0.dcache.overall_misses::total 619526 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2723439500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2756826750 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5480266250 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5861796621 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5628899645 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 11490696266 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80813500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79398250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 160211750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8585236121 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 8385726395 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 16970962516 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8585236121 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 8385726395 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 16970962516 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6703054 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6865174 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13568228 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5117388 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5108007 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10225395 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124410 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123363 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124411 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123361 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11820442 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 11973181 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23793623 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11820442 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 11973181 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23793623 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027224 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027185 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024735 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024243 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024489 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048147 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045313 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046736 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026147 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025930 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026147 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025930 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.026037 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.019245 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14771.616300 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14846.962481 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46309.758576 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45456.304520 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45887.712766 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.402337 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14203.622540 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.211572 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 27393.462931 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 27393.462931 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 596455 # number of writebacks
system.cpu0.dcache.writebacks::total 596455 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182487 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186630 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 369117 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126578 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123831 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250409 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5990 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11580 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 309065 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 310461 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 619526 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 309065 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 310461 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619526 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2357134500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2382546250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739680750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5582137379 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5356296355 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10938433734 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68828500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68170750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136999250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7939271879 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7738842605 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 15678114484 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7939271879 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7738842605 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 15678114484 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91425467750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647011250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072479000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13263386492 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12973041499 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236427991 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104688854242 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103620052749 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208308906991 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027185 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024735 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024243 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024489 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048147 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045313 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046736 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12916.725575 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12766.148261 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12840.591872 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44100.375887 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43254.890577 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43682.270741 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11490.567613 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12195.125224 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.677893 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7578222 # DTB read hits
system.cpu1.dtb.read_misses 7256 # DTB read misses
system.cpu1.dtb.write_hits 5608824 # DTB write hits
system.cpu1.dtb.write_misses 1858 # DTB write misses
system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6698 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7585478 # DTB read accesses
system.cpu1.dtb.write_accesses 5610682 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 13187046 # DTB hits
system.cpu1.dtb.misses 9114 # DTB misses
system.cpu1.dtb.accesses 13196160 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 30894839 # ITB inst hits
system.cpu1.itb.inst_misses 3806 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 30898645 # ITB inst accesses
system.cpu1.itb.hits 30894839 # DTB hits
system.cpu1.itb.misses 3806 # DTB misses
system.cpu1.itb.accesses 30898645 # DTB accesses
system.cpu1.numCycles 2631205114 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 30222584 # Number of instructions committed
system.cpu1.committedOps 38466237 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 34785148 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses
system.cpu1.num_func_calls 1080322 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3981720 # number of instructions that are conditional controls
system.cpu1.num_int_insts 34785148 # number of integer instructions
system.cpu1.num_fp_insts 5462 # number of float instructions
system.cpu1.num_int_register_reads 201769035 # number of times the integer registers were read
system.cpu1.num_int_register_writes 37410979 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written
system.cpu1.num_mem_refs 13781482 # number of memory refs
system.cpu1.num_load_insts 7919681 # Number of load instructions
system.cpu1.num_store_insts 5861801 # Number of store instructions
system.cpu1.num_idle_cycles 2292298207.924829 # Number of idle cycles
system.cpu1.num_busy_cycles 338906906.075172 # Number of busy cycles
system.cpu1.not_idle_fraction 0.128803 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.871197 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1557253805500 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1557253805500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|