path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.629717                       # Number of seconds simulated
sim_ticks                                2629717216500                       # Number of ticks simulated
final_tick                               2629717216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 340896                       # Simulator instruction rate (inst/s)
host_op_rate                                   433786                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14888327014                       # Simulator tick rate (ticks/s)
host_mem_usage                                 445372                       # Number of bytes of host memory used
host_seconds                                   176.63                       # Real time elapsed on the host
sim_insts                                    60212334                       # Number of instructions simulated
sim_ops                                      76619433                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           298016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4661584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           406404                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4399060                       # Number of bytes read from this memory
system.physmem.bytes_read::total            134021512                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       298016                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       406404                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          704420                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3689984                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1527272                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1489008                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6706264                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             10859                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             72871                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6366                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             68770                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15690901                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57656                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           381818                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           372252                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811726                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47250805                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              113326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1772656                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              154543                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1672826                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50964230                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         113326                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         154543                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             267869                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1403187                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             580774                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             566224                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2550184                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1403187                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47250805                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             113326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2353430                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             154543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2239050                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53514414                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15690901                       # Number of read requests accepted
system.physmem.writeReqs                       811726                       # Number of write requests accepted
system.physmem.readBursts                    15690901                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     811726                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM               1004215808                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      1856                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6837952                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 134021512                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6706264                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       29                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  704883                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4518                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              980392                       # Per bank write bursts
system.physmem.perBankRdBursts::1              980205                       # Per bank write bursts
system.physmem.perBankRdBursts::2              980222                       # Per bank write bursts
system.physmem.perBankRdBursts::3              980431                       # Per bank write bursts
system.physmem.perBankRdBursts::4              986950                       # Per bank write bursts
system.physmem.perBankRdBursts::5              980708                       # Per bank write bursts
system.physmem.perBankRdBursts::6              980610                       # Per bank write bursts
system.physmem.perBankRdBursts::7              980424                       # Per bank write bursts
system.physmem.perBankRdBursts::8              980615                       # Per bank write bursts
system.physmem.perBankRdBursts::9              980431                       # Per bank write bursts
system.physmem.perBankRdBursts::10             979815                       # Per bank write bursts
system.physmem.perBankRdBursts::11             979558                       # Per bank write bursts
system.physmem.perBankRdBursts::12             980154                       # Per bank write bursts
system.physmem.perBankRdBursts::13             980093                       # Per bank write bursts
system.physmem.perBankRdBursts::14             980155                       # Per bank write bursts
system.physmem.perBankRdBursts::15             980109                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6731                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6599                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6610                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6672                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6746                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7052                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7033                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6881                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7002                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6827                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6323                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6122                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6612                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6399                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6618                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6616                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2629712785000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6706                       # Read request sizes (log2)
system.physmem.readPktSize::3                15532032                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  152163                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754070                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  57656                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1290849                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1134741                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1135188                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3791353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2690884                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2690157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2706986                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     51561                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     56279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     20477                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    20472                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    20444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20380                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20341                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       45                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5039                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4708                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        90454                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11177.544033                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1030.436917                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16744.733089                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          23393     25.86%     25.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14737     16.29%     42.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         2929      3.24%     45.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2185      2.42%     47.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1403      1.55%     49.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1153      1.27%     50.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          940      1.04%     51.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519         1175      1.30%     52.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          610      0.67%     53.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          557      0.62%     54.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          555      0.61%     54.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          601      0.66%     55.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          293      0.32%     55.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          323      0.36%     56.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          207      0.23%     56.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          643      0.71%     57.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          173      0.19%     57.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          141      0.16%     57.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223          139      0.15%     57.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          211      0.23%     57.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351          108      0.12%     58.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415         2249      2.49%     60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479          108      0.12%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          135      0.15%     60.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           71      0.08%     60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671           48      0.05%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           33      0.04%     60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799           98      0.11%     61.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           34      0.04%     61.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           27      0.03%     61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           23      0.03%     61.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          231      0.26%     61.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119           24      0.03%     61.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           27      0.03%     61.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           30      0.03%     61.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311          143      0.16%     61.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375           12      0.01%     61.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           18      0.02%     61.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503           17      0.02%     61.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567           86      0.10%     61.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631           22      0.02%     61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           12      0.01%     61.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759           15      0.02%     61.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823          205      0.23%     62.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887           13      0.01%     62.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           20      0.02%     62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015           10      0.01%     62.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          404      0.45%     62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143           18      0.02%     62.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207            8      0.01%     62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            8      0.01%     62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335           21      0.02%     62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399           11      0.01%     62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           14      0.02%     62.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527           16      0.02%     62.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591           82      0.09%     62.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655            9      0.01%     62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           15      0.02%     62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783           35      0.04%     62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847          129      0.14%     62.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911           12      0.01%     62.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975            9      0.01%     62.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039            7      0.01%     63.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          283      0.31%     63.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            7      0.01%     63.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231            5      0.01%     63.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295           10      0.01%     63.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359            6      0.01%     63.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423            5      0.01%     63.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           11      0.01%     63.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551            8      0.01%     63.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615          271      0.30%     63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679           14      0.02%     63.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743            4      0.00%     63.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807            9      0.01%     63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871          136      0.15%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            4      0.00%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           11      0.01%     63.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063           11      0.01%     63.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          341      0.38%     64.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            2      0.00%     64.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           14      0.02%     64.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            4      0.00%     64.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383          205      0.23%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447          168      0.19%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511           59      0.07%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639            3      0.00%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            1      0.00%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895          126      0.14%     64.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          267      0.30%     65.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407          256      0.28%     65.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535            2      0.00%     65.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            1      0.00%     65.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663            5      0.01%     65.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           65      0.07%     65.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          454      0.50%     66.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303            1      0.00%     66.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431            9      0.01%     66.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559            2      0.00%     66.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687          192      0.21%     66.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943            2      0.00%     66.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          261      0.29%     66.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711          193      0.21%     66.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967            9      0.01%     66.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          455      0.50%     67.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9351            1      0.00%     67.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           64      0.07%     67.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735            5      0.01%     67.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991          257      0.28%     67.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10183            1      0.00%     67.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          265      0.29%     67.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503          124      0.14%     68.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759            4      0.00%     68.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015          195      0.22%     68.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11079            1      0.00%     68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11207            1      0.00%     68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          336      0.37%     68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527          123      0.14%     68.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783          266      0.29%     69.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          267      0.30%     69.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551          121      0.13%     69.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807           75      0.08%     69.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063            4      0.00%     69.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          387      0.43%     70.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575          197      0.22%     70.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831           78      0.09%     70.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13895            1      0.00%     70.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087          129      0.14%     70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          206      0.23%     70.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599           65      0.07%     70.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           65      0.07%     70.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           71      0.08%     70.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          455      0.50%     71.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           66      0.07%     71.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879          131      0.14%     71.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135          128      0.14%     71.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          401      0.44%     72.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647          130      0.14%     72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903          129      0.14%     72.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17095            1      0.00%     72.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           68      0.08%     72.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          460      0.51%     73.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17600-17607            1      0.00%     73.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           71      0.08%     73.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           66      0.07%     73.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183           64      0.07%     73.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          208      0.23%     73.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695          128      0.14%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951           77      0.09%     73.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207          196      0.22%     74.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            1      0.00%     74.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          386      0.43%     74.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719            3      0.00%     74.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975           72      0.08%     74.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231          120      0.13%     74.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          270      0.30%     74.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999          265      0.29%     75.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255          123      0.14%     75.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          334      0.37%     75.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767          195      0.22%     75.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21824-21831            1      0.00%     75.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023            3      0.00%     76.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279          127      0.14%     76.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          264      0.29%     76.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22720-22727            1      0.00%     76.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791          255      0.28%     76.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047            5      0.01%     76.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           65      0.07%     76.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          452      0.50%     77.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815            9      0.01%     77.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071          192      0.21%     77.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327            3      0.00%     77.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          259      0.29%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839            1      0.00%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095          193      0.21%     78.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351            7      0.01%     78.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          454      0.50%     78.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           66      0.07%     78.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119            5      0.01%     78.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375          256      0.28%     78.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          266      0.29%     79.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887          124      0.14%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143            2      0.00%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399          195      0.22%     79.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          332      0.37%     79.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911          123      0.14%     80.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167          266      0.29%     80.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          267      0.30%     80.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935          122      0.13%     80.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191           74      0.08%     80.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447            4      0.00%     80.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          387      0.43%     81.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959          194      0.21%     81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215           77      0.09%     81.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279            1      0.00%     81.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471          128      0.14%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          205      0.23%     81.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983           64      0.07%     82.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           66      0.07%     82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           71      0.08%     82.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          457      0.51%     82.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           65      0.07%     82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263          130      0.14%     82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519          128      0.14%     83.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          400      0.44%     83.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031          128      0.14%     83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287          135      0.15%     83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           65      0.07%     83.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          456      0.50%     84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           71      0.08%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           66      0.07%     84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567           64      0.07%     84.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          205      0.23%     84.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34944-34951            1      0.00%     84.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079          128      0.14%     84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335           76      0.08%     85.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591          194      0.21%     85.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          386      0.43%     85.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103            3      0.00%     85.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359           73      0.08%     85.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615          121      0.13%     85.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          265      0.29%     86.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383          265      0.29%     86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639          123      0.14%     86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          333      0.37%     86.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151          195      0.22%     87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407            2      0.00%     87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663          125      0.14%     87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          265      0.29%     87.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175          256      0.28%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431            5      0.01%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           65      0.07%     87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          452      0.50%     88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199            7      0.01%     88.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455          192      0.21%     88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          259      0.29%     88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223            3      0.00%     88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479          192      0.21%     89.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735            9      0.01%     89.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          452      0.50%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           64      0.07%     89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503            5      0.01%     89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759          255      0.28%     90.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42816-42823            1      0.00%     90.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          264      0.29%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271          126      0.14%     90.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527            3      0.00%     90.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43712-43719            1      0.00%     90.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783          194      0.21%     90.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          335      0.37%     91.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295          123      0.14%     91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551          264      0.29%     91.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          264      0.29%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319          120      0.13%     91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575           72      0.08%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831            4      0.00%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          385      0.43%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343          194      0.21%     92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599           76      0.08%     92.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855          128      0.14%     92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          209      0.23%     93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367           65      0.07%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           67      0.07%     93.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751            1      0.00%     93.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           73      0.08%     93.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943            2      0.00%     93.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          459      0.51%     93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48256-48263            3      0.00%     93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391           69      0.08%     93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48448-48455            1      0.00%     93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647          129      0.14%     94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903          129      0.14%     94.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            3      0.00%     94.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            1      0.00%     94.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            3      0.00%     94.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5220      5.77%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          90454                       # Bytes accessed per row activation
system.physmem.totQLat                   377144928750                       # Total ticks spent queuing
system.physmem.totMemAccLat              474552728750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  78454360000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 18953440000                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24035.94                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1207.93                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30243.87                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         381.87                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.60                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         1.22                       # Average write queue length when enqueuing
system.physmem.readRowHits                   15616330                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     90931                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  85.11                       # Row buffer hit rate for writes
system.physmem.avgGap                       159351.16                       # Average gap between requests
system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               2.39                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     54426353                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16743636                       # Transaction distribution
system.membus.trans_dist::ReadResp           16743636                       # Transaction distribution
system.membus.trans_dist::WriteReq             763424                       # Transaction distribution
system.membus.trans_dist::WriteResp            763424                       # Transaction distribution
system.membus.trans_dist::Writeback             57656                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4518                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4518                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131342                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131342                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382990                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3860                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892570                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4279432                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               35343496                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390397                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16471520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     18869661                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           143125917                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              143125917                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1225680000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3756000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         18171618500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4990533473                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        35075577250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.l2c.tags.replacements                    62046                       # number of replacements
system.l2c.tags.tagsinuse                51605.865819                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1699437                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   127429                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.336344                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2574782383500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38213.733489                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000701                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2749.245070                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3097.480060                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000187                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4271.539066                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3273.867246                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.583095                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.041950                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.047264                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.065179                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.049955                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.787443                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         9827                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3607                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             412393                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             183168                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        10051                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3578                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             432141                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             187290                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1242055                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          596450                       # number of Writeback hits
system.l2c.Writeback_hits::total               596450                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            57240                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            57291                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               114531                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          9827                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3607                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              412393                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              240408                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         10051                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3578                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              432141                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              244581                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1356586                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         9827                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3607                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             412393                       # number of overall hits
system.l2c.overall_hits::cpu0.data             240408                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        10051                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3578                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             432141                       # number of overall hits
system.l2c.overall_hits::cpu1.data             244581                       # number of overall hits
system.l2c.overall_hits::total                1356586                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             4243                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             5343                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6349                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4883                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                20821                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1353                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1530                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2883                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          68272                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          64705                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             132977                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              4243                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             73615                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6349                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             69588                       # number of demand (read+write) misses
system.l2c.demand_misses::total                153798                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             4243                       # number of overall misses
system.l2c.overall_misses::cpu0.data            73615                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6349                       # number of overall misses
system.l2c.overall_misses::cpu1.data            69588                       # number of overall misses
system.l2c.overall_misses::total               153798                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    301157500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    396109250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        89250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    450843500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    372813750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1521162750                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       232990                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       231990                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       464980                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4857371220                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4602598395                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9459969615                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    301157500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   5253480470                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        89250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    450843500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4975412145                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     10981132365                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    301157500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   5253480470                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        89250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    450843500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4975412145                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    10981132365                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9827                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3609                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         416636                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         188511                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        10052                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         3578                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         438490                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         192173                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1262876                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       596450                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           596450                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1366                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1543                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2909                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       125512                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       121996                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247508                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9827                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3609                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          416636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          314023                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10052                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         3578                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          438490                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          314169                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1510384                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9827                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3609                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         416636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         314023                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10052                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         3578                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         438490                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         314169                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1510384                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.010184                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.028343                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.014479                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.025409                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016487                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990483                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991575                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991062                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.543948                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.530386                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.537263                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010184                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.234426                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.014479                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.221499                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.101827                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010184                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.234426                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.014479                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.221499                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.101827                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70977.492340                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74136.112671                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71010.159080                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76349.324186                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73059.062965                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   172.202513                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   151.627451                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   161.283385                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71147.340345                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71132.036087                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 71139.893478                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 70977.492340                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 71364.266386                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71010.159080                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71498.133946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71399.708481                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 70977.492340                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 71364.266386                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71010.159080                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71498.133946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71399.708481                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               57656                       # number of writebacks
system.l2c.writebacks::total                    57656                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         4243                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         5343                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6349                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4883                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           20821                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1353                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1530                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2883                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        68272                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        64705                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        132977                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         4243                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        73615                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6349                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        69588                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           153798                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         4243                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        73615                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6349                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        69588                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          153798                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    247421000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    329573750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    370327500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    311886250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1259409750                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13531353                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     15301530                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     28832883                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3982762780                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3773110105                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7755872885                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    247421000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4312336530                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    370327500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4084996355                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9015282635                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    247421000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4312336530                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    370327500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4084996355                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9015282635                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    343871250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83755912750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst       842500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82922372500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167022999000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8435630009                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8264647000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16700277009                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    343871250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92191542759                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst       842500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91187019500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183723276009                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.010184                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.028343                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014479                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025409                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016487                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990483                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991575                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991062                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.543948                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.530386                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.537263                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010184                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.234426                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014479                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.221499                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.101827                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010184                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.234426                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014479                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.221499                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.101827                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58312.750412                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61683.277185                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58328.476926                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63871.851321                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60487.476586                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58336.694106                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58312.496793                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58324.919986                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58312.750412                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58579.590165                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58328.476926                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58702.597502                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58617.684463                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58312.750412                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58579.590165                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58617.684463                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    52790683                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2471881                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2471881                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763424                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763424                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           596450                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2909                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2909                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           247508                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          247508                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725145                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753790                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20211                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50526                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7549672                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54754616                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83791781                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28748                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79516                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          138654661                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             138654661                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          169908                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4808598000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3865648250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4421117527                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          13024000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          30647250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48159799                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16715360                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16715360                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8167                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8167                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          536                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382990                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                33447054                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            126646653                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               126646653                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               536000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15532032000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374823000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         42583673750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7421376                       # DTB read hits
system.cpu0.dtb.read_misses                      6854                       # DTB read misses
system.cpu0.dtb.write_hits                    5628030                       # DTB write hits
system.cpu0.dtb.write_misses                     1815                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1247                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                673                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    6418                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   151                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      219                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7428230                       # DTB read accesses
system.cpu0.dtb.write_accesses                5629845                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         13049406                       # DTB hits
system.cpu0.dtb.misses                           8669                       # DTB misses
system.cpu0.dtb.accesses                     13058075                       # DTB accesses
system.cpu0.itb.inst_hits                    30610107                       # ITB inst hits
system.cpu0.itb.inst_misses                      3562                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1247                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                673                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2748                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                30613669                       # ITB inst accesses
system.cpu0.itb.hits                         30610107                       # DTB hits
system.cpu0.itb.misses                           3562                       # DTB misses
system.cpu0.itb.accesses                     30613669                       # DTB accesses
system.cpu0.numCycles                      2628235952                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   29990580                       # Number of instructions committed
system.cpu0.committedOps                     38158663                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             34282971                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4584                       # Number of float alu accesses
system.cpu0.num_func_calls                    1059870                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3968282                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    34282971                       # number of integer instructions
system.cpu0.num_fp_insts                         4584                       # number of float instructions
system.cpu0.num_int_register_reads          196555242                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          36964020                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3346                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1240                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     13622094                       # number of memory refs
system.cpu0.num_load_insts                    7743834                       # Number of load instructions
system.cpu0.num_store_insts                   5878260                       # Number of store instructions
system.cpu0.num_idle_cycles              2282805163.828333                       # Number of idle cycles
system.cpu0.num_busy_cycles              345430788.171666                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.131431                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.868569                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83029                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           856230                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.853093                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           60649685                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           856742                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            70.791072                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      20173406250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   217.243034                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   293.610060                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.424303                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.573457                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997760                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     30192721                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     30456964                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       60649685                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     30192721                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     30456964                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        60649685                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     30192721                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     30456964                       # number of overall hits
system.cpu0.icache.overall_hits::total       60649685                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       417386                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       439357                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       856743                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       417386                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       439357                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        856743                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       417386                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       439357                       # number of overall misses
system.cpu0.icache.overall_misses::total       856743                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5696153000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6111476500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11807629500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5696153000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6111476500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11807629500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5696153000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6111476500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11807629500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     30610107                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     30896321                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     61506428                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     30610107                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     30896321                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     61506428                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     30610107                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     30896321                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     61506428                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013636                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014220                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.013929                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013636                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014220                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.013929                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013636                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014220                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.013929                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.997052                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13647.206662                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.046955                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13781.997052                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13647.206662                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.046955                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13781.997052                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       417386                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       439357                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       856743                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       417386                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       439357                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       856743                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       417386                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       439357                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       856743                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4859799000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5230292500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10090091500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4859799000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5230292500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10090091500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4859799000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5230292500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10090091500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    435321250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      1072500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    436393750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    435321250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst      1072500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    436393750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013636                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014220                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013929                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013636                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014220                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.013929                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013636                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014220                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.013929                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.416406                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.425103                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11777.267512                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.416406                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.425103                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11777.267512                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.416406                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.425103                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11777.267512                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           627680                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.877363                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           23660930                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           628192                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            37.665125                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        664004250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.794485                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.082879                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.360927                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.638834                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999760                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6519451                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6679636                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13199087                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      4994316                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      4980652                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9974968                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       118550                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117644                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       236194                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       124564                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       123208                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247772                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11513767                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     11660288                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        23174055                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11513767                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     11660288                       # number of overall hits
system.cpu0.dcache.overall_hits::total       23174055                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       182495                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       186610                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       369105                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       126878                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       123539                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       250417                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6016                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5563                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11579                       # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data       309373                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       310149                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        619522                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       309373                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       310149                       # number of overall misses
system.cpu0.dcache.overall_misses::total       619522                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2725951250                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2755941500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5481892750                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5868624133                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5606519635                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  11475143768                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     81127500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79383250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    160510750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8594575383                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   8362461135                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  16957036518                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8594575383                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   8362461135                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  16957036518                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6701946                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      6866246                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13568192                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5121194                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      5104191                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10225385                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124566                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       123207                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       247773                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       124564                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       123208                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247772                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11823140                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     11970437                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     23793577                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11823140                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     11970437                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     23793577                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027230                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.027178                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.027204                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024775                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024203                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.024490                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048296                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045152                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046732                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026167                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025910                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026037                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026167                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025910                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.026037                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14937.128414                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14768.455603                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14851.851777                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46254.071888                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45382.588778                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45824.140406                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13485.289229                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14269.863383                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13862.229035                       # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27780.625274                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26962.721579                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 27371.161182                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27780.625274                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26962.721579                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 27371.161182                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       596450                       # number of writebacks
system.cpu0.dcache.writebacks::total           596450                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       182495                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       186610                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       369105                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126878                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       123539                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       250417                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6016                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5563                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11579                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       309373                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       310149                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       619522                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       309373                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       310149                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       619522                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2359626750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2381686500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4741313250                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5588242867                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5334624365                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10922867232                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69088500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     68209750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137298250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7947869617                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7716310865                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15664180482                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7947869617                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7716310865                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  15664180482                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91489795250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90582792250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13259276491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  12977158000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26236434491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027230                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027178                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027204                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024775                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024203                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024490                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048296                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.045152                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046732                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026167                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025910                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.026037                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026167                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025910                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026037                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     7578699                       # DTB read hits
system.cpu1.dtb.read_misses                      7251                       # DTB read misses
system.cpu1.dtb.write_hits                    5604812                       # DTB write hits
system.cpu1.dtb.write_misses                     1846                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1247                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                766                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    6708                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   153                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      233                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 7585950                       # DTB read accesses
system.cpu1.dtb.write_accesses                5606658                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         13183511                       # DTB hits
system.cpu1.dtb.misses                           9097                       # DTB misses
system.cpu1.dtb.accesses                     13192608                       # DTB accesses
system.cpu1.itb.inst_hits                    30896338                       # ITB inst hits
system.cpu1.itb.inst_misses                      3789                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1247                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                766                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2857                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                30900127                       # ITB inst accesses
system.cpu1.itb.hits                         30896338                       # DTB hits
system.cpu1.itb.misses                           3789                       # DTB misses
system.cpu1.itb.accesses                     30900127                       # DTB accesses
system.cpu1.numCycles                      2631198481                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   30221754                       # Number of instructions committed
system.cpu1.committedOps                     38460770                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             34602143                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5685                       # Number of float alu accesses
system.cpu1.num_func_calls                    1080538                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3981203                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    34602143                       # number of integer instructions
system.cpu1.num_fp_insts                         5685                       # number of float instructions
system.cpu1.num_int_register_reads          198301383                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          37233535                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4147                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1540                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     13778426                       # number of memory refs
system.cpu1.num_load_insts                    7920474                       # Number of load instructions
system.cpu1.num_store_insts                   5857952                       # Number of store instructions
system.cpu1.num_idle_cycles              2292395060.642381                       # Number of idle cycles
system.cpu1.num_busy_cycles              338803420.357619                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.128764                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.871236                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1557221573750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------