1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
|
---------- Begin Simulation Statistics ----------
sim_seconds 47.464182 # Number of seconds simulated
sim_ticks 47464181819000 # Number of ticks simulated
final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 165089 # Simulator instruction rate (inst/s)
host_op_rate 194182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9130718670 # Simulator tick rate (ticks/s)
host_mem_usage 773696 # Number of bytes of host memory used
host_seconds 5198.30 # Real time elapsed on the host
sim_insts 858179266 # Number of instructions simulated
sim_ops 1009414094 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory
system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 226886 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1586 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 74342 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 180196 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 74342 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1349757 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1350190 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1349757 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1613 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 144970 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 791709 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 226886 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1586 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 1443 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 74342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 285629 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 180196 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9187 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3069119 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1274831 # Number of read requests accepted
system.physmem.writeReqs 1003591 # Number of write requests accepted
system.physmem.readBursts 1274831 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1003591 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 81546816 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue
system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 81587544 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 64085672 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 221043 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 69298 # Per bank write bursts
system.physmem.perBankRdBursts::1 80196 # Per bank write bursts
system.physmem.perBankRdBursts::2 71590 # Per bank write bursts
system.physmem.perBankRdBursts::3 80518 # Per bank write bursts
system.physmem.perBankRdBursts::4 76240 # Per bank write bursts
system.physmem.perBankRdBursts::5 80771 # Per bank write bursts
system.physmem.perBankRdBursts::6 77164 # Per bank write bursts
system.physmem.perBankRdBursts::7 81418 # Per bank write bursts
system.physmem.perBankRdBursts::8 74880 # Per bank write bursts
system.physmem.perBankRdBursts::9 125815 # Per bank write bursts
system.physmem.perBankRdBursts::10 65333 # Per bank write bursts
system.physmem.perBankRdBursts::11 79047 # Per bank write bursts
system.physmem.perBankRdBursts::12 75605 # Per bank write bursts
system.physmem.perBankRdBursts::13 79656 # Per bank write bursts
system.physmem.perBankRdBursts::14 77605 # Per bank write bursts
system.physmem.perBankRdBursts::15 79033 # Per bank write bursts
system.physmem.perBankWrBursts::0 58028 # Per bank write bursts
system.physmem.perBankWrBursts::1 64393 # Per bank write bursts
system.physmem.perBankWrBursts::2 59641 # Per bank write bursts
system.physmem.perBankWrBursts::3 64677 # Per bank write bursts
system.physmem.perBankWrBursts::4 61513 # Per bank write bursts
system.physmem.perBankWrBursts::5 65147 # Per bank write bursts
system.physmem.perBankWrBursts::6 63058 # Per bank write bursts
system.physmem.perBankWrBursts::7 64825 # Per bank write bursts
system.physmem.perBankWrBursts::8 60547 # Per bank write bursts
system.physmem.perBankWrBursts::9 63081 # Per bank write bursts
system.physmem.perBankWrBursts::10 56749 # Per bank write bursts
system.physmem.perBankWrBursts::11 64053 # Per bank write bursts
system.physmem.perBankWrBursts::12 61964 # Per bank write bursts
system.physmem.perBankWrBursts::13 65797 # Per bank write bursts
system.physmem.perBankWrBursts::14 62586 # Per bank write bursts
system.physmem.perBankWrBursts::15 65266 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 59 # Number of times write queue was full causing retry
system.physmem.totGap 47464179840500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1274801 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1001017 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 816238 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 315854 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 31830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 23000 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 19787 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 18192 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 16305 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 14624 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 12016 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2281 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 783 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 615 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 252 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 201 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 15348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 17874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 37266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 47521 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 53574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 55971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 59005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 60181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 62652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 62838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 63556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 68208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 65188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 65181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 70319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 65705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 61499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 58334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1919 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 339 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 227 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 193 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 760858 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 191.403705 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 116.807820 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 448904 59.00% 59.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 151841 19.96% 78.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 50675 6.66% 85.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 27026 3.55% 89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 17061 2.24% 91.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11068 1.45% 92.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8074 1.06% 93.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8214 1.08% 95.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 760858 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 56148 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 56145 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads
system.physmem.totQLat 34002300770 # Total ticks spent queuing
system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing
system.physmem.readRowHits 1026298 # Number of row buffer hits during reads
system.physmem.writeRowHits 488335 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes
system.physmem.avgGap 20832040.70 # Average gap between requests
system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.645246 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states
system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.668617 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states
system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 135703894 # Number of BP lookups
system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 277006 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 88941283 # DTB read hits
system.cpu0.dtb.read_misses 229899 # DTB read misses
system.cpu0.dtb.write_hits 77314134 # DTB write hits
system.cpu0.dtb.write_misses 47107 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 89171182 # DTB read accesses
system.cpu0.dtb.write_accesses 77361241 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 166255417 # DTB hits
system.cpu0.dtb.misses 277006 # DTB misses
system.cpu0.dtb.accesses 166532423 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 67964 # Table walker walks requested
system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 243132835 # ITB inst hits
system.cpu0.itb.inst_misses 67964 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses
system.cpu0.itb.hits 243132835 # DTB hits
system.cpu0.itb.misses 67964 # DTB misses
system.cpu0.itb.accesses 243200799 # DTB accesses
system.cpu0.numCycles 1024570142 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 453671847 # Number of instructions committed
system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.258395 # CPI: cycles per instruction
system.cpu0.ipc 0.442792 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed
system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 5606815 # number of replacements
system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 153315707 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 153315707 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 153568738 # number of overall hits
system.cpu0.dcache.overall_hits::total 153568738 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3470214 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3470214 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2296821 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2296821 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 622517 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 622517 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 787681 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 787681 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168627 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 168627 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185724 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 185724 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 5767035 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 5767035 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6389552 # number of overall misses
system.cpu0.dcache.overall_misses::total 6389552 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57404903000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 57404903000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53218814500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 53218814500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 70624877500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 70624877500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2615349000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2615349000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4471340500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4471340500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4645500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4645500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 110623717500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 110623717500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 110623717500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 110623717500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 85014217 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 85014217 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74068525 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 74068525 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 875548 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 875548 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 917684 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 917684 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986862 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 1986862 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1984839 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1984839 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 159082742 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 159082742 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 159958290 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 159958290 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040819 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.040819 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031009 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.031009 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.711003 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.711003 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858336 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858336 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084871 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084871 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093571 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093571 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036252 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.036252 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039945 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.039945 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16542.179531 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16542.179531 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23170.640855 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23170.640855 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 89661.776150 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 89661.776150 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15509.669270 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15509.669270 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24075.189529 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24075.189529 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19182.078399 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19182.078399 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17313.219691 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17313.219691 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 3758761 # number of writebacks
system.cpu0.dcache.writebacks::total 3758761 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423304 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 423304 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 954060 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 954060 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 67 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 67 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43006 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43006 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 59 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1377364 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1377364 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1377364 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1377364 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3046910 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3046910 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342761 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1342761 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 616851 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 616851 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 787614 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 787614 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125621 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125621 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185665 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 185665 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4389671 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4389671 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5006522 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5006522 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14625 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30107 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45015119500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45015119500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30226463500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30226463500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15766385500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15766385500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 69831148500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 69831148500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1724289500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1724289500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4281874000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4281874000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4478500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4478500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75241583000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 75241583000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91007968500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 91007968500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2444404000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 9688574 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 233226662 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 233226662 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 233226662 # number of overall hits
system.cpu0.icache.overall_hits::total 233226662 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 9689087 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 9689087 # number of overall misses
system.cpu0.icache.overall_misses::total 9689087 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100299166000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 100299166000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 242915749 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 242915749 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9689087 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 9689087 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 9689087 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 9689087 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 9689087 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 9689087 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95454623000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 95454623000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95454623000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 95454623000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95454623000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 95454623000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039887 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.039887 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.039887 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.766529 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7463777 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7463951 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 154 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1020305 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2664787 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15957.113648 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 26864509 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2680682 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 10.021520 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 6872.215886 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 83.268968 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 86.677569 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4373.710312 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3617.876682 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 923.364231 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.419447 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005082 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005290 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.266950 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.220818 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056358 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.973945 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1328 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14509 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 565 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 693 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 52 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4763 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8150 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 382 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081055 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 513598249 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 513598249 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 486721 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 161483 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 648204 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 3758761 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 3758761 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 96787 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 96787 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34850 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 34850 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 870093 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 870093 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8916496 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 8916496 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2811099 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2811099 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 212338 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 212338 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 486721 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 161483 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 8916496 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3681192 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 13245892 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 486721 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 161483 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 8916496 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3681192 # number of overall hits
system.cpu0.l2cache.overall_hits::total 13245892 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11149 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7679 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 18828 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134429 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 134429 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 150813 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 150813 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 252885 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 252885 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 772590 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 772590 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 977962 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 977962 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 573862 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 573862 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11149 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7679 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 772590 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1230847 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2022265 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11149 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7679 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 772590 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1230847 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2022265 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 426258000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 324009000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 750267000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4100217500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 4100217500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3583690499 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3583690499 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4385000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4385000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16205618499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 16205618499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27749596500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27749596500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 38364944997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 38364944997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67134826000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 67134826000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 426258000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 324009000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27749596500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 54570563496 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 83070426996 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 426258000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 324009000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27749596500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 54570563496 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 83070426996 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 497870 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 169162 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 667032 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 3758761 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 3758761 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231216 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 231216 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 185663 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 185663 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1122978 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1122978 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9689086 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 9689086 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3789061 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 3789061 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 786200 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 786200 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 497870 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 169162 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 9689086 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 4912039 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 15268157 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 497870 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 169162 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 9689086 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 4912039 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 15268157 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045394 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.028227 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.581400 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.581400 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.812294 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.812294 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.225191 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.225191 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079738 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079738 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.258101 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.258101 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729919 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729919 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045394 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079738 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250578 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.132450 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045394 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079738 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250578 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.132450 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42194.165907 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39848.470363 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30500.989370 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30500.989370 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23762.477366 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23762.477366 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2192500 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2192500 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64082.956676 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64082.956676 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35917.623190 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35917.623190 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39229.484374 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39229.484374 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 116987.753153 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 116987.753153 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 41077.913625 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 41077.913625 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 189 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 189 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 1318085 # number of writebacks
system.cpu0.l2cache.writebacks::total 1318085 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5018 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5018 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1141 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1141 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6159 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6170 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6159 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 6170 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11148 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7676 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 18824 # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 109829 # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total 109829 # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 670532 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 134429 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 134429 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 150813 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 150813 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247867 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 247867 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 772583 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 772583 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 976821 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 976821 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 573859 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 573859 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11148 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7676 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 772583 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1224688 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 2016095 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11148 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7676 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 772583 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1224688 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2686627 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 66934 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 82416 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 277905000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 637268000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33195033631 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4709210494 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4709210494 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2870671499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2870671499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4013000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4013000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13996811499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13996811499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23113725500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23113725500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32421419997 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32421419997 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 63691409500 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 63691409500 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277905000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23113725500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46418231496 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 70169224996 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277905000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23113725500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46418231496 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 103364258627 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2327318500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9322247500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2417234500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2417234500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4744553000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11739482000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028221 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.581400 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.581400 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812294 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.812294 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220723 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220723 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 123013748 # Number of BP lookups
system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 261280 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 79147380 # DTB read hits
system.cpu1.dtb.read_misses 216729 # DTB read misses
system.cpu1.dtb.write_hits 70165250 # DTB write hits
system.cpu1.dtb.write_misses 44551 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 79364109 # DTB read accesses
system.cpu1.dtb.write_accesses 70209801 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 149312630 # DTB hits
system.cpu1.dtb.misses 261280 # DTB misses
system.cpu1.dtb.accesses 149573910 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 64423 # Table walker walks requested
system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 219650463 # ITB inst hits
system.cpu1.itb.inst_misses 64423 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses
system.cpu1.itb.hits 219650463 # DTB hits
system.cpu1.itb.misses 64423 # DTB misses
system.cpu1.itb.accesses 219714886 # DTB accesses
system.cpu1.numCycles 870330668 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 404507419 # Number of instructions committed
system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.151581 # CPI: cycles per instruction
system.cpu1.ipc 0.464774 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed
system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements 4754677 # number of replacements
system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits
system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses
system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41378134500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 143188790 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707385 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks
system.cpu1.dcache.writebacks::total 3093987 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1182784 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 3889795 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4459525 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4459525 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38219808000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24026284000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24026284000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13466616000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13466616000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1560972500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174804000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62246092000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75712708000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 75712708000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4058237000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3938068000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3938068000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7996305000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16002.409381 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16002.409381 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16977.751666 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16977.751666 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172617.481923 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172617.481923 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174466.950204 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174466.950204 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173523.393082 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173523.393082 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 8864427 # number of replacements
system.cpu1.icache.tags.tagsinuse 506.853262 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 210585390 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 8864939 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 23.754861 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.853262 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989948 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.989948 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 447765626 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 447765626 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 210585390 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 210585390 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 210585390 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 210585390 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 210585390 # number of overall hits
system.cpu1.icache.overall_hits::total 210585390 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 8864949 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 8864949 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 8864949 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 8864949 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 8864949 # number of overall misses
system.cpu1.icache.overall_misses::total 8864949 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93186086500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 93186086500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 93186086500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 93186086500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 93186086500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 93186086500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 219450339 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 219450339 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 219450339 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 219450339 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 219450339 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 219450339 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.040396 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.040396 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.040396 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.040396 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.040396 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.040396 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10511.745358 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10511.745358 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10511.745358 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10511.745358 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8864949 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 8864949 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 8864949 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 8864949 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 8864949 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 8864949 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88753612500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 88753612500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88753612500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 88753612500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88753612500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 88753612500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.040396 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.040396 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.040396 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10011.745414 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6449392 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6450426 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 905 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 802102 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2183837 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13560.981052 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 24336260 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2199514 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.064381 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9986977778000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 3995.301083 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.705175 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.813454 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5399.423450 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3183.311357 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 849.426534 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.243854 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004132 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004017 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.329555 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194294 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051845 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.827697 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1064 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14535 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 92 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 248 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 600 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 111 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 33 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 692 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4987 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7639 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1109 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064941 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887146 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 457590280 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 457590280 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 449487 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151613 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 601100 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 3093985 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 3093985 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65506 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 65506 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33165 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 33165 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 791344 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 791344 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8112196 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 8112196 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2464747 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2464747 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 204016 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 204016 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 449487 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151613 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 8112196 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3256091 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 11969387 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 449487 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151613 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 8112196 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3256091 # number of overall hits
system.cpu1.l2cache.overall_hits::total 11969387 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10587 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7678 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 18265 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 126676 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 126676 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 148906 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 148906 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 229716 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 229716 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 752753 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 752753 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 896376 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 896376 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 260955 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 260955 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10587 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7678 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 752753 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1126092 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1897110 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10587 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7678 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 752753 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1126092 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1897110 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 399086500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 314156000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 713242500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3920313500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 3920313500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3517664000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3517664000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5390999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5390999 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11586003000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 11586003000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27103959000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 27103959000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32012190991 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32012190991 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17327350500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 17327350500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 399086500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 314156000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 27103959000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 43598193991 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 71415395491 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 399086500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 314156000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27103959000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 43598193991 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 71415395491 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 460074 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159291 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 619365 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 3093985 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 3093985 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 192182 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 192182 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 182071 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 182071 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1021060 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1021060 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8864949 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 8864949 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3361123 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3361123 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464971 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 464971 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 460074 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159291 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 8864949 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4382183 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 13866497 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 460074 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159291 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 8864949 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4382183 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 13866497 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048201 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.659146 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.659146 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.817846 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.817846 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224978 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224978 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.084913 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.084913 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.266689 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.266689 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.561229 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.561229 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048201 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.084913 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256971 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.136812 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048201 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.084913 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256971 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.136812 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40916.384475 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39049.685190 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30947.563074 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30947.563074 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23623.386566 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23623.386566 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 770142.714286 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 770142.714286 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50436.203834 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50436.203834 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36006.444345 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36006.444345 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35712.905066 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35712.905066 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66399.764327 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66399.764327 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 37644.309234 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 37644.309234 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 895073 # number of writebacks
system.cpu1.l2cache.writebacks::total 895073 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4757 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 4757 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1267 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1267 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6024 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6024 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10587 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7677 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 18264 # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104448 # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total 104448 # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 626506 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 126676 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 126676 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 148906 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 148906 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224959 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 224959 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 752748 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 752748 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 895109 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 895109 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 260951 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 260951 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10587 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7677 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 752748 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1120068 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1891080 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10587 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7677 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 752748 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1120068 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2517586 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23602 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46174 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 268081000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 603645500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27110588000 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4296542495 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4296542495 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2791394499 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2791394499 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4964999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4964999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9564152000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9564152000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 22587351000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 22587351000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26554233491 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26554233491 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15760443000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15760443000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 268081000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 22587351000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36118385491 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 59309381991 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 268081000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 22587351000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36118385491 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 86419969991 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11784000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3870100000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3881884000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3768766500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3768766500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 11784000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7638866500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7650650500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029488 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.659146 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.659146 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817846 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817846 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220319 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220319 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084913 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.266312 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266312 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.561220 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.561220 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136378 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181559 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33051.111476 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43272.670972 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33917.573139 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33917.573139 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18746.017615 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18746.017615 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 709285.571429 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 709285.571429 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 42515.089416 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 42515.089416 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30006.524096 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29665.921682 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40378 # Transaction distribution
system.iobus.trans_dist::ReadResp 40378 # Transaction distribution
system.iobus.trans_dist::WriteReq 136939 # Transaction distribution
system.iobus.trans_dist::WriteResp 136939 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7513376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36227000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 567439447 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92820000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115886 # number of replacements
system.iocache.tags.tagsinuse 11.252205 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115902 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9146784544000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.402122 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.850083 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.462633 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.240630 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.703263 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1043376 # Number of tag accesses
system.iocache.tags.data_accesses 1043376 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses
system.iocache.demand_misses::total 8947 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8907 # number of overall misses
system.iocache.overall_misses::total 8947 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1688317981 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1693512981 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 13959998466 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13959998466 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1688317981 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1693881981 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1688317981 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1693881981 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 189549.565623 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 189346.263529 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130486.787426 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130486.787426 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 189324.017101 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 189324.017101 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34260 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3572 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.591265 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106949 # number of writebacks
system.iocache.writebacks::total 106949 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242967981 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1246312981 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8610798466 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8610798466 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1242967981 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1246531981 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1242967981 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1246531981 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139549.565623 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 139346.263529 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80486.787426 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80486.787426 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1172651 # number of replacements
system.l2c.tags.tagsinuse 63896.612844 # Cycle average of tags in use
system.l2c.tags.total_refs 5899189 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1234288 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.779427 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 19626.342189 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 209.741305 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 250.506537 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 6148.160419 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 12486.088901 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 12942.693356 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 77.886538 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 86.786571 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4894.205028 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3546.886464 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3627.315534 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.299474 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003200 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003822 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.093813 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.190523 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.197490 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001188 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.074680 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.054121 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055348 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.974985 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 12177 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 211 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 49249 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 56 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 1468 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 3502 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 7139 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1696 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 11834 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 35465 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.185806 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003220 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.751480 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 69068672 # Number of tag accesses
system.l2c.tags.data_accesses 69068672 # Number of data accesses
system.l2c.Writeback_hits::writebacks 2213157 # number of Writeback hits
system.l2c.Writeback_hits::total 2213157 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 26227 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 30963 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 57190 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5791 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 6000 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11791 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 170699 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 173368 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 344067 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6059 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4018 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 717194 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 567434 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 309455 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6450 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4624 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 697524 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 530409 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 314319 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 3157486 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6059 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4018 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 717194 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 738133 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 309455 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6450 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4624 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 697524 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 703777 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 314319 # number of demand (read+write) hits
system.l2c.demand_hits::total 3501553 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6059 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4018 # number of overall hits
system.l2c.overall_hits::cpu0.inst 717194 # number of overall hits
system.l2c.overall_hits::cpu0.data 738133 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 309455 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6450 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4624 # number of overall hits
system.l2c.overall_hits::cpu1.inst 697524 # number of overall hits
system.l2c.overall_hits::cpu1.data 703777 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 314319 # number of overall hits
system.l2c.overall_hits::total 3501553 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 46094 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 42278 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 88372 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 9356 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 8640 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 17996 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 470394 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 130669 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 601063 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1196 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 55388 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 120389 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1070 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 55224 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 85443 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 623362 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1196 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 55388 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 590783 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1176 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1070 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 55224 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 216112 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) misses
system.l2c.demand_misses::total 1224425 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1196 # number of overall misses
system.l2c.overall_misses::cpu0.inst 55388 # number of overall misses
system.l2c.overall_misses::cpu0.data 590783 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 168332 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1176 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1070 # number of overall misses
system.l2c.overall_misses::cpu1.inst 55224 # number of overall misses
system.l2c.overall_misses::cpu1.data 216112 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 133806 # number of overall misses
system.l2c.overall_misses::total 1224425 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 737888500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 668601000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1406489500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 133423500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 126121000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 259544500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 68021517000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 17893316000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 85914833000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 182621000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 165049500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7432164500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 16649727500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 164644500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 152256000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7382488500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 11836491000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 93356372957 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 182621000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 165049500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 7432164500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 84671244500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 164644500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 152256000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 7382488500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 29729807000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 179271205957 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 182621000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 165049500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 7432164500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 84671244500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 164644500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 152256000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 7382488500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 29729807000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of overall miss cycles
system.l2c.overall_miss_latency::total 179271205957 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 2213157 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 2213157 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 72321 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 73241 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 145562 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 15147 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 14640 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 29787 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 641093 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 304037 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 945130 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7397 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5214 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 772582 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 687823 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 477787 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7626 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5694 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 752748 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 615852 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 448125 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3780848 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 7397 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 5214 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 772582 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1328916 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 477787 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 7626 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5694 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 752748 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 919889 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 448125 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4725978 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 7397 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 5214 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 772582 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1328916 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 477787 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 7626 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5694 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 752748 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 919889 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 448125 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4725978 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.637353 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.577245 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.607109 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.617680 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590164 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.604156 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.733738 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.429780 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.635958 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.229382 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.071692 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.175029 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.187917 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.073363 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.138740 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.164874 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.229382 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.071692 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.444560 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.187917 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.073363 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.234933 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.259084 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.229382 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.071692 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.444560 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.187917 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.073363 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.234933 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.259084 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16008.341650 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15814.395194 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15915.555832 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14260.741770 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14597.337963 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 14422.343854 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144605.409508 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136936.197568 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 142938.149578 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138001.254181 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134183.658915 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138299.408584 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142295.327103 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133682.610821 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138530.845125 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 149762.694802 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 146412.565863 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 146412.565863 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 2168 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 31 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 69.935484 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 894068 # number of writebacks
system.l2c.writebacks::total 894068 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 157 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 173 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 381 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 157 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 173 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 157 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 173 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 381 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 39667 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 39667 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 46094 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 42278 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 88372 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9356 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8640 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 17996 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 470394 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 130669 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 601063 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1337 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1196 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 55231 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 120360 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1070 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55051 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 85422 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 622981 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1337 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1196 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 55231 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 590754 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1176 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1070 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 55051 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 216091 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 1224044 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1337 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1196 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 55231 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 590754 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1176 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1070 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 55051 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 216091 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 1224044 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23508 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 90534 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 38054 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 46080 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 128588 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3387465005 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3115331505 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 6502796510 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 715527500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 661381001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 1376908501 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 63317577000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16586626000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 79904203000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153089500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6862441500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 15441020000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141556000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6812739500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10979665500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 87082118457 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153089500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 6862441500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 78758597000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141556000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 6812739500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 27566291500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 166986321457 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153089500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 6862441500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 78758597000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141556000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 6812739500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 27566291500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 166986321457 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2064046000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9850500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3446902500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 11417239000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154023500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3385027500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5539051000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4218069500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9850500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6831930000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 16956290000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.637353 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.577245 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.607109 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.617680 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590164 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604156 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733738 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.429780 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.635958 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174987 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.138705 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.164773 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.259003 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.259003 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73490.367618 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73686.823052 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73584.353755 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76477.928602 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76548.726968 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76511.919371 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134605.409508 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126936.197568 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 132938.149578 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128290.295779 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128534.399803 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 139782.944355 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 90534 # Transaction distribution
system.membus.trans_dist::ReadResp 722459 # Transaction distribution
system.membus.trans_dist::WriteReq 38054 # Transaction distribution
system.membus.trans_dist::WriteResp 38054 # Transaction distribution
system.membus.trans_dist::Writeback 1001017 # Transaction distribution
system.membus.trans_dist::CleanEvict 217536 # Transaction distribution
system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution
system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 614073 # Transaction distribution
system.membus.trans_dist::ReadExResp 593351 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 620798 # Total snoops (count)
system.membus.snoop_fanout::samples 3413791 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3413791 # Request fanout histogram
system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2987756 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
|