path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.443139                       # Number of seconds simulated
sim_ticks                                47443139283500                       # Number of ticks simulated
final_tick                               47443139283500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 174986                       # Simulator instruction rate (inst/s)
host_op_rate                                   205797                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9320406551                       # Simulator tick rate (ticks/s)
host_mem_usage                                 765676                       # Number of bytes of host memory used
host_seconds                                  5090.24                       # Real time elapsed on the host
sim_insts                                   890723033                       # Number of instructions simulated
sim_ops                                    1047557701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       111744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        91648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7668224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13156952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     13340800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       149248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       146240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3865344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         11856672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     13765376                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        430976                       # Number of bytes read from this memory
system.physmem.bytes_read::total             64583224                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7668224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3865344                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11533568                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75782720                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75803536                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1746                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1432                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            119816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            205599                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       208450                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2332                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2285                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             60396                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            185275                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       215084                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6734                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1009149                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1184105                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1186708                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2355                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1932                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              161630                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              277320                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       281196                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3146                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3082                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               81473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              249913                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       290145                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9084                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1361276                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         161630                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          81473                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             243103                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1597338                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1597777                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1597338                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2355                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1932                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             161630                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             277759                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       281196                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3146                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3082                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              81473                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             249913                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       290145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9084                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2959053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1009149                       # Number of read requests accepted
system.physmem.writeReqs                      1850399                       # Number of write requests accepted
system.physmem.readBursts                     1009149                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1850399                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 64564224                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21312                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 115242304                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  64583224                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              118279760                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      333                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   49721                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         115106                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               57845                       # Per bank write bursts
system.physmem.perBankRdBursts::1               61929                       # Per bank write bursts
system.physmem.perBankRdBursts::2               56818                       # Per bank write bursts
system.physmem.perBankRdBursts::3               63723                       # Per bank write bursts
system.physmem.perBankRdBursts::4               61880                       # Per bank write bursts
system.physmem.perBankRdBursts::5               68171                       # Per bank write bursts
system.physmem.perBankRdBursts::6               59739                       # Per bank write bursts
system.physmem.perBankRdBursts::7               60869                       # Per bank write bursts
system.physmem.perBankRdBursts::8               54876                       # Per bank write bursts
system.physmem.perBankRdBursts::9              108415                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50407                       # Per bank write bursts
system.physmem.perBankRdBursts::11              61358                       # Per bank write bursts
system.physmem.perBankRdBursts::12              58228                       # Per bank write bursts
system.physmem.perBankRdBursts::13              64090                       # Per bank write bursts
system.physmem.perBankRdBursts::14              57873                       # Per bank write bursts
system.physmem.perBankRdBursts::15              62595                       # Per bank write bursts
system.physmem.perBankWrBursts::0              107469                       # Per bank write bursts
system.physmem.perBankWrBursts::1              113594                       # Per bank write bursts
system.physmem.perBankWrBursts::2              115011                       # Per bank write bursts
system.physmem.perBankWrBursts::3              118413                       # Per bank write bursts
system.physmem.perBankWrBursts::4              118243                       # Per bank write bursts
system.physmem.perBankWrBursts::5              118449                       # Per bank write bursts
system.physmem.perBankWrBursts::6              111339                       # Per bank write bursts
system.physmem.perBankWrBursts::7              115322                       # Per bank write bursts
system.physmem.perBankWrBursts::8              110047                       # Per bank write bursts
system.physmem.perBankWrBursts::9              111027                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102767                       # Per bank write bursts
system.physmem.perBankWrBursts::11             112058                       # Per bank write bursts
system.physmem.perBankWrBursts::12             108184                       # Per bank write bursts
system.physmem.perBankWrBursts::13             112341                       # Per bank write bursts
system.physmem.perBankWrBursts::14             110504                       # Per bank write bursts
system.physmem.perBankWrBursts::15             115893                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         251                       # Number of times write queue was full causing retry
system.physmem.totGap                    47443137361000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1009107                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1847796                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    676531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    118770                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     46489                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     34633                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     29357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     26883                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     24732                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     22204                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18862                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      5388                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      235                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       73                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    43843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    64070                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    91575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   102673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   109951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   108175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   103872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    98771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    95896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    92750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    92610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   110859                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    98695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    94070                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   109570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    97266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    90790                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    87057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     7476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     6313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     6611                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     8079                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     7980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     6674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     6184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     6061                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     5542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     5221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3055                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1034                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      832                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1017757                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      176.667963                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     107.708761                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     246.723752                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         648817     63.75%     63.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       197916     19.45%     83.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        48918      4.81%     88.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23519      2.31%     90.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        17229      1.69%     92.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11413      1.12%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8164      0.80%     93.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7432      0.73%     94.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        54349      5.34%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1017757                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         78960                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.776165                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      140.389446                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          78957    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           78960                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         78960                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.804724                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.151306                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.211366                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           71201     90.17%     90.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47            3689      4.67%     94.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63            1610      2.04%     96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79             798      1.01%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             435      0.55%     98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            299      0.38%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           436      0.55%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           198      0.25%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            63      0.08%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            19      0.02%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            61      0.08%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            31      0.04%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            15      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             6      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             4      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             5      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             7      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             4      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             9      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             8      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             9      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            14      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             5      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             4      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           78960                       # Writes before turning the bus around for reads
system.physmem.totQLat                    36416381887                       # Total ticks spent queuing
system.physmem.totMemAccLat               55331681887                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5044080000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       36098.14                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  54848.14                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.36                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.43                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.36                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.49                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
system.physmem.readRowHits                     756126                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1035585                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.95                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.51                       # Row buffer hit rate for writes
system.physmem.avgGap                     16591131.66                       # Average gap between requests
system.physmem.pageHitRate                      63.77                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3944550960                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2152284750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3829511400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5947512480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3098754740640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1192681206900                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27419667632250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31726977439380                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.736993                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45614623336779                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1584230440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    244280410221                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3749639040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2045934000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4039144200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5720654160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3098754740640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1188668792790                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27423187293750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31726166198580                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.719894                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45620445429017                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1584230440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    238458431983                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          576                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          576                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             26                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               28                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           12                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              130059643                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         92054393                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5970282                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            98035548                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               70777475                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.195725                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               15296635                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1065115                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   268213                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               268213                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8180                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        73055                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       268213                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         268213    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       268213                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        81235                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        80487     99.08%     99.08% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          639      0.79%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           31      0.04%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           33      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           28      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        81235                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    788586204                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      788586204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    788586204                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        73055     89.93%     89.93% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         8180     10.07%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        81235                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       268213                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       268213                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        81235                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        81235                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       349448                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    82876233                       # DTB read hits
system.cpu0.dtb.read_misses                    221834                       # DTB read misses
system.cpu0.dtb.write_hits                   73950839                       # DTB write hits
system.cpu0.dtb.write_misses                    46379                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   33850                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     2174                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9634                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10897                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83098067                       # DTB read accesses
system.cpu0.dtb.write_accesses               73997218                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        156827072                       # DTB hits
system.cpu0.dtb.misses                         268213                       # DTB misses
system.cpu0.dtb.accesses                    157095285                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    59559                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                59559                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          562                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52025                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        59559                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          59559    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        59559                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        52587                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        47969     91.22%     91.22% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535         3703      7.04%     98.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          280      0.53%     98.79% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071          523      0.99%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839           24      0.05%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607           24      0.05%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           27      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143           16      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            8      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        52587                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    787865704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      787865704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    787865704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        52025     98.93%     98.93% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          562      1.07%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        52587                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        59559                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        59559                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52587                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52587                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       112146                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   232580630                       # ITB inst hits
system.cpu0.itb.inst_misses                     59559                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   23871                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   192056                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               232640189                       # ITB inst accesses
system.cpu0.itb.hits                        232580630                       # DTB hits
system.cpu0.itb.misses                          59559                       # DTB misses
system.cpu0.itb.accesses                    232640189                       # DTB accesses
system.cpu0.numCycles                       928928804                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  429144762                       # Number of instructions committed
system.cpu0.committedOps                    504441860                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     43734034                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     3788                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 93957994041                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.164605                       # CPI: cycles per instruction
system.cpu0.ipc                              0.461978                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   12678                       # number of quiesce instructions executed
system.cpu0.tickCycles                      694752800                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      234176004                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements          5394073                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.331401                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          148625740                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5394584                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.550918                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       5096417500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.331401                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938147                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.938147                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        316412315                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       316412315                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     75879605                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       75879605                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     68405292                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      68405292                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       266627                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       266627                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       249000                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       249000                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1685353                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1685353                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1648257                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1648257                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    144284897                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       144284897                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    144551524                       # number of overall hits
system.cpu0.dcache.overall_hits::total      144551524                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3254530                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3254530                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2315784                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2315784                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       640707                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       640707                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       788472                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       788472                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       144645                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       144645                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       180684                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       180684                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5570314                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5570314                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6211021                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6211021                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  49481056746                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  49481056746                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  45032988844                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  45032988844                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  32697185728                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  32697185728                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2134918217                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2134918217                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3848217698                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   3848217698                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3587000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3587000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  94514045590                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  94514045590                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  94514045590                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  94514045590                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     79134135                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     79134135                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     70721076                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     70721076                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       907334                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       907334                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1037472                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1037472                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1829998                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1829998                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1828941                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1828941                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    149855211                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    149855211                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    150762545                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    150762545                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041127                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.041127                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032745                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.032745                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.706142                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.706142                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.759994                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.759994                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079041                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079041                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098792                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098792                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037171                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.037171                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041197                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.041197                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15203.748850                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15203.748850                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19446.109328                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41469.051188                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14759.709751                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21298.054604                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3714069                       # number of writebacks
system.cpu0.dcache.writebacks::total          3714069                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       414551                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       414551                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       973091                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       973091                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data           89                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total           89                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40213                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40213                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           42                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           42                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1387642                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1387642                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1387642                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1387642                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2839979                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2839979                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1342693                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1342693                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       635024                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       635024                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       788383                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       788383                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       104432                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       104432                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       180642                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       180642                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4182672                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4182672                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4817696                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4817696                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37224821633                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  37224821633                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  24320285408                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  24320285408                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14430000107                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14430000107                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  31505168022                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  31505168022                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1352929391                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1352929391                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3566593771                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3566593771                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3248500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3248500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61545107041                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  61545107041                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75975107148                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  75975107148                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5918601247                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5918601247                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5692373000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5692373000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11610974247                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11610974247                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035888                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035888                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018986                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018986                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.699879                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.699879                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.759908                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.759908                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057067                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057067                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098769                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098769                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027911                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027911                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031956                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031956                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          9298569                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.930207                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          223083541                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9299081                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            23.989848                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      24039613250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.930207                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999864                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          423                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        474064354                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       474064354                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    223083541                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      223083541                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    223083541                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       223083541                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    223083541                       # number of overall hits
system.cpu0.icache.overall_hits::total      223083541                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9299091                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9299091                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9299091                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9299091                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9299091                       # number of overall misses
system.cpu0.icache.overall_misses::total      9299091                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92099739258                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  92099739258                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  92099739258                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  92099739258                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  92099739258                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  92099739258                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    232382632                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    232382632                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    232382632                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    232382632                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    232382632                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    232382632                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040016                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.040016                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040016                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.040016                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040016                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.040016                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9904.165822                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9904.165822                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9904.165822                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9904.165822                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9904.165822                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9904.165822                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9299091                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9299091                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9299091                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9299091                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9299091                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9299091                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  82773169690                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  82773169690                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  82773169690                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  82773169690                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  82773169690                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  82773169690                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4833897250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   4833897250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040016                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.040016                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.040016                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8901.210848                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8901.210848                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8901.210848                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7190203                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7193896                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         3174                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       922256                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2625541                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15991.413435                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          14807300                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2641343                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.605974                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5822698500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4879.764539                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    24.400359                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    12.549912                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  6476.155414                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3443.547426                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1154.995785                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.297837                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001489                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000766                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.395273                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.210177                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.070495                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.976038                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          899                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14803                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          131                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          212                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          261                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           49                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          584                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3987                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7940                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2205                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.054871                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.903503                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       317363753                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      317363753                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       462963                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       140724                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      8558678                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2632719                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total      11795084                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3714063                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3714063                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       203687                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       203687                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       102333                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       102333                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31948                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        31948                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       859061                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       859061                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       462963                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       140724                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      8558678                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3491780                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       12654145                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       462963                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       140724                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      8558678                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3491780                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      12654145                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10993                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8048                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       740412                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       946440                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1705893                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       583142                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       583142                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       124112                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       124112                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       148691                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       148691                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       269272                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       269272                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10993                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8048                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       740412                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1215712                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1975165                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10993                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8048                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       740412                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1215712                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1975165                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    390640720                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    300789761                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  22448225702                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  32185912694                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  55325568877                       # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    214128828                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    214128828                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2731788344                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2731788344                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3090531448                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3090531448                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3176498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3176498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13196588662                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  13196588662                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    390640720                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    300789761                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22448225702                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  45382501356                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  68522157539                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    390640720                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    300789761                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22448225702                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  45382501356                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  68522157539                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       473956                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       148772                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      9299090                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3579159                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total     13500977                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3714064                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3714064                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       786829                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       786829                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       226445                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       226445                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       180639                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       180639                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1128333                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1128333                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       473956                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       148772                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9299090                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4707492                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     14629310                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       473956                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       148772                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9299090                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4707492                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     14629310                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.023194                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.054096                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.079622                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.264431                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.126353                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.741129                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.741129                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.548089                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.548089                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823139                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823139                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.238646                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.238646                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.023194                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.054096                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079622                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.258250                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.135014                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.023194                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.054096                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079622                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.258250                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.135014                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35535.406168                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37374.473285                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30318.560075                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34007.346154                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32432.027611                       # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   367.198432                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   367.198432                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22010.670556                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22010.670556                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20784.926109                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.926109                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1058832.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1058832.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49008.395459                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49008.395459                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35535.406168                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37374.473285                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30318.560075                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37329.977294                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 34691.865003                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35535.406168                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37374.473285                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30318.560075                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37329.977294                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 34691.865003                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           99                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           99                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1355884                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1355884                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst            6                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          800                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          808                       # number of ReadReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           23                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           23                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         7927                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         7927                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         8727                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         8735                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            6                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         8727                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         8735                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10992                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8047                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       740406                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       945640                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1705085                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       695861                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       695861                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       583119                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       583119                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       124112                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       124112                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       148691                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       148691                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       261345                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       261345                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10992                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8047                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       740406                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1206985                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1966430                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10992                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8047                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       740406                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1206985                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       695861                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2662291                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    318665266                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    248030007                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  17610392548                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  25914267732                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  44091355553                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  32596842182                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  32596842182                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  25478427229                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25478427229                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2526518712                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2526518712                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2211223584                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2211223584                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2721498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2721498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10434978340                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10434978340                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    318665266                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    248030007                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17610392548                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  36349246072                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  54526333893                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    318665266                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    248030007                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17610392548                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  36349246072                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  32596842182                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  87123176075                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5652021253                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10043092003                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5443565000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5443565000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11095586253                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15486657003                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.264207                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.126293                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.741100                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.741100                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.548089                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.548089                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823139                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823139                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.231620                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231620                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256397                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.134417                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256397                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.181983                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       907166                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       907166                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      16236238                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     13810704                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        33172                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        33172                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      3714064                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1025800                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1145042                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       786829                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       475552                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       336189                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       478151                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           52                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1267323                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1138296                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18702794                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15835764                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       326673                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1038123                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         35903354                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    598489344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    596885449                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1190176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3791640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1200356609                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4763261                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     24114639                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       3.184867                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.388190                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3          19656632     81.51%     81.51% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4           4458007     18.49%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      24114639                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   14405309409                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    207723992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14053020534                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7776245419                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    178137962                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    564500428                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              140284857                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         99939687                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6358953                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups           105820632                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               77032296                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            72.795158                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16359380                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect           1035022                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   298079                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               298079                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11270                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91179                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       298079                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         298079    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       298079                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       102449                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       101103     98.69%     98.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1144      1.12%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           36      0.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           71      0.07%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           73      0.07%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       102449                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1267166444                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1267166444    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1267166444                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        91179     89.00%     89.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        11270     11.00%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       102449                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       298079                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       298079                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       102449                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       102449                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       400528                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    91176680                       # DTB read hits
system.cpu1.dtb.read_misses                    248433                       # DTB read misses
system.cpu1.dtb.write_hits                   79002879                       # DTB write hits
system.cpu1.dtb.write_misses                    49646                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   41482                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      884                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7879                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11586                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                91425113                       # DTB read accesses
system.cpu1.dtb.write_accesses               79052525                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        170179559                       # DTB hits
system.cpu1.dtb.misses                         298079                       # DTB misses
system.cpu1.dtb.accesses                    170477638                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    68407                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                68407                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          609                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        58709                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        68407                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          68407    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        68407                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        59318                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        54668     92.16%     92.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         3100      5.23%     97.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          594      1.00%     98.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          801      1.35%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           32      0.05%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           14      0.02%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           58      0.10%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           21      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911            5      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        59318                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1266435944                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1266435944    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1266435944                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        58709     98.97%     98.97% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          609      1.03%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        59318                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        68407                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        68407                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        59318                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        59318                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       127725                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   251160195                       # ITB inst hits
system.cpu1.itb.inst_misses                     68407                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   30244                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   224879                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               251228602                       # ITB inst accesses
system.cpu1.itb.hits                        251160195                       # DTB hits
system.cpu1.itb.misses                          68407                       # DTB misses
system.cpu1.itb.accesses                    251228602                       # DTB accesses
system.cpu1.numCycles                       937856787                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  461578271                       # Number of instructions committed
system.cpu1.committedOps                    543115841                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     48137471                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     5811                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 93949323576                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.031848                       # CPI: cycles per instruction
system.cpu1.ipc                              0.492163                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5892                       # number of quiesce instructions executed
system.cpu1.tickCycles                      744774671                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      193082116                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements          5501509                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          462.401458                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          161882040                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5502021                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.422287                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8380046591500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   462.401458                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.903128                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.903128                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        343173973                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       343173973                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     83605080                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       83605080                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     73820570                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      73820570                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       234480                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       234480                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        75463                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total        75463                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1844270                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1844270                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1832447                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1832447                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    157425650                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       157425650                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    157660130                       # number of overall hits
system.cpu1.dcache.overall_hits::total      157660130                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3592418                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3592418                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2291328                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2291328                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       658469                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       658469                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       456956                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       456956                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       185722                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       185722                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       196000                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       196000                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5883746                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5883746                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6542215                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6542215                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  54049590884                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  54049590884                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  39638005604                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  39638005604                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  12577649145                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  12577649145                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2799761413                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2799761413                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4076020251                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4076020251                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2567000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2567000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  93687596488                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  93687596488                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  93687596488                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  93687596488                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     87197498                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     87197498                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     76111898                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     76111898                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       892949                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       892949                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       532419                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       532419                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2029992                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2029992                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2028447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2028447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    163309396                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    163309396                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    164202345                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    164202345                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041199                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.041199                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030105                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030105                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.737409                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.737409                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.858264                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.858264                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091489                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091489                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096626                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096626                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036028                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.036028                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039842                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.039842                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15045.462662                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15045.462662                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17299.140762                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17299.140762                       # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.858291                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.858291                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15075.012185                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15075.012185                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20796.021689                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20796.021689                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15923.120490                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15923.120490                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14320.470435                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14320.470435                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3514313                       # number of writebacks
system.cpu1.dcache.writebacks::total          3514313                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       402319                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       402319                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       938195                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       938195                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           62                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           62                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44601                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44601                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           41                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           41                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1340514                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1340514                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1340514                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1340514                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3190099                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3190099                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1353133                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1353133                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       658162                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       658162                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       456894                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       456894                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141121                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141121                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195959                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       195959                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4543232                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4543232                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5201394                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5201394                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41952700254                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41952700254                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21819340170                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21819340170                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13178817169                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13178817169                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  11885329605                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  11885329605                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1778237950                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1778237950                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3771476218                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3771476218                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2255500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2255500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63772040424                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  63772040424                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  76950857593                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  76950857593                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    517375000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    517375000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    587265498                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    587265498                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1104640498                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1104640498                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036585                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036585                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017778                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017778                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.737066                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.737066                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.858147                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.858147                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069518                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069518                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096605                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096605                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027820                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027820                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031677                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031677                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          9531492                       # number of replacements
system.cpu1.icache.tags.tagsinuse          507.211334                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          241397065                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          9532004                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            25.324902                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8370013399000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.211334                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990647                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.990647                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        511390144                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       511390144                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    241397065                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      241397065                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    241397065                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       241397065                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    241397065                       # number of overall hits
system.cpu1.icache.overall_hits::total      241397065                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      9532005                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      9532005                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      9532005                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       9532005                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      9532005                       # number of overall misses
system.cpu1.icache.overall_misses::total      9532005                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  94727843232                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  94727843232                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  94727843232                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  94727843232                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  94727843232                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  94727843232                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    250929070                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    250929070                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    250929070                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    250929070                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    250929070                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    250929070                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037987                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.037987                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037987                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.037987                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037987                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.037987                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9937.871752                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9937.871752                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9937.871752                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9937.871752                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9937.871752                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9937.871752                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9532005                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      9532005                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      9532005                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      9532005                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      9532005                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      9532005                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  85170319722                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  85170319722                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  85170319722                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  85170319722                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  85170319722                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  85170319722                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8117000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8117000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8117000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8117000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037987                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.037987                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.037987                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8935.194612                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8935.194612                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8935.194612                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7632700                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7634373                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         1426                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       974619                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2493350                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13598.009718                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          15504995                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2509448                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            6.178648                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9806309185500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5002.427380                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    85.119837                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.520686                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4382.194744                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3239.455000                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   801.292071                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.305324                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.005195                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005342                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.267468                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.197721                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048907                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.829957                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1340                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14690                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          958                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           41                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           27                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1230                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4980                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7916                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          444                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.081787                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.896606                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       320697996                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      320697996                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       533308                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       157578                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      8712936                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2963890                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total      12367712                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3514312                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3514312                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       195589                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       195589                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        70594                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        70594                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        40360                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        40360                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       897925                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       897925                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       533308                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       157578                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8712936                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3861815                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       13265637                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       533308                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       157578                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8712936                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3861815                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      13265637                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12573                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8955                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       819069                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data      1025149                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1865746                       # number of ReadReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       260149                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       260149                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       141488                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       141488                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       155591                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       155591                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       244809                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       244809                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12573                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8955                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       819069                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1269958                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2110555                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12573                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8955                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       819069                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1269958                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2110555                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    462714995                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    376910753                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  23725938333                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  33521266479                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  58086830560                       # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    226799088                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    226799088                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3089566814                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3089566814                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3237262107                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3237262107                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2205498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2205498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10480888835                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10480888835                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    462714995                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    376910753                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  23725938333                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  44002155314                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  68567719395                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    462714995                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    376910753                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  23725938333                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  44002155314                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  68567719395                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       545881                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       166533                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      9532005                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3989039                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total     14233458                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3514312                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3514312                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       455738                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       455738                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       212082                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       212082                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195951                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       195951                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1142734                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1142734                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       545881                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       166533                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      9532005                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5131773                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     15376192                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       545881                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       166533                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      9532005                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5131773                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     15376192                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023032                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053773                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.085928                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.256991                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.131082                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.570830                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.570830                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.667138                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.667138                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.794030                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.794030                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.214231                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.214231                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023032                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053773                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.085928                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.247470                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.137261                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023032                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053773                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.085928                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.247470                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.137261                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28966.959234                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32698.921307                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31133.300331                       # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   871.804574                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   871.804574                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21836.246282                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21836.246282                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20806.229840                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20806.229840                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275687.250000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275687.250000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42812.514389                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42812.514389                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28966.959234                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34648.512245                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32488.004053                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28966.959234                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34648.512245                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32488.004053                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1040490                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1040490                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          845                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          849                       # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            8                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            8                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7280                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         7280                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         8125                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         8129                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         8125                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         8129                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12572                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8954                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       819067                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data      1024304                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1864897                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       717839                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       717839                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       260141                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       260141                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       141488                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       141488                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       155591                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       155591                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237529                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       237529                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12572                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8954                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       819067                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1261833                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      2102426                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12572                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8954                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       819067                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1261833                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       717839                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2820265                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    380310007                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    318025257                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  18380027667                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  26750668121                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  45829031052                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32395588345                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32395588345                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   8350999174                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   8350999174                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2765649497                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2765649497                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2300876668                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2300876668                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1886998                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1886998                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7923837459                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7923837459                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    380310007                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    318025257                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  18380027667                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34674505580                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  53752868511                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    380310007                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    318025257                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  18380027667                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34674505580                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32395588345                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  86148456856                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7360000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    476808000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    484168000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    548574002                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    548574002                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7360000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1025382002                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1032742002                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.256780                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.131022                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.570813                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.570813                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.667138                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.667138                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.794030                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.794030                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207860                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207860                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245886                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136733                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245886                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183418                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26115.946165                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32101.818529                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14787.980462                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 235874.750000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33359.452778                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27479.472783                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25567.068002                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      16743915                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     14472665                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         5158                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         5158                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3514312                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1035959                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1137929                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       455738                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       448749                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       344575                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       466415                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           78                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1299611                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1147815                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     19064189                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15671741                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       370835                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1205745                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         36312510                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    610054016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    588145619                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1332264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4367048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1203898947                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4911557                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     24519969                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       3.188170                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.390848                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3          19906035     81.18%     81.18% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4           4613934     18.82%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      24519969                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   13930930666                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    160378480                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  14310919255                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8198844119                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    204674963                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    660298903                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136954                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29970                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106984                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47756                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122846                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354666                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47776                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155884                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7355312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7513282                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36279000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            22103000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           609062244                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92879000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148791282                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              171000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115866                       # number of replacements
system.iocache.tags.tagsinuse               11.306200                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115882                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9129676346000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.405197                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.901004                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462825                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.243813                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706638                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1043187                       # Number of tag accesses
system.iocache.tags.data_accesses             1043187                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8886                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8923                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106984                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106984                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8886                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8926                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8886                       # number of overall misses
system.iocache.overall_misses::total             8926                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5190000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1626687073                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1631877073                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19941362889                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19941362889                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5559000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1626687073                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1632246073                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5559000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1626687073                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1632246073                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8886                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8923                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106984                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106984                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8886                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8926                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8886                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8926                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182884.352012                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       138975                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 183061.790795                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 182864.225073                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       138975                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 183061.790795                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 182864.225073                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        111964                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16416                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.820419                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106950                       # number of writebacks
system.iocache.writebacks::total               106950                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8886                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8923                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106984                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106984                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8886                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8926                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8886                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8926                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3264000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1163415573                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1166679573                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14378130953                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14378130953                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3477000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1163415573                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1166892573                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3477000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1163415573                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1166892573                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88216.216216                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130926.803174                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 130749.699989                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134395.152107                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134395.152107                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 130926.803174                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 130729.618306                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 130729.618306                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1418934                       # number of replacements
system.l2c.tags.tagsinuse                64475.403646                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4887849                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1480275                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.301987                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8811587000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   16720.464314                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     9.676845                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     2.082484                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3893.344537                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5310.090712                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3772.998059                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   379.879752                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   518.261056                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4648.220337                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    11740.962883                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17479.422666                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.255134                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000148                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000032                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.059408                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.081026                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.057571                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005797                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.007908                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.070926                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.179153                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.266715                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.983817                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9966                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          213                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        51162                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           69                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          272                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         1682                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         7941                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          195                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1978                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3        11118                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        37794                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.152069                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003250                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.780670                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 63367915                       # Number of tag accesses
system.l2c.tags.data_accesses                63367915                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6326                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4773                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             672724                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             551559                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       298336                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6350                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4103                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             758519                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             584378                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       311165                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                3198233                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2396374                       # number of Writeback hits
system.l2c.Writeback_hits::total              2396374                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       132089                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       134441                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       266530                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           29493                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           27736                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               57229                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          5838                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          6131                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11969                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            53859                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            51185                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105044                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6326                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4773                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              672724                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              605418                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       298336                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6350                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4103                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              758519                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              635563                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       311165                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3303277                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6326                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4773                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             672724                       # number of overall hits
system.l2c.overall_hits::cpu0.data             605418                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       298336                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6350                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4103                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             758519                       # number of overall hits
system.l2c.overall_hits::cpu1.data             635563                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       311165                       # number of overall hits
system.l2c.overall_hits::total                3303277                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1746                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1432                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            67682                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           130428                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       208623                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2332                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2285                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            60547                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           132466                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       215131                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               822672                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       442954                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       116624                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       559578                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         45697                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         44658                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             90355                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         8940                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8873                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           17813                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          77535                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          55004                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             132539                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1746                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1432                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             67682                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            207963                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       208623                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2332                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             60547                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            187470                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       215131                       # number of demand (read+write) misses
system.l2c.demand_misses::total                955211                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1746                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1432                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            67682                       # number of overall misses
system.l2c.overall_misses::cpu0.data           207963                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       208623                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2332                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2285                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            60547                       # number of overall misses
system.l2c.overall_misses::cpu1.data           187470                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       215131                       # number of overall misses
system.l2c.overall_misses::total               955211                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    161430014                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    133523499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   5728187863                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  12139315223                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  27793617273                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    206166757                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    199956257                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   5085068912                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  11808697846                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  27463393997                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    90719357641                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     48375493                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     41411697                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total     89787190                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    259807838                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    288996819                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    548804657                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     49028949                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     59371116                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    108400065                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6929592651                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4617668591                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11547261242                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    161430014                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    133523499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5728187863                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19068907874                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  27793617273                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    206166757                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    199956257                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5085068912                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16426366437                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27463393997                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    102266618883                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    161430014                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    133523499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5728187863                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19068907874                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  27793617273                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    206166757                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    199956257                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5085068912                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16426366437                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27463393997                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   102266618883                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8072                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6205                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         740406                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         681987                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       506959                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         8682                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6388                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         819066                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         716844                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       526296                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            4020905                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2396374                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2396374                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       575043                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       251065                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       826108                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        75190                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        72394                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          147584                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        14778                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        15004                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         29782                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       131394                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       106189                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           237583                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8072                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6205                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          740406                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          813381                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       506959                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8682                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          819066                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          823033                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       526296                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4258488                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8072                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6205                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         740406                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         813381                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       506959                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8682                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         819066                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         823033                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       526296                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4258488                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.230782                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.091412                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.191247                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.268602                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.357702                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.073922                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.184791                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.204599                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.770297                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.464517                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.677367                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.607754                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.616874                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.612228                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.604953                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.591376                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.598113                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.590095                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.517982                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.557864                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.230782                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.091412                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.255677                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.268602                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.357702                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.073922                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.227779                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.224308                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.230782                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.091412                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.255677                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.268602                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.357702                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.073922                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.227779                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.224308                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92457.052692                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93242.666899                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84633.844493                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 93072.923168                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88407.700257                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87508.208753                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83985.480899                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 89145.122869                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 110274.031012                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   109.211099                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   355.087263                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total   160.455182                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5685.446266                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6471.333669                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6073.871474                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5484.222483                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6691.211090                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  6085.446865                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89373.736390                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83951.505181                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 87123.497552                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92457.052692                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93242.666899                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84633.844493                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 91693.752610                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88407.700257                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87508.208753                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83985.480899                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 87621.307073                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 107061.810305                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92457.052692                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93242.666899                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84633.844493                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 91693.752610                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88407.700257                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87508.208753                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83985.480899                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 87621.307073                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 107061.810305                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               855                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    106.875000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1077155                       # number of writebacks
system.l2c.writebacks::total                  1077155                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst           162                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            20                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst           217                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               417                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            162                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             20                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            217                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                417                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           162                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            20                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           217                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               417                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1746                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1432                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        67520                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       130408                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       208623                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2332                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2285                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        60330                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       132448                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       215131                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          822255                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       442954                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       116624                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       559578                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        45697                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        44658                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        90355                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         8940                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8873                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        17813                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        77535                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        55004                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        132539                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1746                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1432                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        67520                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       207943                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       208623                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2332                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2285                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        60330                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       187452                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       215131                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           954794                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1746                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1432                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        67520                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       207943                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       208623                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2332                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2285                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        60330                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       187452                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       215131                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          954794                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    139394486                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    115450499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   4870282387                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10505515777                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  25233483205                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    176791243                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    171176743                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   4312003588                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data  10147787904                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24818336697                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  80490222529                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  14873961513                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   3737572303                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  18611533816                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    814223914                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    794539944                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1608763858                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    159553413                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    157960839                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    317514252                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5960412849                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3929978409                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9890391258                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    139394486                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    115450499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   4870282387                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  16465928626                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  25233483205                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    176791243                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    171176743                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4312003588                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14077766313                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  24818336697                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  90380613787                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    139394486                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    115450499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   4870282387                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  16465928626                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25233483205                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    176791243                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    171176743                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4312003588                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14077766313                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24818336697                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  90380613787                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5001418750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5293500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    377070000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8571795000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4829205000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    452800000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5282005000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9830623750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5293500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    829870000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13853800000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.216303                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.191218                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.357702                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.184765                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.204495                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.770297                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.464517                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.677367                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.607754                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.616874                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.612228                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.604953                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.591376                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.598113                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.590095                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.517982                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.557864                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.216303                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.255653                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.357702                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.227758                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.224210                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.216303                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.255653                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.357702                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.227758                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.224210                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80558.829037                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76617.147137                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 97889.611530                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33579.020650                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32048.054457                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33259.945559                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.885507                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17791.659815                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17804.923446                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17847.137919                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17802.416206                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17824.861169                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76873.835674                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71448.956603                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 74622.497967                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79184.818080                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75100.646101                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 94659.804929                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79184.818080                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75100.646101                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 94659.804929                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              921958                       # Transaction distribution
system.membus.trans_dist::ReadResp             921958                       # Transaction distribution
system.membus.trans_dist::WriteReq              38330                       # Transaction distribution
system.membus.trans_dist::WriteResp             38330                       # Transaction distribution
system.membus.trans_dist::Writeback           1184105                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       663691                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       663691                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           435500                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         292205                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          115129                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
system.membus.trans_dist::ReadExReq            144960                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128452                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25278                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5060662                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5208838                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336578                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       336578                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5545416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    168740232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    168947996                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14122752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14122752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               183070748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           632037                       # Total snoops (count)
system.membus.snoop_fanout::samples           3551920                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3551920    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3551920                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109974000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               33484                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21181500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         10917620106                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6186347625                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          152234718                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            4966231                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4959010                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38330                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38330                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2396374                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       933256                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       826108                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          485771                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        304174                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         789945                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          119                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           295867                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295867                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7796872                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6899953                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              14696825                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    260005833                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    222466259                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              482472092                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1634381                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9291173                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.012493                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.111071                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                9175099     98.75%     98.75% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 116074      1.25%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9291173                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8184497542                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2554500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4445775595                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4394903352                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------