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|
---------- Begin Simulation Statistics ----------
sim_seconds 47.276773 # Number of seconds simulated
sim_ticks 47276772827000 # Number of ticks simulated
final_tick 47276772827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 146674 # Simulator instruction rate (inst/s)
host_op_rate 172507 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7728246229 # Simulator tick rate (ticks/s)
host_mem_usage 772984 # Number of bytes of host memory used
host_seconds 6117.40 # Real time elapsed on the host
sim_insts 897262562 # Number of instructions simulated
sim_ops 1055295890 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 117376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 90560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 7953664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 13400200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 16005120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 165760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 157376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3942400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 13075216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 14708224 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 454784 # Number of bytes read from this memory
system.physmem.bytes_read::total 70070680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 7953664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3942400 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 11896064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 81443392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 81463976 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1834 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1415 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 124276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 209391 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 250080 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2590 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2459 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 61600 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 204313 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 229816 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 7106 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1094880 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1272553 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1275127 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2483 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1916 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 168236 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 283442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 338541 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3329 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 83390 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 276567 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 311109 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9620 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1482138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 168236 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 83390 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 251626 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1722694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1723129 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1722694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2483 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1916 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 168236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 283877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 338541 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 83390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 276568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 311109 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9620 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3205266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1094880 # Number of read requests accepted
system.physmem.writeReqs 1275127 # Number of write requests accepted
system.physmem.readBursts 1094880 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1275127 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 70042240 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 30080 # Total number of bytes read from write queue
system.physmem.bytesWritten 81461504 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 70070680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 81463976 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 470 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 60604 # Per bank write bursts
system.physmem.perBankRdBursts::1 71691 # Per bank write bursts
system.physmem.perBankRdBursts::2 59265 # Per bank write bursts
system.physmem.perBankRdBursts::3 66946 # Per bank write bursts
system.physmem.perBankRdBursts::4 67906 # Per bank write bursts
system.physmem.perBankRdBursts::5 80109 # Per bank write bursts
system.physmem.perBankRdBursts::6 61949 # Per bank write bursts
system.physmem.perBankRdBursts::7 69447 # Per bank write bursts
system.physmem.perBankRdBursts::8 60494 # Per bank write bursts
system.physmem.perBankRdBursts::9 115448 # Per bank write bursts
system.physmem.perBankRdBursts::10 56514 # Per bank write bursts
system.physmem.perBankRdBursts::11 69665 # Per bank write bursts
system.physmem.perBankRdBursts::12 63387 # Per bank write bursts
system.physmem.perBankRdBursts::13 66346 # Per bank write bursts
system.physmem.perBankRdBursts::14 64421 # Per bank write bursts
system.physmem.perBankRdBursts::15 60218 # Per bank write bursts
system.physmem.perBankWrBursts::0 77101 # Per bank write bursts
system.physmem.perBankWrBursts::1 84577 # Per bank write bursts
system.physmem.perBankWrBursts::2 74746 # Per bank write bursts
system.physmem.perBankWrBursts::3 81276 # Per bank write bursts
system.physmem.perBankWrBursts::4 79990 # Per bank write bursts
system.physmem.perBankWrBursts::5 87328 # Per bank write bursts
system.physmem.perBankWrBursts::6 77464 # Per bank write bursts
system.physmem.perBankWrBursts::7 81707 # Per bank write bursts
system.physmem.perBankWrBursts::8 78209 # Per bank write bursts
system.physmem.perBankWrBursts::9 81569 # Per bank write bursts
system.physmem.perBankWrBursts::10 73819 # Per bank write bursts
system.physmem.perBankWrBursts::11 80687 # Per bank write bursts
system.physmem.perBankWrBursts::12 78674 # Per bank write bursts
system.physmem.perBankWrBursts::13 80970 # Per bank write bursts
system.physmem.perBankWrBursts::14 77560 # Per bank write bursts
system.physmem.perBankWrBursts::15 77159 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 62 # Number of times write queue was full causing retry
system.physmem.totGap 47276770796500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1094850 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1272553 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 725931 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 132585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 49587 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 38066 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 32959 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 30077 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 28140 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 24582 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 22148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1854 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 970 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 328 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 280 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 26459 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 34937 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 52906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 67814 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 70802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 73289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 75619 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 78304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 78281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 81577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 85157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 81436 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 80619 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 87129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 77597 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 71470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 67901 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2425 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1908 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1516 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 902 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 339 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 212 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1013795 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 149.441747 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 100.507639 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 197.056675 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 662057 65.30% 65.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 208347 20.55% 85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 52181 5.15% 91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23884 2.36% 93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 17639 1.74% 95.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11113 1.10% 96.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7357 0.73% 96.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6249 0.62% 97.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24968 2.46% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1013795 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 63452 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.247415 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 156.483425 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 63450 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 63452 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 63452 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.059825 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.482738 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.878895 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 55385 87.29% 87.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 2264 3.57% 90.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 727 1.15% 92.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 608 0.96% 92.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 1019 1.61% 94.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 457 0.72% 95.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 338 0.53% 95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 295 0.46% 96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 198 0.31% 96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 179 0.28% 96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 127 0.20% 97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 154 0.24% 97.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 464 0.73% 98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 118 0.19% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 142 0.22% 98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 119 0.19% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 89 0.14% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 71 0.11% 98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 72 0.11% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 80 0.13% 99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 103 0.16% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 73 0.12% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 46 0.07% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 54 0.09% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 48 0.08% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 39 0.06% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 53 0.08% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 25 0.04% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 49 0.08% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 20 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 13 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 6 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 63452 # Writes before turning the bus around for reads
system.physmem.totQLat 38795138463 # Total ticks spent queuing
system.physmem.totMemAccLat 59315325963 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5472050000 # Total ticks spent in databus transfers
system.physmem.avgQLat 35448.45 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 54198.45 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing
system.physmem.readRowHits 817920 # Number of row buffer hits during reads
system.physmem.writeRowHits 535530 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.07 # Row buffer hit rate for writes
system.physmem.avgGap 19947945.64 # Average gap between requests
system.physmem.pageHitRate 57.17 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3880003680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2117065500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4195752600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4174344720 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1190314271070 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27321927289500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31614497574750 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.711016 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45452122728628 # Time in different power states
system.physmem_0.memoryStateTime::REF 1578675280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 245973030122 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3784278960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2064834750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4340583000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4073632560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1186461286245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27325307092500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31613920555695 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.698811 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45457733356018 # Time in different power states
system.physmem_1.memoryStateTime::REF 1578675280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 240362584982 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 132137665 # Number of BP lookups
system.cpu0.branchPred.condPredicted 93617551 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5999845 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 98810350 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 69427031 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 70.262914 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15260285 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1044115 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 3387017 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2259695 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1127322 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 409659 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 271762 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 271762 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10351 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74846 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 271762 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 271762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 271762 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 85197 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 84296 98.94% 98.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 776 0.91% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 35 0.04% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 35 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 85197 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 74846 87.85% 87.85% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10351 12.15% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 85197 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271762 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271762 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 356959 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 82756248 # DTB read hits
system.cpu0.dtb.read_misses 224730 # DTB read misses
system.cpu0.dtb.write_hits 74117187 # DTB write hits
system.cpu0.dtb.write_misses 47032 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 34573 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 2108 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9506 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 11030 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 82980978 # DTB read accesses
system.cpu0.dtb.write_accesses 74164219 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 156873435 # DTB hits
system.cpu0.dtb.misses 271762 # DTB misses
system.cpu0.dtb.accesses 157145197 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 60398 # Table walker walks requested
system.cpu0.itb.walker.walksLong 60398 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 589 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51882 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 60398 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 60398 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 60398 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 52471 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 46836 89.26% 89.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 4750 9.05% 98.31% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 22 0.04% 98.36% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 772 1.47% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 15 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 26 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 9 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 52471 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 51882 98.88% 98.88% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 589 1.12% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 52471 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60398 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60398 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52471 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52471 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 112869 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 234456044 # ITB inst hits
system.cpu0.itb.inst_misses 60398 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 24118 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 160109 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 234516442 # ITB inst accesses
system.cpu0.itb.hits 234456044 # DTB hits
system.cpu0.itb.misses 60398 # DTB misses
system.cpu0.itb.accesses 234516442 # DTB accesses
system.cpu0.numPwrStateTransitions 8178 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 4089 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 11447226771.455124 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 162386644618.467285 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 2836 69.36% 69.36% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 1230 30.08% 99.44% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.51% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.56% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 14 0.34% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7470355608744 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 4089 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 469062558520 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 938130839 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 430200528 # Number of instructions committed
system.cpu0.committedOps 505771410 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 45690974 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 3904 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93616054941 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.180683 # CPI: cycles per instruction
system.cpu0.ipc 0.458572 # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu 351125189 69.42% 69.42% # Class of committed instruction
system.cpu0.op_class_0::IntMult 1073769 0.21% 69.64% # Class of committed instruction
system.cpu0.op_class_0::IntDiv 52983 0.01% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc 68782 0.01% 69.66% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction
system.cpu0.op_class_0::MemRead 79655364 15.75% 85.41% # Class of committed instruction
system.cpu0.op_class_0::MemWrite 73795280 14.59% 100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::total 505771410 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 4089 # number of quiesce instructions executed
system.cpu0.tickCycles 697846091 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 240284748 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 5497391 # number of replacements
system.cpu0.dcache.tags.tagsinuse 500.377946 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 148839422 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5497903 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.072035 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.377946 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977301 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.977301 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 316768421 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 316768421 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 75978032 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 75978032 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 68482955 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 68482955 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 264842 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 264842 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 244065 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 244065 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1687572 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1687572 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1654235 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1654235 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 144705052 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 144705052 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 144969894 # number of overall hits
system.cpu0.dcache.overall_hits::total 144969894 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3066734 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3066734 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2419958 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2419958 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670609 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 670609 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 786129 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 786129 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148878 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 148878 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 181031 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 181031 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 6272821 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 6272821 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6943430 # number of overall misses
system.cpu0.dcache.overall_misses::total 6943430 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47243422000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 47243422000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 49248110500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 49248110500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26231986000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 26231986000 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2187373500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2187373500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4323764500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4323764500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2754000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2754000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 122723518500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 122723518500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 79044766 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 79044766 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 70902913 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 70902913 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935451 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 935451 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1030194 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1030194 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1836450 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 1836450 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1835266 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1835266 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 150977873 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 150977873 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 151913324 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 151913324 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038797 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.038797 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.034131 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.034131 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716883 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716883 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763088 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763088 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081068 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081068 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098640 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098640 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045707 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045707 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 5497393 # number of writebacks
system.cpu0.dcache.writebacks::total 5497393 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200047 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 200047 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012976 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1012976 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 94 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 94 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39271 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39271 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 90 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 90 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1213117 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1213117 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1213117 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1213117 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2866687 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 2866687 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1406982 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1406982 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668415 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 668415 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 786035 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 786035 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109607 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 109607 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180941 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 180941 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5059704 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5059704 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5728119 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5728119 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20634 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42909 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39457015000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39457015000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27671793000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27671793000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15966528000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15966528000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25439405000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25439405000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1452927000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1452927000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4140525000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4140525000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2476500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2476500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92568213000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 92568213000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4015086500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4015086500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4015086500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4015086500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036267 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036267 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019844 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019844 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714538 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714538 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.762997 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.762997 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059684 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059684 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098591 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098591 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033513 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033513 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037706 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.037706 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 9280608 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.932285 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 225009210 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 9281120 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 24.243756 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 22204306000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932285 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 477861809 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 477861809 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 225009210 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 225009210 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 225009210 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 225009210 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 225009210 # number of overall hits
system.cpu0.icache.overall_hits::total 225009210 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 9281130 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 9281130 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 9281130 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 9281130 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 9281130 # number of overall misses
system.cpu0.icache.overall_misses::total 9281130 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94226606500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 94226606500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 94226606500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 94226606500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 94226606500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 94226606500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290340 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 234290340 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 234290340 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 234290340 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 234290340 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 234290340 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039614 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.039614 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039614 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.039614 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039614 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.039614 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10152.492908 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10152.492908 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 9280608 # number of writebacks
system.cpu0.icache.writebacks::total 9280608 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9281130 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 9281130 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 9281130 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 9281130 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 9281130 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 9281130 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89586042000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 89586042000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89586042000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 89586042000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89586042000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 89586042000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039614 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.039614 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.039614 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9652.492962 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7507862 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7509065 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 1069 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 942183 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2584098 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15590.889787 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 13248667 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2600019 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.095604 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15296.249521 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.752726 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.010194 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.877346 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.933609 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001343 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014214 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.951592 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 376 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15477 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 104 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 124 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 121 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1649 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4407 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3577 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022949 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.944641 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 507607175 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 507607175 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 496900 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154788 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 651688 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3675506 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3675506 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 11099665 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 11099665 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 891359 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 891359 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8598093 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 8598093 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2690347 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2690347 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202108 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 202108 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 496900 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154788 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 8598093 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3581706 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 12831487 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 496900 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154788 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 8598093 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3581706 # number of overall hits
system.cpu0.l2cache.overall_hits::total 12831487 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 19803 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9619 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 29422 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 245426 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 245426 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 180938 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 180938 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278613 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 278613 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 683036 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 683036 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953863 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 953863 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 581978 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 581978 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 19803 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9619 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 683036 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1232476 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 1944934 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 19803 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9619 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 683036 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1232476 # number of overall misses
system.cpu0.l2cache.overall_misses::total 1944934 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 614702000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 331371000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 946073000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 874372000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 874372000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295339000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295339000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2383999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2383999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13650875999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 13650875999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23732034500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23732034500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33660637494 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33660637494 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333947500 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 333947500 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 614702000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 331371000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23732034500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 47311513493 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 71989620993 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 614702000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 331371000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23732034500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 47311513493 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 71989620993 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 516703 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164407 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 681110 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3675506 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 3675506 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 11099665 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 11099665 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 245426 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 245426 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180938 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 180938 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1169972 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1169972 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9281129 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 9281129 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3644210 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 3644210 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 784086 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 784086 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 516703 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164407 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 9281129 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 4814182 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 14776421 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 516703 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164407 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 9281129 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 4814182 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 14776421 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058507 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.043197 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.238136 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.238136 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073594 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073594 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261748 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261748 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.742237 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.742237 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058507 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073594 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.256009 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.131624 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038326 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058507 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073594 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.256009 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.131624 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34449.630939 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32155.291958 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3562.670622 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3562.670622 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1632.266301 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1632.266301 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 794666.333333 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 794666.333333 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48995.832926 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48995.832926 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34744.924865 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34744.924865 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35288.754773 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35288.754773 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 573.814646 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 573.814646 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 37013.914607 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31040.852396 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34449.630939 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34744.924865 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38387.371026 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 37013.914607 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches 44195 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 1595582 # number of writebacks
system.cpu0.l2cache.writebacks::total 1595582 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 11 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 92 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9447 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 9447 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 778 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 778 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 11 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 92 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10225 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 10340 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 11 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 92 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10225 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 10340 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 19792 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9527 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 29319 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 781759 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 245426 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 245426 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 180938 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 180938 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269166 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 269166 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 683024 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 683024 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 953085 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 953085 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 581976 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 581976 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 19792 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9527 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 683024 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1222251 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 1934594 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 19792 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9527 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 683024 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1222251 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 781759 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2716353 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72934 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 95209 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 272683000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 768369000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38385674547 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4516919997 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4516919997 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2779143996 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2779143996 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2017999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2017999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10852711499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10852711499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19633488000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19633488000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27859151994 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27859151994 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19308557500 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19308557500 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 272683000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19633488000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38711863493 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 59113720493 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 495686000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 272683000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19633488000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38711863493 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38385674547 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 97499395040 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3849707000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8268091500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3849707000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8268091500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.230062 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.230062 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073593 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261534 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261534 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.742235 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.742235 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130924 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.183830 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 30377137 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15497883 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2826 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 666100 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 666086 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 826394 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 13852976 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 22275 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 22275 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5277668 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 11102490 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1369040 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 998456 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 452524 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330100 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 496609 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1203701 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1179860 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9281130 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4723846 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 838465 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 784086 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 27947466 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17813968 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 344869 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1089699 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 47196002 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1191298304 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 667170422 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1315256 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4133624 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1863917606 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 5747559 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 110232304 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 21648150 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.044453 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.206103 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 20685836 95.55% 95.55% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 962300 4.45% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 21648150 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 30255355989 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 202143120 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 14002739292 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 7861824025 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 180564794 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 573087816 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 142890193 # Number of BP lookups
system.cpu1.branchPred.condPredicted 101173603 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6378415 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 107083119 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 74895456 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 69.941422 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 16732142 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 1061167 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 3812146 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2601182 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1210964 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 435637 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 301450 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 301450 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14052 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94528 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 301450 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 301450 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 301450 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 108580 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 107036 98.58% 98.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1312 1.21% 99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 57 0.05% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.06% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 74 0.07% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 108580 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -588118056 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -588118056 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -588118056 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 94528 87.06% 87.06% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 14052 12.94% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 108580 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 301450 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 301450 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108580 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108580 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 410030 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 92214946 # DTB read hits
system.cpu1.dtb.read_misses 251350 # DTB read misses
system.cpu1.dtb.write_hits 79863458 # DTB write hits
system.cpu1.dtb.write_misses 50100 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 41485 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1017 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8355 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11459 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 92466296 # DTB read accesses
system.cpu1.dtb.write_accesses 79913558 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 172078404 # DTB hits
system.cpu1.dtb.misses 301450 # DTB misses
system.cpu1.dtb.accesses 172379854 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 68405 # Table walker walks requested
system.cpu1.itb.walker.walksLong 68405 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 536 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57692 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 68405 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 68405 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 68405 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 58228 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 52664 90.44% 90.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 3935 6.76% 97.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 14 0.02% 97.23% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 1454 2.50% 99.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 63 0.11% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 12 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 10 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 58228 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -588816556 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -588816556 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -588816556 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 57692 99.08% 99.08% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 536 0.92% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 58228 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68405 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68405 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58228 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58228 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 126633 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 253981708 # ITB inst hits
system.cpu1.itb.inst_misses 68405 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 29878 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 186858 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 254050113 # ITB inst accesses
system.cpu1.itb.hits 253981708 # DTB hits
system.cpu1.itb.misses 68405 # DTB misses
system.cpu1.itb.accesses 254050113 # DTB accesses
system.cpu1.numPwrStateTransitions 29008 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 14504 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 3226000342.121070 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 122202778079.734619 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 4515 31.13% 31.13% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 9966 68.71% 99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.91% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11813587669000 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 14504 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 486863864876 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 973770006 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 467062034 # Number of instructions committed
system.cpu1.committedOps 549524480 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 49354477 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 5829 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 93580668477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.084884 # CPI: cycles per instruction
system.cpu1.ipc 0.479643 # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu 379758717 69.11% 69.11% # Class of committed instruction
system.cpu1.op_class_0::IntMult 1174710 0.21% 69.32% # Class of committed instruction
system.cpu1.op_class_0::IntDiv 62873 0.01% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc 42788 0.01% 69.34% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.op_class_0::MemRead 88942339 16.19% 85.53% # Class of committed instruction
system.cpu1.op_class_0::MemWrite 79543053 14.47% 100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::total 549524480 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 14504 # number of quiesce instructions executed
system.cpu1.tickCycles 754340504 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 219429502 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5584308 # number of replacements
system.cpu1.dcache.tags.tagsinuse 440.375822 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 163963779 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5584818 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 29.358840 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8377741807000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.375822 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.860109 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.860109 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 234 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 347150058 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 347150058 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 84821089 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 84821089 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 74565342 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 74565342 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 240493 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 240493 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 73857 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 73857 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1888770 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1888770 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1879546 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1879546 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 159460288 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 159460288 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 159700781 # number of overall hits
system.cpu1.dcache.overall_hits::total 159700781 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3413550 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3413550 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2348662 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2348662 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664960 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 664960 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 462804 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 462804 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186013 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 186013 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193851 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 193851 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 6225016 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 6225016 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6889976 # number of overall misses
system.cpu1.dcache.overall_misses::total 6889976 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52244752500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 52244752500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 43500498500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 43500498500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11517052000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 11517052000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2853085500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2853085500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4630433000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4630433000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2585500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2585500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 107262303000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 107262303000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 88234639 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 88234639 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 76914004 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 76914004 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 905453 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 905453 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 536661 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 536661 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074783 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2074783 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2073397 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2073397 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 165685304 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 165685304 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 166590757 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 166590757 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038687 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038687 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030536 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030536 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.734395 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.734395 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.862377 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.862377 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089654 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089654 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.093494 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.093494 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037571 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.037571 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041359 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.041359 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 5584335 # number of writebacks
system.cpu1.dcache.writebacks::total 5584335 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169267 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 169267 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 957224 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 957224 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44866 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44866 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 87 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 87 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1126549 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1126549 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1126549 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1126549 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3244283 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 3244283 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1391438 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1391438 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664681 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 664681 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462746 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 462746 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141147 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141147 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193764 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 193764 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 5098467 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 5098467 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5763148 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5763148 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17608 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33461 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45298654500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45298654500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 25106196000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 25106196000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14639124500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14639124500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11050641000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11050641000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1898988000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1898988000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4434665000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4434665000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2119500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2119500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81455491500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 81455491500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 96094616000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 96094616000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2936127500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2936127500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2936127500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2936127500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036769 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036769 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.734087 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.734087 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.862269 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.862269 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068030 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068030 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.093452 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.093452 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030772 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034595 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034595 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 9521452 # number of replacements
system.cpu1.icache.tags.tagsinuse 507.043038 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 244267020 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 9521964 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 25.653008 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8368158607000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.043038 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990318 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.990318 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 517099934 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 517099934 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 244267020 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 244267020 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 244267020 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 244267020 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 244267020 # number of overall hits
system.cpu1.icache.overall_hits::total 244267020 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 9521965 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 9521965 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 9521965 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 9521965 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 9521965 # number of overall misses
system.cpu1.icache.overall_misses::total 9521965 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96688620500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 96688620500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 96688620500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 96688620500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 96688620500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 96688620500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 253788985 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 253788985 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 253788985 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 253788985 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 253788985 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 253788985 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037519 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.037519 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037519 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.037519 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037519 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.037519 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10154.271781 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10154.271781 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 9521452 # number of writebacks
system.cpu1.icache.writebacks::total 9521452 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9521965 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 9521965 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 9521965 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 9521965 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 9521965 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 9521965 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91927638500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 91927638500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91927638500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 91927638500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91927638500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 91927638500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9070500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9070500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9070500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9070500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037519 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.037519 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037519 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.037519 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9654.271834 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7586302 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7586460 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 136 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 987804 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2406613 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13125.467163 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 13856134 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2421819 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 5.721375 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.086630 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.305413 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 234.798314 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.784258 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001653 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000873 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014331 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.801115 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14856 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 106 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 108 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 47 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 743 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6180 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6756 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 775 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.906738 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 519862521 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 519862521 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 578094 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 171981 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 750075 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3464322 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3464322 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 11639503 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 11639503 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 901874 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 901874 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8781698 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 8781698 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3023137 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 3023137 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191670 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 191670 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 578094 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 171981 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 8781698 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3925011 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 13456784 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 578094 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 171981 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 8781698 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3925011 # number of overall hits
system.cpu1.l2cache.overall_hits::total 13456784 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22586 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11050 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 33636 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 232349 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 232349 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193761 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 193761 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259533 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 259533 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 740267 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 740267 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1026659 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1026659 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 269262 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 269262 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22586 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11050 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 740267 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1286192 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 2060095 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22586 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11050 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 740267 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1286192 # number of overall misses
system.cpu1.l2cache.overall_misses::total 2060095 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 726971000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 437240000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1164211000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 947721000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 947721000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273329000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273329000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2036499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2036499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11444500498 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 11444500498 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24621036000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24621036000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 35849827996 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 35849827996 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 304696500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 304696500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 726971000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 437240000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24621036000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 47294328494 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 73079575494 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 726971000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 437240000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24621036000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 47294328494 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 73079575494 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 600680 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 183031 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 783711 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3464322 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3464322 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 11639503 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 11639503 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232349 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 232349 # number of UpgradeReq accesses(hits+misses)
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system.cpu1.l2cache.SCUpgradeReq_accesses::total 193761 # number of SCUpgradeReq accesses(hits+misses)
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system.cpu1.l2cache.ReadSharedReq_accesses::total 4049796 # number of ReadSharedReq accesses(hits+misses)
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system.cpu1.l2cache.InvalidateReq_accesses::total 460932 # number of InvalidateReq accesses(hits+misses)
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system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 183031 # number of overall (read+write) accesses
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system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.060372 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.042919 # miss rate for ReadReq accesses
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system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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system.cpu1.l2cache.ReadExReq_miss_rate::total 0.223464 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077743 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077743 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253509 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253509 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584169 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584169 # miss rate for InvalidateReq accesses
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system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.060372 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077743 # miss rate for demand accesses
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system.cpu1.l2cache.demand_miss_rate::total 0.132765 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037601 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.060372 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077743 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246813 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.132765 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39569.230769 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34612.052563 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4078.868426 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4078.868426 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1410.650234 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1410.650234 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678833 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678833 # average SCUpgradeFailReq miss latency
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system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44096.513730 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33259.669822 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33259.669822 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34918.924391 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34918.924391 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1131.598592 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1131.598592 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency
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system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32186.797131 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39569.230769 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33259.669822 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36770.815317 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35473.886153 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 49424 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1233392 # number of writebacks
system.cpu1.l2cache.writebacks::total 1233392 # number of writebacks
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system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 779944 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 779944 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 232349 # number of UpgradeReq MSHR misses
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system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193761 # number of SCUpgradeReq MSHR misses
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system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 740265 # number of ReadCleanReq MSHR misses
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system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 269262 # number of InvalidateReq MSHR misses
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system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 34084097769 # number of HardPFReq MSHR miss cycles
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system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4320296500 # number of UpgradeReq MSHR miss cycles
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system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2976407492 # number of SCUpgradeReq MSHR miss cycles
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1712499 # number of SCUpgradeFailReq MSHR miss cycles
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system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8961948498 # number of ReadExReq MSHR miss cycles
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system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20179405000 # number of ReadCleanReq MSHR miss cycles
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system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29636625496 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7368901000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7368901000 # number of InvalidateReq MSHR miss cycles
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system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369748000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20179405000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38598573994 # number of demand (read+write) MSHR miss cycles
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system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369748000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20179405000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38598573994 # number of overall MSHR miss cycles
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system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8310500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2795199500 # number of ReadReq MSHR uncacheable cycles
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system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8310500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2795199500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2803510000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042758 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.216988 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.216988 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077743 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253348 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253348 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584169 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584169 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132230 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182494 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 570833 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 570833 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 31064178 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15870221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 609547 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 609525 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 22 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 891069 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 14544906 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 15853 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 15853 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4703319 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 11641461 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1517999 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 982833 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 435735 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338791 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 485404 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1187635 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1166992 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9521965 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5021918 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 508584 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 460932 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28565571 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17994817 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387517 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1269560 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 48217465 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1218784704 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 696648341 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1464248 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4805440 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1921702733 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5371031 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 85625912 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 21661443 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.043843 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.204751 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 20711756 95.62% 95.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 949665 4.38% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 22 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 21661443 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 30930175985 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 161428122 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 14285968218 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 8290126100 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 204584802 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 668995768 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40347 # Transaction distribution
system.iobus.trans_dist::ReadResp 40347 # Transaction distribution
system.iobus.trans_dist::WriteReq 136610 # Transaction distribution
system.iobus.trans_dist::WriteResp 136610 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47638 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122572 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47658 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155679 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496829 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 41998503 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 312000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25719009 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 34474500 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 569697884 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92693000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115612 # number of replacements
system.iocache.tags.tagsinuse 11.289058 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9127814531000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.847615 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.441443 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240476 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.465090 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705566 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1041036 # Number of tag accesses
system.iocache.tags.data_accesses 1041036 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses
system.iocache.demand_misses::total 115671 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115631 # number of overall misses
system.iocache.overall_misses::total 115671 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1683130463 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1688328963 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12860878921 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12860878921 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14544009384 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14549576884 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14544009384 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14549576884 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 188851.114430 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125784.136767 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125784.136767 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33720 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3566 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.455973 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237980463 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1241328963 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7515783412 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7515783412 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8753763875 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8757331375 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8753763875 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8757331375 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75708.962272 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1555997 # number of replacements
system.l2c.tags.tagsinuse 65230.630092 # Cycle average of tags in use
system.l2c.tags.total_refs 7273929 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1617589 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.496772 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 7807986500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 8906.310468 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.466536 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 9.611192 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3875.011018 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 9658.633081 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3787.473530 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 432.466953 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 495.764320 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3981.420883 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 15318.580710 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.135900 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000236 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000147 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.059128 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.147379 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057792 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.006599 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.007565 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.060752 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.233743 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.286101 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995340 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10605 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 254 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50733 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 57 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 363 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 10181 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4720 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 44382 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.161819 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003876 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.774124 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 80901066 # Number of tag accesses
system.l2c.tags.data_accesses 80901066 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2828973 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2828973 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 204859 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 171268 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 376127 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 49678 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 57164 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 106842 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57243 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 53868 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 111111 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12667 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5625 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 610867 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 589040 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292600 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12537 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4791 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 678625 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 607071 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 308630 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 3122453 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 131047 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 131317 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 262364 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 12667 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 610867 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 646283 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 292600 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12537 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4791 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 678625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 660939 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 308630 # number of demand (read+write) hits
system.l2c.demand_hits::total 3233564 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 12667 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5625 # number of overall hits
system.l2c.overall_hits::cpu0.inst 610867 # number of overall hits
system.l2c.overall_hits::cpu0.data 646283 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 292600 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12537 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4791 # number of overall hits
system.l2c.overall_hits::cpu1.inst 678625 # number of overall hits
system.l2c.overall_hits::cpu1.data 660939 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 308630 # number of overall hits
system.l2c.overall_hits::total 3233564 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 21060 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 26656 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 47716 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 518 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 636 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1154 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76722 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 60050 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 136772 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1834 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1415 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 72156 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 133347 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 250233 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2590 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2459 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 61640 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 144790 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 229898 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 900362 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 438466 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 125863 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 564329 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1834 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1415 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 72156 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 210069 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 250233 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2590 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2459 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 61640 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 204840 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 229898 # number of demand (read+write) misses
system.l2c.demand_misses::total 1037134 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1834 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1415 # number of overall misses
system.l2c.overall_misses::cpu0.inst 72156 # number of overall misses
system.l2c.overall_misses::cpu0.data 210069 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 250233 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2590 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2459 # number of overall misses
system.l2c.overall_misses::cpu1.inst 61640 # number of overall misses
system.l2c.overall_misses::cpu1.data 204840 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 229898 # number of overall misses
system.l2c.overall_misses::total 1037134 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 165743500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 162277500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 328021000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8669000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8803000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 17472000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 7005748000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5240435998 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 12246183998 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 169372000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 128340500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6167992000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 12302035500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 231186000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 216219500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5316209000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 13039902500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 99287989218 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 31523000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 29313000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 60836000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 169372000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 128340500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 6167992000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 19307783500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 231186000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 216219500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 5316209000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 18280338498 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 111534173216 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 169372000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 128340500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 6167992000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 19307783500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33104444764 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 231186000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 216219500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 5316209000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 18280338498 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 28612287454 # number of overall miss cycles
system.l2c.overall_miss_latency::total 111534173216 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 2828973 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2828973 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 225919 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 197924 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 423843 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 50196 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 57800 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 107996 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 133965 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 113918 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247883 # number of ReadExReq accesses(hits+misses)
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system.l2c.overall_avg_miss_latency::total 107540.754826 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 751 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 114190001 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 5436084068 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 17205479828 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191629001 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 4693018541 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 16230689731 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 101142417768 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 151031002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 114190001 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 5436084068 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 17205479828 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30601839845 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 205285501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191629001 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 4693018541 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 16230689731 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26313170250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 101142417768 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3477966008 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6312000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2478199000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 9282561008 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3477966008 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6312000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2478199000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 9282561008 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.093219 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.134678 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.112579 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010320 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011003 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.010686 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572702 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.527134 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.551760 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184563 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192553 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.223735 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.769896 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489397 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.682634 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.242775 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.242775 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3909047 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2292243 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 2625 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 90635 # Transaction distribution
system.membus.trans_dist::ReadResp 999620 # Transaction distribution
system.membus.trans_dist::WriteReq 38128 # Transaction distribution
system.membus.trans_dist::WriteResp 38128 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1272553 # Transaction distribution
system.membus.trans_dist::CleanEvict 289712 # Transaction distribution
system.membus.trans_dist::UpgradeReq 348270 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 267748 # Transaction distribution
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 152656 # Transaction distribution
system.membus.trans_dist::ReadExResp 136047 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 908985 # Transaction distribution
system.membus.trans_dist::InvalidateReq 669058 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122572 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24944 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4823028 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4970598 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238389 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238389 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5208987 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155679 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49888 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144251456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 144458411 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7283200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 151741611 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 583612 # Total snoops (count)
system.membus.snoopTraffic 163584 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2475487 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012229 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.109905 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2445215 98.78% 98.78% # Request fanout histogram
system.membus.snoop_fanout::1 30272 1.22% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2475487 # Request fanout histogram
system.membus.reqLayer0.occupancy 102607988 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 20962995 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8793410200 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5849158337 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45598905 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 12529275 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6783970 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2045593 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 207524 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 190768 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 16756 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 90637 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4878287 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38128 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38128 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 3994832 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 3079472 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 721673 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 374590 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1096263 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 301835 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 301835 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4787847 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 854297 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 826693 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9608901 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8808719 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18417620 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240252134 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 217815813 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 458067947 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2968837 # Total snoops (count)
system.toL2Bus.snoopTraffic 127024720 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 8725155 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.358566 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.483567 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5613365 64.34% 64.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3095034 35.47% 99.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 16756 0.19% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8725155 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9593262018 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2632911 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4411209152 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4336941336 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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