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|
---------- Begin Simulation Statistics ----------
sim_seconds 47.482239 # Number of seconds simulated
sim_ticks 47482239150000 # Number of ticks simulated
final_tick 47482239150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 126606 # Simulator instruction rate (inst/s)
host_op_rate 148916 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6789587746 # Simulator tick rate (ticks/s)
host_mem_usage 767628 # Number of bytes of host memory used
host_seconds 6993.39 # Real time elapsed on the host
sim_insts 885402765 # Number of instructions simulated
sim_ops 1041431052 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 88704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 71680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 8153920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 42330888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 14734656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 154368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 137408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2906176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 14216400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 12693312 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 441664 # Number of bytes read from this memory
system.physmem.bytes_read::total 95929176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 8153920 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2906176 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 11060096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 76090688 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 76111272 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1386 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1120 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 127405 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 661433 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 230229 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2412 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2147 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 45409 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 222144 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 198333 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6901 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1498919 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1188917 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1191491 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 171726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 891510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 310319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3251 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 61206 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 299405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 267328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9302 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2020317 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 171726 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 61206 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 232931 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1602508 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1602942 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1602508 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 171726 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 891943 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 310319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2894 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 61206 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 299405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 267328 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9302 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3623259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1498919 # Number of read requests accepted
system.physmem.writeReqs 1191491 # Number of write requests accepted
system.physmem.readBursts 1498919 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1191491 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 95891200 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 39616 # Total number of bytes read from write queue
system.physmem.bytesWritten 76109696 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 95929176 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 76111272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 619 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 217911 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 89027 # Per bank write bursts
system.physmem.perBankRdBursts::1 94433 # Per bank write bursts
system.physmem.perBankRdBursts::2 86611 # Per bank write bursts
system.physmem.perBankRdBursts::3 92371 # Per bank write bursts
system.physmem.perBankRdBursts::4 85965 # Per bank write bursts
system.physmem.perBankRdBursts::5 91989 # Per bank write bursts
system.physmem.perBankRdBursts::6 84150 # Per bank write bursts
system.physmem.perBankRdBursts::7 94780 # Per bank write bursts
system.physmem.perBankRdBursts::8 85741 # Per bank write bursts
system.physmem.perBankRdBursts::9 143775 # Per bank write bursts
system.physmem.perBankRdBursts::10 89074 # Per bank write bursts
system.physmem.perBankRdBursts::11 90853 # Per bank write bursts
system.physmem.perBankRdBursts::12 89498 # Per bank write bursts
system.physmem.perBankRdBursts::13 91267 # Per bank write bursts
system.physmem.perBankRdBursts::14 94459 # Per bank write bursts
system.physmem.perBankRdBursts::15 94307 # Per bank write bursts
system.physmem.perBankWrBursts::0 73359 # Per bank write bursts
system.physmem.perBankWrBursts::1 78327 # Per bank write bursts
system.physmem.perBankWrBursts::2 72063 # Per bank write bursts
system.physmem.perBankWrBursts::3 77110 # Per bank write bursts
system.physmem.perBankWrBursts::4 71233 # Per bank write bursts
system.physmem.perBankWrBursts::5 76219 # Per bank write bursts
system.physmem.perBankWrBursts::6 70290 # Per bank write bursts
system.physmem.perBankWrBursts::7 78154 # Per bank write bursts
system.physmem.perBankWrBursts::8 70631 # Per bank write bursts
system.physmem.perBankWrBursts::9 75804 # Per bank write bursts
system.physmem.perBankWrBursts::10 71232 # Per bank write bursts
system.physmem.perBankWrBursts::11 74262 # Per bank write bursts
system.physmem.perBankWrBursts::12 72932 # Per bank write bursts
system.physmem.perBankWrBursts::13 74472 # Per bank write bursts
system.physmem.perBankWrBursts::14 77093 # Per bank write bursts
system.physmem.perBankWrBursts::15 76033 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 28 # Number of times write queue was full causing retry
system.physmem.totGap 47482237279500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1498889 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1188917 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 923724 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 366189 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 46304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 33513 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 28479 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 26369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 23870 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 21021 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 18560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1922 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 878 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 355 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 308 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 261 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 16928 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 19684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 43592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 56076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 62915 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 66422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 68359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 72568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 74023 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 77349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 76686 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 79204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 77889 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 78555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 85240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 78371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 74036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 70191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 826 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 662 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 452 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 473 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 421 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 84 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 913839 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 188.217382 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 115.370572 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 246.881339 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 545143 59.65% 59.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 181104 19.82% 79.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 60696 6.64% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 30627 3.35% 89.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 20207 2.21% 91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12827 1.40% 93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9718 1.06% 94.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 9868 1.08% 95.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 43649 4.78% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 913839 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 67807 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.096303 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 333.350943 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 67804 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 67807 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 67807 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.538219 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.057457 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.559402 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 64146 94.60% 94.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1206 1.78% 96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 504 0.74% 97.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 212 0.31% 97.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 312 0.46% 97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 493 0.73% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 138 0.20% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 37 0.05% 98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 37 0.05% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 40 0.06% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 31 0.05% 99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 23 0.03% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 428 0.63% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 42 0.06% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 41 0.06% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 38 0.06% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 18 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 4 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 20 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 67807 # Writes before turning the bus around for reads
system.physmem.totQLat 45254251156 # Total ticks spent queuing
system.physmem.totMemAccLat 73347376156 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 7491500000 # Total ticks spent in databus transfers
system.physmem.avgQLat 30203.73 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 48953.73 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.02 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.02 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing
system.physmem.readRowHits 1205783 # Number of row buffer hits during reads
system.physmem.writeRowHits 567891 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 47.75 # Row buffer hit rate for writes
system.physmem.avgGap 17648699.37 # Average gap between requests
system.physmem.pageHitRate 66.00 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3440351880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1877176125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5610742800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3866972400 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1186805359620 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27448283421000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31751192752785 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.696261 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45662122488643 # Time in different power states
system.physmem_0.memoryStateTime::REF 1585536160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 234575955107 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3468270960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1892409750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 6075934800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3839134320 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1190698585875 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27444868310250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31752151374915 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.716450 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45656375341719 # Time in different power states
system.physmem_1.memoryStateTime::REF 1585536160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 240323289781 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 141674450 # Number of BP lookups
system.cpu0.branchPred.condPredicted 99862421 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6468001 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 105068912 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 76755781 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.052799 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 16951451 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1146227 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 285287 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 285287 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10160 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74871 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 285287 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 285287 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 285287 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 85031 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19876.756712 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18427.446368 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 12146.929549 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 81330 95.65% 95.65% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3040 3.58% 99.22% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 313 0.37% 99.59% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 238 0.28% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 17 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 85031 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 74871 88.05% 88.05% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10160 11.95% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 85031 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 285287 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 285287 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85031 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85031 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 370318 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 92463041 # DTB read hits
system.cpu0.dtb.read_misses 237707 # DTB read misses
system.cpu0.dtb.write_hits 80598198 # DTB write hits
system.cpu0.dtb.write_misses 47580 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 37525 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1680 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 10312 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 10309 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 92700748 # DTB read accesses
system.cpu0.dtb.write_accesses 80645778 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 173061239 # DTB hits
system.cpu0.dtb.misses 285287 # DTB misses
system.cpu0.dtb.accesses 173346526 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 62168 # Table walker walks requested
system.cpu0.itb.walker.walksLong 62168 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 557 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49936 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 62168 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 62168 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 62168 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 50493 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 22007.793159 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 20271.994764 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 13773.268921 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 46934 92.95% 92.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 2907 5.76% 98.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 206 0.41% 99.12% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 384 0.76% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.02% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 12 0.02% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 50493 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 49936 98.90% 98.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 557 1.10% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 50493 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62168 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62168 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50493 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50493 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 112661 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 254201587 # ITB inst hits
system.cpu0.itb.inst_misses 62168 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 26890 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 207950 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 254263755 # ITB inst accesses
system.cpu0.itb.hits 254201587 # DTB hits
system.cpu0.itb.misses 62168 # DTB misses
system.cpu0.itb.accesses 254263755 # DTB accesses
system.cpu0.numCycles 1026940097 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 473675073 # Number of instructions committed
system.cpu0.committedOps 555986446 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 46253045 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 4767 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93938653200 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.168026 # CPI: cycles per instruction
system.cpu0.ipc 0.461249 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 15947 # number of quiesce instructions executed
system.cpu0.tickCycles 756887334 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 270052763 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 5859905 # number of replacements
system.cpu0.dcache.tags.tagsinuse 507.688861 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 164189310 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5860417 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.016660 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.688861 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991580 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.991580 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 349055381 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 349055381 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 84695912 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 84695912 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 74803438 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 74803438 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 285827 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 285827 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 206325 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 206325 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1857926 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1857926 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1831957 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1831957 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 159499350 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 159499350 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 159785177 # number of overall hits
system.cpu0.dcache.overall_hits::total 159785177 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3661656 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3661656 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2387103 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2387103 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 659778 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 659778 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 802996 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 802996 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167218 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 167218 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191201 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 191201 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 6048759 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 6048759 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6708537 # number of overall misses
system.cpu0.dcache.overall_misses::total 6708537 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54989546000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 54989546000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45746153500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 45746153500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55227374500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 55227374500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2454584500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2454584500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4061452500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4061452500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2247500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2247500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 100735699500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 100735699500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 100735699500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 100735699500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88357568 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 88357568 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77190541 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77190541 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 945605 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 945605 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1009321 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1009321 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2025144 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2025144 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023158 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2023158 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 165548109 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 165548109 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 166493714 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 166493714 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041441 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.041441 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030925 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.030925 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.697731 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.697731 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.795580 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.795580 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082571 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082571 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094506 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094506 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036538 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.036538 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040293 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.040293 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15017.671239 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15017.671239 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.879187 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.879187 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 68776.649572 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 68776.649572 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14678.949037 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14678.949037 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21241.795283 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21241.795283 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16653.944966 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16653.944966 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15016.045898 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15016.045898 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 3953843 # number of writebacks
system.cpu0.dcache.writebacks::total 3953843 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 461349 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 461349 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 989528 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 989528 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 101 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43137 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43137 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 40 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1450877 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1450877 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1450877 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1450877 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3200307 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3200307 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1397575 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1397575 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 654192 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 654192 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 802895 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 802895 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124081 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124081 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191161 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 191161 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4597882 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4597882 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5252074 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5252074 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32791 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65643 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43347515000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43347515000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25679741500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25679741500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14396564000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14396564000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54417843000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54417843000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1641270500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1641270500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3869107000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3869107000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2035000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2035000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69027256500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 69027256500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83423820500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 83423820500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5925160000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5925160000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5714063000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5714063000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11639223000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11639223000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036220 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036220 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018106 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018106 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.691824 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.691824 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.795480 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.795480 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061270 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061270 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094486 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094486 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031545 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031545 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13544.798983 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13544.798983 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18374.499759 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18374.499759 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22006.634138 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22006.634138 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 67777.035602 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 67777.035602 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13227.411933 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13227.411933 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20240.043733 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20240.043733 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15012.837759 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15012.837759 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15883.976597 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15883.976597 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180694.702815 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180694.702815 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173933.489590 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173933.489590 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177310.954710 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177310.954710 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 10143465 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.926573 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 243844472 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 10143977 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 24.038350 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 29838959000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926573 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 518120904 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 518120904 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 243844472 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 243844472 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 243844472 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 243844472 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 243844472 # number of overall hits
system.cpu0.icache.overall_hits::total 243844472 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 10143987 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 10143987 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 10143987 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 10143987 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 10143987 # number of overall misses
system.cpu0.icache.overall_misses::total 10143987 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100406017500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 100406017500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 100406017500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 100406017500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 100406017500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 100406017500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 253988459 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 253988459 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 253988459 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 253988459 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 253988459 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 253988459 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039939 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.039939 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039939 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.039939 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039939 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.039939 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.082233 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.082233 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9898.082233 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9898.082233 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10143987 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10143987 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 10143987 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10143987 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 10143987 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10143987 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95334024500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 95334024500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95334024500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 95334024500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95334024500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 95334024500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039939 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.039939 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.039939 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9398.082283 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7957449 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7958709 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 1099 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1036699 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2852729 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16231.938482 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 28072062 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2868819 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 9.785233 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 27361359000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 6837.547665 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 84.005962 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.461189 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5084.590207 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3169.997386 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 963.336073 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.417331 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005127 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005643 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.310339 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.193481 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058797 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.990719 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1316 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 636 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1121 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2596 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5686 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5177 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080322 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id
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system.cpu0.l2cache.Writeback_hits::total 3953840 # number of Writeback hits
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system.cpu0.l2cache.InvalidateReq_hits::total 184784 # number of InvalidateReq hits
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system.cpu0.l2cache.InvalidateReq_misses::total 616671 # number of InvalidateReq misses
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system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 254237500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24450345500 # number of overall miss cycles
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system.cpu0.l2cache.ReadReq_accesses::total 658612 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 3953841 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 3953841 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236083 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 236083 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191155 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 191155 # number of SCUpgradeReq accesses(hits+misses)
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system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1172952 # number of ReadExReq accesses(hits+misses)
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system.cpu0.l2cache.ReadCleanReq_accesses::total 10143986 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3978241 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 3978241 # number of ReadSharedReq accesses(hits+misses)
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system.cpu0.l2cache.InvalidateReq_accesses::total 801455 # number of InvalidateReq accesses(hits+misses)
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system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048486 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.028206 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
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system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.573281 # miss rate for UpgradeReq accesses
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system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079739 # miss rate for ReadCleanReq accesses
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system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34240.740741 # average ReadReq miss latency
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system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21721.139779 # average UpgradeReq miss latency
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system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu0.l2cache.CleanEvict_mshr_misses::total 115899 # number of CleanEvict MSHR misses
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system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 117935 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209670500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 501095000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33786234533 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33786234533 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2742370498 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2742370498 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2416828000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2416828000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1703998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1703998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10773413498 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10773413498 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19596844500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19596844500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27840391991 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27840391991 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 48183450000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 48183450000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209670500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19596844500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38613805489 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 58711744989 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209670500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19596844500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38613805489 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33786234533 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 92497979522 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5662672500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10022117000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5467648500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5467648500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11130321000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15489765500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028205 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.573281 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.573281 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.821857 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821857 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217168 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217168 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079739 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256125 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256125 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.769439 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.769439 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247254 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131699 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247254 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178383 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26975.398363 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45363.741930 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20262.523814 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20262.523814 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15383.814337 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15383.814337 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 283999.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 283999.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42293.793764 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42293.793764 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24227.493856 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27323.244934 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27323.244934 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 78134.775269 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 78134.775269 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27943.350118 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32502.371679 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172689.838675 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117792.238167 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166432.743821 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166432.743821 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169558.383986 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 131341.548311 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 878258 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 15087550 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32852 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 7538926 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 15047066 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 979875 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 473443 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 345382 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 491005 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1529585 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1182209 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10143987 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6286308 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 908183 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 801455 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30533828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18915495 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 338792 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1107688 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 50895803 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 652561728 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 589425738 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1225096 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4043800 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1247256362 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 11033818 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 44172113 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.260955 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.439155 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 32645184 73.90% 73.90% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 11526929 26.10% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 44172113 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 20686801483 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 184431489 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 15296388050 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 8393036752 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 185661487 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 602239946 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 126920633 # Number of BP lookups
system.cpu1.branchPred.condPredicted 90998639 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5685011 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 95306954 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 70103943 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 73.555958 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 14523133 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 944517 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 273163 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 273163 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10101 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83297 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 273163 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 273163 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 273163 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 93398 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20769.759524 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.534327 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16072.129923 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 92090 98.60% 98.60% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1102 1.18% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 44 0.05% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 68 0.07% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 64 0.07% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 93398 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -1497259648 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1497259648 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1497259648 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 83297 89.18% 89.18% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 10101 10.82% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 93398 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 273163 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 273163 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93398 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93398 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 366561 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 80454143 # DTB read hits
system.cpu1.dtb.read_misses 224980 # DTB read misses
system.cpu1.dtb.write_hits 71458601 # DTB write hits
system.cpu1.dtb.write_misses 48183 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 37844 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 998 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 7832 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11981 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 80679123 # DTB read accesses
system.cpu1.dtb.write_accesses 71506784 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 151912744 # DTB hits
system.cpu1.dtb.misses 273163 # DTB misses
system.cpu1.dtb.accesses 152185907 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 69906 # Table walker walks requested
system.cpu1.itb.walker.walksLong 69906 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 595 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61795 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 69906 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 69906 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 69906 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 62390 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 23626.751082 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21282.847568 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 17788.570372 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 60952 97.70% 97.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1278 2.05% 99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.13% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 62390 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1498102148 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1498102148 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1498102148 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 61795 99.05% 99.05% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 595 0.95% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 62390 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69906 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69906 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62390 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62390 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 132296 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 226287653 # ITB inst hits
system.cpu1.itb.inst_misses 69906 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 26941 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 214530 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 226357559 # ITB inst accesses
system.cpu1.itb.hits 226287653 # DTB hits
system.cpu1.itb.misses 69906 # DTB misses
system.cpu1.itb.accesses 226357559 # DTB accesses
system.cpu1.numCycles 843613035 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 411727692 # Number of instructions committed
system.cpu1.committedOps 485444606 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 45963671 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 5033 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 94121734017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.048959 # CPI: cycles per instruction
system.cpu1.ipc 0.488053 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 5855 # number of quiesce instructions executed
system.cpu1.tickCycles 670689322 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 172923713 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements 4998697 # number of replacements
system.cpu1.dcache.tags.tagsinuse 442.736384 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 144280355 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 4999208 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 28.860643 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8387679361000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.736384 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.864720 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.864720 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 306336541 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 306336541 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 73634827 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 73634827 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 66559153 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 66559153 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 217159 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 217159 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 114949 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 114949 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1666179 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1666179 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1632337 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1632337 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 140193980 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 140193980 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 140411139 # number of overall hits
system.cpu1.dcache.overall_hits::total 140411139 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3169592 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3169592 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2202884 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2202884 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634590 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 634590 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446274 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 446274 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 155480 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 155480 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187648 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 187648 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5372476 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5372476 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6007066 # number of overall misses
system.cpu1.dcache.overall_misses::total 6007066 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46997405500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 46997405500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36924614000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 36924614000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13123924500 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 13123924500 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2384254000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2384254000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3955578000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 3955578000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3296000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3296000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 83922019500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 83922019500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 83922019500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 83922019500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 76804419 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 76804419 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 68762037 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 68762037 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 851749 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 851749 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 561223 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 561223 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1821659 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1821659 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1819985 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1819985 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 145566456 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 145566456 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 146418205 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 146418205 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041268 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.041268 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745043 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745043 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.795181 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.795181 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085351 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085351 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103104 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103104 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036907 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.036907 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041027 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.041027 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14827.588377 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14827.588377 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16761.942072 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16761.942072 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 29407.773027 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 29407.773027 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15334.795472 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15334.795472 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21079.777029 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21079.777029 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15620.734183 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15620.734183 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13970.550598 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13970.550598 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 3232302 # number of writebacks
system.cpu1.dcache.writebacks::total 3232302 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357442 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 357442 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 916671 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 916671 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 62 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 62 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39535 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39535 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 40 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1274113 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1274113 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1274113 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1274113 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2812150 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2812150 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1286213 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1286213 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634154 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 634154 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446212 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 446212 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115945 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115945 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187608 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 187608 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4098363 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4098363 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4732517 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4732517 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5214 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10217 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37676406000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37676406000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20748839500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20748839500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13118141500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13118141500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12673625000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 12673625000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1579299000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1579299000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3766730000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3766730000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3027000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3027000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58425245500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 58425245500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71543387000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 71543387000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 574067000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 574067000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 612660500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 612660500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1186727500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1186727500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036614 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036614 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018705 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018705 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.744532 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.744532 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.795071 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.795071 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063648 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063648 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103082 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103082 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028155 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028155 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032322 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032322 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13397.722739 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13397.722739 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16131.728959 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16131.728959 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20686.050234 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20686.050234 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 28402.698717 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 28402.698717 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13621.104834 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13621.104834 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20077.661933 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20077.661933 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14255.751748 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14255.751748 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15117.407291 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15117.407291 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110101.074031 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110101.074031 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 122458.624825 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 122458.624825 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116152.246256 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116152.246256 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 8492244 # number of replacements
system.cpu1.icache.tags.tagsinuse 506.981743 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 217573051 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 8492756 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 25.618663 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8375822912000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.981743 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 460624372 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 460624372 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 217573051 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 217573051 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 217573051 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 217573051 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 217573051 # number of overall hits
system.cpu1.icache.overall_hits::total 217573051 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 8492757 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 8492757 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 8492757 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 8492757 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 8492757 # number of overall misses
system.cpu1.icache.overall_misses::total 8492757 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 83328642500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 83328642500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 83328642500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 83328642500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 83328642500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 83328642500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 226065808 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 226065808 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 226065808 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 226065808 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 226065808 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 226065808 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037568 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.037568 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037568 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.037568 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037568 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.037568 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9811.730455 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9811.730455 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9811.730455 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9811.730455 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8492757 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 8492757 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 8492757 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 8492757 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 8492757 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 8492757 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 79082264500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 79082264500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 79082264500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 79082264500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 79082264500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 79082264500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8371000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8371000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8371000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8371000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037568 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.037568 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.037568 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9311.730513 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90010.752688 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90010.752688 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6929819 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6929951 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 118 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 828225 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2217454 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13495.655652 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 24120573 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2233034 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 10.801704 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 10014360255000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 5089.747096 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.528183 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 67.846494 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3761.982865 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3615.755476 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 887.795537 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.310654 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004427 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004141 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.229613 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.220688 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054187 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.823709 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14232 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 323 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5272 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5785 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2792 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077148 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.868652 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 454838713 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 454838713 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 490664 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168334 # number of ReadReq hits
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system.cpu1.l2cache.Writeback_hits::writebacks 3232300 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 3232300 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70185 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 70185 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33315 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 33315 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 851172 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 851172 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7787132 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 7787132 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2622380 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2622380 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 211432 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 211432 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 490664 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168334 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 7787132 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3473552 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 11919682 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 490664 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168334 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 7787132 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3473552 # number of overall hits
system.cpu1.l2cache.overall_hits::total 11919682 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11999 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9044 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 21043 # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 130491 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 130491 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154287 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 154287 # number of SCUpgradeReq misses
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system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 236022 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 236022 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 705624 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 705624 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939588 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 939588 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 233719 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 233719 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11999 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9044 # number of demand (read+write) misses
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system.cpu1.l2cache.overall_misses::cpu1.inst 705624 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1175610 # number of overall misses
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system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 460284000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 375161500 # number of ReadReq miss cycles
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system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2824238500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 2824238500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3183877499 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3183877499 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2927500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2927500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9419253499 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 9419253499 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19920417000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19920417000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29851836990 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29851836990 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 10546903000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 10546903000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 460284000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 375161500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19920417000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 39271090489 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 60026952989 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 460284000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 375161500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19920417000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 39271090489 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 60026952989 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 502663 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 177378 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 680041 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 3232302 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 3232302 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 200676 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 200676 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187602 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 187602 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1087194 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1087194 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8492756 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 8492756 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3561968 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3561968 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 445151 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 445151 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 502663 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 177378 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 8492756 # number of demand (read+write) accesses
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system.cpu1.l2cache.demand_accesses::total 13821959 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 502663 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 177378 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 8492756 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4649162 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 13821959 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050987 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.030944 # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.650257 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.650257 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.822417 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.822417 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.217093 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.217093 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.083085 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.083085 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.263783 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.263783 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.525033 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.525033 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050987 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.083085 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252865 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.137627 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050987 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.083085 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252865 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.137627 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41481.811146 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39701.824835 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21643.166962 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21643.166962 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20636.071082 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20636.071082 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 487916.666667 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 487916.666667 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39908.370826 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39908.370826 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28230.923268 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28230.923268 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31771.198642 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31771.198642 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45126.425323 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45126.425323 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41481.811146 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28230.923268 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33404.862573 # average overall miss latency
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system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41481.811146 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28230.923268 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33404.862573 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31555.316596 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 960235 # number of writebacks
system.cpu1.l2cache.writebacks::total 960235 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6240 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 6240 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 370 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 370 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6610 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 6614 # number of demand (read+write) MSHR hits
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system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6610 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 6614 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11999 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9041 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 21040 # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104712 # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total 104712 # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 691959 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 691959 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 130491 # number of UpgradeReq MSHR misses
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system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 154287 # number of SCUpgradeReq MSHR misses
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system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 233715 # number of InvalidateReq MSHR misses
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system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11999 # number of demand (read+write) MSHR misses
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system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11999 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9041 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 705623 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1169000 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 691959 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2587622 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5307 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10310 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 320879500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 709169500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28798715692 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28798715692 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2619056498 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2619056498 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2341678999 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2341678999 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2531500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2531500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7275794499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7275794499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15686656500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15686656500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24180303490 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24180303490 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 9143886000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 9143886000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 320879500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15686656500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31456097989 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 47851923989 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 320879500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15686656500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31456097989 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28798715692 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 76650639681 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7627000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 532300500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 539927500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 575129000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 575129000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7627000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1107429500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1115056500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030939 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.650257 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.650257 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.822417 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.822417 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211353 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211353 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.083085 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.263680 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.263680 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.525024 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.525024 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251443 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137149 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251443 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.187211 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33705.774715 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41619.107045 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20070.782644 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20070.782644 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15177.422589 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.422589 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 421916.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 421916.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31663.900997 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31663.900997 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22230.931390 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25745.144886 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25745.144886 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39124.087029 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39124.087029 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25242.843263 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29622.038954 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102090.621404 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101738.741285 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114956.825904 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 114956.825904 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 108390.868161 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108152.909796 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 900589 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 12966269 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 5003 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 6817398 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 13255066 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 909243 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 440871 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344666 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 456246 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1853750 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1095537 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8492756 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6090536 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 551879 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 445151 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25476691 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16156139 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 386266 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1103974 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 43123070 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 543542336 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511133259 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419024 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4021304 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1060115923 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 11712363 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 39696559 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.307834 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.461597 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 27476611 69.22% 69.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 12219948 30.78% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 39696559 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 17378215985 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 190636988 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 12741161217 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7401084853 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 208902970 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 601334453 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40366 # Transaction distribution
system.iobus.trans_dist::ReadResp 40366 # Transaction distribution
system.iobus.trans_dist::WriteReq 136635 # Transaction distribution
system.iobus.trans_dist::WriteResp 136635 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47764 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122698 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354002 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47784 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36259000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 569722386 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147920000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115594 # number of replacements
system.iocache.tags.tagsinuse 11.293777 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115610 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9174240356000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.830924 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.462853 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.466428 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705861 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040865 # Number of tag accesses
system.iocache.tags.data_accesses 1040865 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses
system.iocache.demand_misses::total 8924 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8884 # number of overall misses
system.iocache.overall_misses::total 8924 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1643383037 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1648578037 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12626572349 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12626572349 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1643383037 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1648947037 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1643383037 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1648947037 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 184982.331945 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 184797.448380 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118306.089770 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118306.089770 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 184776.673801 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 184776.673801 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 32047 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3474 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.224813 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106695 # number of writebacks
system.iocache.writebacks::total 106695 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199183037 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1202528037 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7290172349 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7290172349 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1199183037 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1202747037 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1199183037 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1202747037 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134982.331945 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 134797.448380 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68306.089770 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68306.089770 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1417273 # number of replacements
system.l2c.tags.tagsinuse 63778.929439 # Cycle average of tags in use
system.l2c.tags.total_refs 6059487 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1477461 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.101284 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 17721.105226 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.826880 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 142.018903 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5534.663770 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7879.546362 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8528.634482 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 234.293349 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 288.797420 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3403.637563 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 8415.757562 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11494.647922 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.270403 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002073 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002167 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.084452 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.120232 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.130137 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003575 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004407 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.051935 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.128414 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.175394 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.973189 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 9520 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 195 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50473 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 311 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 9149 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1751 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5310 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 43220 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.145264 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.002975 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.770157 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 72899096 # Number of tag accesses
system.l2c.tags.data_accesses 72899096 # Number of data accesses
system.l2c.Writeback_hits::writebacks 2396145 # number of Writeback hits
system.l2c.Writeback_hits::total 2396145 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 29304 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 31986 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 61290 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 6099 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 5707 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11806 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 163881 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 167785 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 331666 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5962 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3875 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 733621 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 590091 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 312280 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6619 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4964 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 660183 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 546610 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 303770 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 3167975 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5962 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3875 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 733621 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 753972 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 312280 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6619 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4964 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 660183 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 714395 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 303770 # number of demand (read+write) hits
system.l2c.demand_hits::total 3499641 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5962 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3875 # number of overall hits
system.l2c.overall_hits::cpu0.inst 733621 # number of overall hits
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system.l2c.overall_mshr_uncacheable_latency::total 14177043000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561367 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.584325 # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.410035 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166445 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202368 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.292574 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.292574 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20763.848676 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20748.656488 # average UpgradeReq mshr miss latency
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.859554 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20804.792992 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74998.374967 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 82445.049668 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80225.346258 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80567.388288 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average ReadSharedReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154689.304992 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84123.177283 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97112.990662 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149431.465360 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 97955.526684 # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152057.942203 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90897.846304 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 110548.279438 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 90388 # Transaction distribution
system.membus.trans_dist::ReadResp 903121 # Transaction distribution
system.membus.trans_dist::WriteReq 37855 # Transaction distribution
system.membus.trans_dist::WriteResp 37855 # Transaction distribution
system.membus.trans_dist::Writeback 1188917 # Transaction distribution
system.membus.trans_dist::CleanEvict 251117 # Transaction distribution
system.membus.trans_dist::UpgradeReq 423385 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 299485 # Transaction distribution
system.membus.trans_dist::UpgradeResp 111205 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 657294 # Transaction distribution
system.membus.trans_dist::ReadExResp 636531 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 812733 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122698 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5171308 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 5317856 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342726 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342726 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5660582 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47596 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 164770304 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 164975029 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7270144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 172245173 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 635192 # Total snoops (count)
system.membus.snoop_fanout::samples 3870084 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3870084 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3870084 # Request fanout histogram
system.membus.reqLayer0.occupancy 109645497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 19606499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8359681063 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 8175730132 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 229316266 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq 90390 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4911274 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 37855 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 3585089 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1614217 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 477552 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 311291 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 788843 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 110 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1123188 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1123188 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4828127 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8913245 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6867211 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 15780456 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 273644474 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200023995 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 473668469 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3257042 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 13541412 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.121741 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.326987 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 11892865 87.83% 87.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1648547 12.17% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 13541412 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 8755054077 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 5258284103 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4190040133 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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