path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.694137                       # Number of seconds simulated
sim_ticks                                51694136923000                       # Number of ticks simulated
final_tick                               51694136923000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 173196                       # Simulator instruction rate (inst/s)
host_op_rate                                   203514                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9441127725                       # Simulator tick rate (ticks/s)
host_mem_usage                                 675004                       # Number of bytes of host memory used
host_seconds                                  5475.42                       # Real time elapsed on the host
sim_insts                                   948323287                       # Number of instructions simulated
sim_ops                                    1114322939                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       407232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       344384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10254400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         100902664                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        404352                       # Number of bytes read from this memory
system.physmem.bytes_read::total            112313032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10254400                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10254400                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     94405184                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          94425764                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6363                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5381                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             160225                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1576617                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6318                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1754904                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1475081                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1477654                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7878                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6662                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               198367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1951917                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7822                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2172645                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          198367                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             198367                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1826226                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1826624                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1826226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7878                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6662                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              198367                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1952315                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7822                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3999270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1754904                       # Number of read requests accepted
system.physmem.writeReqs                      1477654                       # Number of write requests accepted
system.physmem.readBursts                     1754904                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1477654                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                112259136                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     54720                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  94423744                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 112313032                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               94425764                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      855                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2252                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         146151                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              109407                       # Per bank write bursts
system.physmem.perBankRdBursts::1              112864                       # Per bank write bursts
system.physmem.perBankRdBursts::2              109220                       # Per bank write bursts
system.physmem.perBankRdBursts::3              104188                       # Per bank write bursts
system.physmem.perBankRdBursts::4              106449                       # Per bank write bursts
system.physmem.perBankRdBursts::5              113846                       # Per bank write bursts
system.physmem.perBankRdBursts::6              104146                       # Per bank write bursts
system.physmem.perBankRdBursts::7              106564                       # Per bank write bursts
system.physmem.perBankRdBursts::8               99467                       # Per bank write bursts
system.physmem.perBankRdBursts::9              160932                       # Per bank write bursts
system.physmem.perBankRdBursts::10             104576                       # Per bank write bursts
system.physmem.perBankRdBursts::11             109948                       # Per bank write bursts
system.physmem.perBankRdBursts::12             102336                       # Per bank write bursts
system.physmem.perBankRdBursts::13             105581                       # Per bank write bursts
system.physmem.perBankRdBursts::14              99543                       # Per bank write bursts
system.physmem.perBankRdBursts::15             104982                       # Per bank write bursts
system.physmem.perBankWrBursts::0               93507                       # Per bank write bursts
system.physmem.perBankWrBursts::1               95050                       # Per bank write bursts
system.physmem.perBankWrBursts::2               93111                       # Per bank write bursts
system.physmem.perBankWrBursts::3               91031                       # Per bank write bursts
system.physmem.perBankWrBursts::4               92702                       # Per bank write bursts
system.physmem.perBankWrBursts::5               96804                       # Per bank write bursts
system.physmem.perBankWrBursts::6               89915                       # Per bank write bursts
system.physmem.perBankWrBursts::7               93502                       # Per bank write bursts
system.physmem.perBankWrBursts::8               87351                       # Per bank write bursts
system.physmem.perBankWrBursts::9               94209                       # Per bank write bursts
system.physmem.perBankWrBursts::10              90719                       # Per bank write bursts
system.physmem.perBankWrBursts::11              94851                       # Per bank write bursts
system.physmem.perBankWrBursts::12              89273                       # Per bank write bursts
system.physmem.perBankWrBursts::13              92330                       # Per bank write bursts
system.physmem.perBankWrBursts::14              88747                       # Per bank write bursts
system.physmem.perBankWrBursts::15              92269                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
system.physmem.totGap                    51694135218000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1754889                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1475081                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1420187                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    327570                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       933                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       327                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       534                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       776                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       878                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      379                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      176                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      124                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       46                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    15753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    18367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    69542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    87805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    88303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    88136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    87821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    90771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    91285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    93842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    92895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    93403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    89996                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    90062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   102154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    88485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    90293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    86850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      503                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       688077                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      300.376987                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.587339                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     327.638975                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         270609     39.33%     39.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       164654     23.93%     63.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        63521      9.23%     72.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        36566      5.31%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        27027      3.93%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        18739      2.72%     84.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14736      2.14%     86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        13602      1.98%     88.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        78623     11.43%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         688077                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         86230                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.341007                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      270.950677                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          86227    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           86230                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         86230                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.109718                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.738195                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        5.845815                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           83739     97.11%     97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             148      0.17%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             433      0.50%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             182      0.21%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             327      0.38%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             491      0.57%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             146      0.17%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              35      0.04%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              38      0.04%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              19      0.02%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              25      0.03%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              26      0.03%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             445      0.52%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              41      0.05%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              34      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              31      0.04%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            32      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             8      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           86230                       # Writes before turning the bus around for reads
system.physmem.totQLat                    26659687931                       # Total ticks spent queuing
system.physmem.totMemAccLat               59548106681                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8770245000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15198.94                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33948.94                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.17                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.17                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1434287                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1107055                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.77                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.03                       # Row buffer hit rate for writes
system.physmem.avgGap                     15991711.59                       # Average gap between requests
system.physmem.pageHitRate                      78.69                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2644873560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1443135375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6760088400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4831630560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1310236671105                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29867151449250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34569477532170                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.731116                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49685803332014                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1726180820000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    282152299236                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2556988560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1395182250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6921447000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4728773520                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1305311169150                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29871472073250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34568795317650                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.717918                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49692977337193                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1726180820000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    274978307807                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               260235992                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182594285                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12181539                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            193306639                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               136184729                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.450104                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31573215                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2152291                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    586554                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                586554                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22200                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191198                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       586554                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          586554    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       586554                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       213398                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 26171.173113                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 22678.472578                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15672.620914                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       210833     98.80%     98.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2191      1.03%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          145      0.07%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          108      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           74      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           36      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       213398                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    -58656296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       -58656296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    -58656296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        191199     89.60%     89.60% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         22200     10.40%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       213399                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       586554                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       586554                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213399                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213399                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       799953                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    183104972                       # DTB read hits
system.cpu.dtb.read_misses                     484611                       # DTB read misses
system.cpu.dtb.write_hits                   162443368                       # DTB write hits
system.cpu.dtb.write_misses                    101943                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    80156                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       829                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15457                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23578                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                183589583                       # DTB read accesses
system.cpu.dtb.write_accesses               162545311                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         345548340                       # DTB hits
system.cpu.dtb.misses                          586554                       # DTB misses
system.cpu.dtb.accesses                     346134894                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    136663                       # Table walker walks requested
system.cpu.itb.walker.walksLong                136663                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       119012                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       136663                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          136663    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       136663                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       120092                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28563.884355                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 25001.850654                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17459.523046                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-32767        59524     49.57%     49.57% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-65535        57595     47.96%     97.52% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-98303         1126      0.94%     98.46% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::98304-131071         1581      1.32%     99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-163839           30      0.02%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::163840-196607          128      0.11%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-229375           37      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::229376-262143           22      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-294911           13      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::294912-327679           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-360447           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       120092                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    -59528796                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       -59528796    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    -59528796                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        119012     99.10%     99.10% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1080      0.90%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       120092                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136663                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       136663                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       120092                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       120092                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       256755                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    453103030                       # ITB inst hits
system.cpu.itb.inst_misses                     136663                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57609                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    364302                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                453239693                       # ITB inst accesses
system.cpu.itb.hits                         453103030                       # DTB hits
system.cpu.itb.misses                          136663                       # DTB misses
system.cpu.itb.accesses                     453239693                       # DTB accesses
system.cpu.numCycles                       2508251480                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   948323287                       # Number of instructions committed
system.cpu.committedOps                    1114322939                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      97332960                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7744                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100881187078                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.644933                       # CPI: cycles per instruction
system.cpu.ipc                               0.378081                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16604                       # number of quiesce instructions executed
system.cpu.tickCycles                      1790178903                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       718072577                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          11134622                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.957818                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           329114421                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11135134                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.556395                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4277412500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.957818                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1383337751                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1383337751                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    168246441                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168246441                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    151606594                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      151606594                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       524249                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        524249                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       336460                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       336460                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4018923                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4018923                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4332342                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4332342                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     319853035                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        319853035                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    320377284                       # number of overall hits
system.cpu.dcache.overall_hits::total       320377284                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6626426                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6626426                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4317891                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4317891                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1480828                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1480828                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1245336                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1245336                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       315150                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       315150                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10944317                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10944317                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     12425145                       # number of overall misses
system.cpu.dcache.overall_misses::total      12425145                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 107226750500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 107226750500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 152543350000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 152543350000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  58512566000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  58512566000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4781324500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4781324500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       115500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       115500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 259770100500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 259770100500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 259770100500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 259770100500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    174872867                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    174872867                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    155924485                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    155924485                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2005077                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2005077                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1581796                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1581796                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4334073                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4334073                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4332344                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4332344                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    330797352                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    330797352                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    332802429                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    332802429                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037893                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037893                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027692                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027692                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738539                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.738539                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787292                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.787292                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072715                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072715                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.033085                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.033085                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037335                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037335                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.686855                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.686855                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35328.207683                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35328.207683                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 46985.364592                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 46985.364592                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15171.583373                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15171.583373                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        57750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        57750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23735.615525                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23735.615525                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20906.806359                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20906.806359                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8552025                       # number of writebacks
system.cpu.dcache.writebacks::total           8552025                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       818755                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       818755                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904630                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1904630                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          150                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          150                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70014                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70014                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2723385                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2723385                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2723385                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2723385                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5807671                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5807671                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2413261                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2413261                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473332                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1473332                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1245186                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1245186                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       245136                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       245136                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8220932                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8220932                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9694264                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9694264                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  87900213000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  87900213000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80008628500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  80008628500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23654166000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23654166000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  57263274500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  57263274500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3335164500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3335164500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       113500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       113500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167908841500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 167908841500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191563007500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 191563007500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830486500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830486500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5692032500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5692032500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11522519000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11522519000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033211                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033211                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015477                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015477                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734801                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734801                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787198                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787198                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056560                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056560                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024852                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024852                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029129                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.029129                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15135.191542                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15135.191542                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33153.740312                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33153.740312                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16054.878330                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16054.878330                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 45987.727536                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 45987.727536                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13605.363961                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13605.363961                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        56750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        56750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20424.550586                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20424.550586                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19760.448808                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19760.448808                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173016.602867                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173016.602867                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168867.965111                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168867.965111                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170942.037801                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170942.037801                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24460747                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.918526                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           428265010                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24461259                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.507889                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26893649500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.918526                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999841                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999841                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         477187547                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        477187547                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    428265010                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       428265010                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     428265010                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        428265010                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    428265010                       # number of overall hits
system.cpu.icache.overall_hits::total       428265010                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24461269                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24461269                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24461269                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24461269                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24461269                       # number of overall misses
system.cpu.icache.overall_misses::total      24461269                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 325762917500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 325762917500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 325762917500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 325762917500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 325762917500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 325762917500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    452726279                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    452726279                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    452726279                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    452726279                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    452726279                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    452726279                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054031                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054031                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054031                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054031                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054031                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054031                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13317.498675                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13317.498675                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13317.498675                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13317.498675                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24461269                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24461269                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24461269                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24461269                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24461269                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24461269                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52295                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52295                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 301301649500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 301301649500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 301301649500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 301301649500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 301301649500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 301301649500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4042938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4042938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054031                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054031                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054031                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12317.498716                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12317.498716                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12317.498716                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1604829                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65266.156442                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           67107084                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1667914                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            40.234139                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      24502559000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 35881.888844                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   344.047128                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   429.269400                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8228.433015                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20382.518055                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.547514                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005250                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006550                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125556                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.311013                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995883                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          276                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62809                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          275                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          504                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2442                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5503                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54305                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958389                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        585371330                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       585371330                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       972902                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       283103                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1256005                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8552025                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8552025                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10723                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10723                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1658365                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1658365                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24353307                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24353307                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7197008                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      7197008                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       701735                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       701735                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       972902                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       283103                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24353307                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8855373                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34464685                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       972902                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       283103                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24353307                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8855373                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34464685                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6363                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5381                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        11744                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        38680                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        38680                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       705767                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       705767                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107959                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       107959                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       328857                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       328857                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       543451                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       543451                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6363                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5381                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       107959                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1034624                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1154327                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6363                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5381                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       107959                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1034624                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1154327                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    554201500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    467153500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1021355000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    576538000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    576538000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       110500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       110500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  57650400000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  57650400000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8792604500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   8792604500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  27746254000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  27746254000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  47759810000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  47759810000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    554201500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    467153500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   8792604500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  85396654000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  95210613500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    554201500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    467153500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   8792604500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  85396654000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  95210613500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       979265                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       288484                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1267749                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8552025                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8552025                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49403                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        49403                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2364132                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2364132                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24461266                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24461266                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7525865                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7525865                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1245186                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1245186                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       979265                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       288484                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24461266                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9889997                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35619012                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       979265                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       288484                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24461266                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9889997                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35619012                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018653                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.009264                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782948                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782948                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.298531                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.298531                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004413                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004413                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043697                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043697                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.436442                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.436442                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018653                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004413                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.104613                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032408                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018653                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004413                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.104613                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032408                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86815.368891                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86968.239101                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14905.325750                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14905.325750                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        55250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        55250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81684.748649                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81684.748649                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81443.923156                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81443.923156                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84371.790778                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84371.790778                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87882.458584                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87882.458584                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82481.492246                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82481.492246                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1368450                       # number of writebacks
system.cpu.l2cache.writebacks::total          1368450                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6363                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5381                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        11744                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1115                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1115                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38680                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        38680                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       705767                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       705767                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107956                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107956                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       328836                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       328836                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       543451                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       543451                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6363                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5381                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       107956                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1034603                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1154303                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6363                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5381                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       107956                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1034603                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1154303                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85994                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119701                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    413343500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    903915000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    803162500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    803162500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        90500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        90500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  50592730000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  50592730000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7712869000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7712869000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  24456668500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  24456668500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  42325300000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  42325300000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    413343500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7712869000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  75049398500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  83666182500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    413343500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7712869000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  75049398500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  83666182500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409182000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8641547500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5303781000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5303781000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10712963000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13945328500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009264                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782948                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782948                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.298531                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.298531                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004413                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043694                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043694                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.436442                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.436442                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032407                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032407                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76968.239101                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.283868                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.283868                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71684.748649                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71684.748649                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71444.560747                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74373.452116                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74373.452116                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77882.458584                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77882.458584                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160514.614677                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.121404                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157349.541638                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157349.541638                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158931.890336                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116501.353372                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        1796538                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33784448                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback     10027137                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict     27284097                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        49406                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        49408                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2364132                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2364132                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24461269                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7534742                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1351850                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1245186                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73484098                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33638682                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       696808                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2281485                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         110101073                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1568867840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1180529566                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2307872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7834120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2759539398                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2279468                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     74907361                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.047344                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.212374                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           71360927     95.27%     95.27% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            3546434      4.73%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       74907361                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    45104615497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1167000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36773946781                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15533347490                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     408345956                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1302236467                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           568973549                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115486                       # number of replacements
system.iocache.tags.tagsinuse               10.447136                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13147036427000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.519010                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928125                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219938                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433008                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652946                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
system.iocache.tags.data_accesses             1039893                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
system.iocache.overall_misses::total             8880                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1592056146                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1597125146                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12612249403                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12612249403                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1592056146                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1597476146                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1592056146                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1597476146                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 180096.849095                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 179917.218204                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118242.794223                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118242.794223                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 179895.962387                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 179895.962387                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         29944                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3370                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.885460                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1150056146                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1153275146                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279049403                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7279049403                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1150056146                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1153476146                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1150056146                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1153476146                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130096.849095                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 129917.218204                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68242.794223                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68242.794223                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               85994                       # Transaction distribution
system.membus.trans_dist::ReadResp             543407                       # Transaction distribution
system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
system.membus.trans_dist::Writeback           1475081                       # Transaction distribution
system.membus.trans_dist::CleanEvict           242486                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            39492                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           39494                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1248409                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1248409                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        457413                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5186779                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5316437                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341268                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341268                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5657705                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199510060                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    199680478                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7228736                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7228736                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               206909214                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3224                       # Total snoops (count)
system.membus.snoop_fanout::samples           3692024                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3692024    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3692024                       # Request fanout histogram
system.membus.reqLayer0.occupancy           102515000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5516000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9935800091                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         9380119144                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228946369                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------